git.gag.com Git - fw/openocd/blob - src/target/armv7a_cache_l2x.c

   1 /***************************************************************************
   2  *   Copyright (C) 2015 by Oleksij Rempel                                  *
   3  *   linux@rempel-privat.de                                                *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  17  ***************************************************************************/
  18
  19 #ifdef HAVE_CONFIG_H
  20 #include "config.h"
  21 #endif
  22
  23 #include "jtag/interface.h"
  24 #include "arm.h"
  25 #include "armv7a.h"
  26 #include "armv7a_cache.h"
  27 #include <helper/time_support.h>
  28 #include "target.h"
  29 #include "target_type.h"
  30 #include "smp.h"
  31
  32 static int arm7a_l2x_sanity_check(struct target *target)
  33 {
  34         struct armv7a_common *armv7a = target_to_armv7a(target);
  35         struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
  36                 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
  37
  38         if (target->state != TARGET_HALTED) {
  39                 LOG_ERROR("%s: target not halted", __func__);
  40                 return ERROR_TARGET_NOT_HALTED;
  41         }
  42
  43         if (!l2x_cache || !l2x_cache->base) {
  44                 LOG_DEBUG("l2x is not configured!");
  45                 return ERROR_FAIL;
  46         }
  47
  48         return ERROR_OK;
  49 }
  50 /*
  51  * clean and invalidate complete l2x cache
  52  */
  53 int arm7a_l2x_flush_all_data(struct target *target)
  54 {
  55         struct armv7a_common *armv7a = target_to_armv7a(target);
  56         struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
  57                 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
  58         uint32_t l2_way_val;
  59         int retval;
  60
  61         retval = arm7a_l2x_sanity_check(target);
  62         if (retval)
  63                 return retval;
  64
  65         l2_way_val = (1 << l2x_cache->way) - 1;
  66
  67         return target_write_phys_u32(target,
  68                         l2x_cache->base + L2X0_CLEAN_INV_WAY,
  69                         l2_way_val);
  70 }
  71
  72 int armv7a_l2x_cache_flush_virt(struct target *target, target_addr_t virt,
  73                                         uint32_t size)
  74 {
  75         struct armv7a_common *armv7a = target_to_armv7a(target);
  76         struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
  77                 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
  78         /* FIXME: different controllers have different linelen? */
  79         uint32_t i, linelen = 32;
  80         int retval;
  81
  82         retval = arm7a_l2x_sanity_check(target);
  83         if (retval)
  84                 return retval;
  85
  86         for (i = 0; i < size; i += linelen) {
  87                 target_addr_t pa, offs = virt + i;
  88
  89                 /* FIXME: use less verbose virt2phys? */
  90                 retval = target->type->virt2phys(target, offs, &pa);
  91                 if (retval != ERROR_OK)
  92                         goto done;
  93
  94                 retval = target_write_phys_u32(target,
  95                                 l2x_cache->base + L2X0_CLEAN_INV_LINE_PA, pa);
  96                 if (retval != ERROR_OK)
  97                         goto done;
  98         }
  99         return retval;
 100
 101 done:
 102         LOG_ERROR("d-cache invalidate failed");
 103
 104         return retval;
 105 }
 106
 107 static int armv7a_l2x_cache_inval_virt(struct target *target, target_addr_t virt,
 108                                         uint32_t size)
 109 {
 110         struct armv7a_common *armv7a = target_to_armv7a(target);
 111         struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
 112                 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
 113         /* FIXME: different controllers have different linelen */
 114         uint32_t i, linelen = 32;
 115         int retval;
 116
 117         retval = arm7a_l2x_sanity_check(target);
 118         if (retval)
 119                 return retval;
 120
 121         for (i = 0; i < size; i += linelen) {
 122                 target_addr_t pa, offs = virt + i;
 123
 124                 /* FIXME: use less verbose virt2phys? */
 125                 retval = target->type->virt2phys(target, offs, &pa);
 126                 if (retval != ERROR_OK)
 127                         goto done;
 128
 129                 retval = target_write_phys_u32(target,
 130                                 l2x_cache->base + L2X0_INV_LINE_PA, pa);
 131                 if (retval != ERROR_OK)
 132                         goto done;
 133         }
 134         return retval;
 135
 136 done:
 137         LOG_ERROR("d-cache invalidate failed");
 138
 139         return retval;
 140 }
 141
 142 static int armv7a_l2x_cache_clean_virt(struct target *target, target_addr_t virt,
 143                                         unsigned int size)
 144 {
 145         struct armv7a_common *armv7a = target_to_armv7a(target);
 146         struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
 147                 (armv7a->armv7a_mmu.armv7a_cache.outer_cache);
 148         /* FIXME: different controllers have different linelen */
 149         uint32_t i, linelen = 32;
 150         int retval;
 151
 152         retval = arm7a_l2x_sanity_check(target);
 153         if (retval)
 154                 return retval;
 155
 156         for (i = 0; i < size; i += linelen) {
 157                 target_addr_t pa, offs = virt + i;
 158
 159                 /* FIXME: use less verbose virt2phys? */
 160                 retval = target->type->virt2phys(target, offs, &pa);
 161                 if (retval != ERROR_OK)
 162                         goto done;
 163
 164                 retval = target_write_phys_u32(target,
 165                                 l2x_cache->base + L2X0_CLEAN_LINE_PA, pa);
 166                 if (retval != ERROR_OK)
 167                         goto done;
 168         }
 169         return retval;
 170
 171 done:
 172         LOG_ERROR("d-cache invalidate failed");
 173
 174         return retval;
 175 }
 176
 177 static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
 178         struct armv7a_cache_common *armv7a_cache)
 179 {
 180         struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache *)
 181                 (armv7a_cache->outer_cache);
 182
 183         if (armv7a_cache->info == -1) {
 184                 command_print(cmd, "cache not yet identified");
 185                 return ERROR_OK;
 186         }
 187
 188         command_print(cmd,
 189                       "L2 unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
 190                       l2x_cache->base, l2x_cache->way);
 191
 192         return ERROR_OK;
 193 }
 194
 195 static int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
 196 {
 197         struct armv7a_l2x_cache *l2x_cache;
 198         struct target_list *head;
 199
 200         struct armv7a_common *armv7a = target_to_armv7a(target);
 201         if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
 202                 LOG_ERROR("L2 cache was already initialised\n");
 203                 return ERROR_FAIL;
 204         }
 205
 206         l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
 207         l2x_cache->base = base;
 208         l2x_cache->way = way;
 209         armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
 210
 211         /*  initialize all targets in this cluster (smp target)
 212          *  l2 cache must be configured after smp declaration */
 213         foreach_smp_target(head, target->smp_targets) {
 214                 struct target *curr = head->target;
 215                 if (curr != target) {
 216                         armv7a = target_to_armv7a(curr);
 217                         if (armv7a->armv7a_mmu.armv7a_cache.outer_cache) {
 218                                 LOG_ERROR("smp target : cache l2 already initialized\n");
 219                                 return ERROR_FAIL;
 220                         }
 221                         armv7a->armv7a_mmu.armv7a_cache.outer_cache = l2x_cache;
 222                 }
 223         }
 224         return ERROR_OK;
 225 }
 226
 227 COMMAND_HANDLER(arm7a_l2x_cache_info_command)
 228 {
 229         struct target *target = get_current_target(CMD_CTX);
 230         struct armv7a_common *armv7a = target_to_armv7a(target);
 231         int retval;
 232
 233         retval = arm7a_l2x_sanity_check(target);
 234         if (retval)
 235                 return retval;
 236
 237         return arm7a_handle_l2x_cache_info_command(CMD,
 238                         &armv7a->armv7a_mmu.armv7a_cache);
 239 }
 240
 241 COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command)
 242 {
 243         struct target *target = get_current_target(CMD_CTX);
 244
 245         return arm7a_l2x_flush_all_data(target);
 246 }
 247
 248 COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd)
 249 {
 250         struct target *target = get_current_target(CMD_CTX);
 251         target_addr_t virt;
 252         uint32_t size;
 253
 254         if (CMD_ARGC == 0 || CMD_ARGC > 2)
 255                 return ERROR_COMMAND_SYNTAX_ERROR;
 256
 257         if (CMD_ARGC == 2)
 258                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
 259         else
 260                 size = 1;
 261
 262         COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
 263
 264         return armv7a_l2x_cache_flush_virt(target, virt, size);
 265 }
 266
 267 COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd)
 268 {
 269         struct target *target = get_current_target(CMD_CTX);
 270         target_addr_t virt;
 271         uint32_t size;
 272
 273         if (CMD_ARGC == 0 || CMD_ARGC > 2)
 274                 return ERROR_COMMAND_SYNTAX_ERROR;
 275
 276         if (CMD_ARGC == 2)
 277                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
 278         else
 279                 size = 1;
 280
 281         COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
 282
 283         return armv7a_l2x_cache_inval_virt(target, virt, size);
 284 }
 285
 286 COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd)
 287 {
 288         struct target *target = get_current_target(CMD_CTX);
 289         target_addr_t virt;
 290         uint32_t size;
 291
 292         if (CMD_ARGC == 0 || CMD_ARGC > 2)
 293                 return ERROR_COMMAND_SYNTAX_ERROR;
 294
 295         if (CMD_ARGC == 2)
 296                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], size);
 297         else
 298                 size = 1;
 299
 300         COMMAND_PARSE_ADDRESS(CMD_ARGV[0], virt);
 301
 302         return armv7a_l2x_cache_clean_virt(target, virt, size);
 303 }
 304
 305 /* FIXME: should we configure way size? or controller type? */
 306 COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd)
 307 {
 308         struct target *target = get_current_target(CMD_CTX);
 309         uint32_t base, way;
 310
 311         if (CMD_ARGC != 2)
 312                 return ERROR_COMMAND_SYNTAX_ERROR;
 313
 314         /* command_print(CMD, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
 315         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
 316         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
 317
 318         /* AP address is in bits 31:24 of DP_SELECT */
 319         return armv7a_l2x_cache_init(target, base, way);
 320 }
 321
 322 static const struct command_registration arm7a_l2x_cache_commands[] = {
 323         {
 324                 .name = "conf",
 325                 .handler = armv7a_l2x_cache_conf_cmd,
 326                 .mode = COMMAND_ANY,
 327                 .help = "configure l2x cache",
 328                 .usage = "<base_addr> <number_of_way>",
 329         },
 330         {
 331                 .name = "info",
 332                 .handler = arm7a_l2x_cache_info_command,
 333                 .mode = COMMAND_ANY,
 334                 .help = "print cache related information",
 335                 .usage = "",
 336         },
 337         {
 338                 .name = "flush_all",
 339                 .handler = arm7a_l2x_cache_flush_all_command,
 340                 .mode = COMMAND_ANY,
 341                 .help = "flush complete l2x cache",
 342                 .usage = "",
 343         },
 344         {
 345                 .name = "flush",
 346                 .handler = arm7a_l2x_cache_flush_virt_cmd,
 347                 .mode = COMMAND_ANY,
 348                 .help = "flush (clean and invalidate) l2x cache by virtual address offset and range size",
 349                 .usage = "<virt_addr> [size]",
 350         },
 351         {
 352                 .name = "inval",
 353                 .handler = arm7a_l2x_cache_inval_virt_cmd,
 354                 .mode = COMMAND_ANY,
 355                 .help = "invalidate l2x cache by virtual address offset and range size",
 356                 .usage = "<virt_addr> [size]",
 357         },
 358         {
 359                 .name = "clean",
 360                 .handler = arm7a_l2x_cache_clean_virt_cmd,
 361                 .mode = COMMAND_ANY,
 362                 .help = "clean l2x cache by virtual address address offset and range size",
 363                 .usage = "<virt_addr> [size]",
 364         },
 365         COMMAND_REGISTRATION_DONE
 366 };
 367
 368 const struct command_registration arm7a_l2x_cache_command_handler[] = {
 369         {
 370                 .name = "l2x",
 371                 .mode = COMMAND_ANY,
 372                 .help = "l2x cache command group",
 373                 .usage = "",
 374                 .chain = arm7a_l2x_cache_commands,
 375         },
 376         COMMAND_REGISTRATION_DONE
 377 };