1 /***************************************************************************
2 * Copyright (C) 2009 by David Brownell *
4 * Copyright (C) ST-Ericsson SA 2011 michel.jaouen@stericsson.com *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
20 ***************************************************************************/
25 #include <helper/replacements.h>
28 #include "arm_disassembler.h"
31 #include <helper/binarybuffer.h>
32 #include <helper/command.h>
38 #include "arm_opcodes.h"
40 #include "target_type.h"
42 static void armv7a_show_fault_registers(struct target *target)
44 uint32_t dfsr, ifsr, dfar, ifar;
45 struct armv7a_common *armv7a = target_to_armv7a(target);
46 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
49 retval = dpm->prepare(dpm);
50 if (retval != ERROR_OK)
53 /* ARMV4_5_MRC(cpnum, op1, r0, CRn, CRm, op2) */
55 /* c5/c0 - {data, instruction} fault status registers */
56 retval = dpm->instr_read_data_r0(dpm,
57 ARMV4_5_MRC(15, 0, 0, 5, 0, 0),
59 if (retval != ERROR_OK)
62 retval = dpm->instr_read_data_r0(dpm,
63 ARMV4_5_MRC(15, 0, 0, 5, 0, 1),
65 if (retval != ERROR_OK)
68 /* c6/c0 - {data, instruction} fault address registers */
69 retval = dpm->instr_read_data_r0(dpm,
70 ARMV4_5_MRC(15, 0, 0, 6, 0, 0),
72 if (retval != ERROR_OK)
75 retval = dpm->instr_read_data_r0(dpm,
76 ARMV4_5_MRC(15, 0, 0, 6, 0, 2),
78 if (retval != ERROR_OK)
81 LOG_USER("Data fault registers DFSR: %8.8" PRIx32
82 ", DFAR: %8.8" PRIx32, dfsr, dfar);
83 LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
84 ", IFAR: %8.8" PRIx32, ifsr, ifar);
87 /* (void) */ dpm->finish(dpm);
90 int armv7a_read_ttbcr(struct target *target)
92 struct armv7a_common *armv7a = target_to_armv7a(target);
93 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
95 int retval = dpm->prepare(dpm);
96 if (retval!=ERROR_OK) goto done;
97 /* MRC p15,0,<Rt>,c2,c0,2 ; Read CP15 Translation Table Base Control Register*/
98 retval = dpm->instr_read_data_r0(dpm,
99 ARMV4_5_MRC(15, 0, 0, 2, 0, 2),
101 if (retval!=ERROR_OK) goto done;
102 armv7a->armv7a_mmu.ttbr1_used = ((ttbcr & 0x7)!=0)? 1: 0;
103 armv7a->armv7a_mmu.ttbr0_mask = 7 << (32 -((ttbcr & 0x7)));
105 LOG_INFO("ttb1 %s ,ttb0_mask %x",
106 armv7a->armv7a_mmu.ttbr1_used ? "used":"not used",
107 armv7a->armv7a_mmu.ttbr0_mask);
109 if (armv7a->armv7a_mmu.ttbr1_used == 1)
111 LOG_INFO("SVC access above %x",
112 (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask));
113 armv7a->armv7a_mmu.os_border = 0xffffffff & armv7a->armv7a_mmu.ttbr0_mask;
117 /* fix me , default is hard coded LINUX border */
118 armv7a->armv7a_mmu.os_border = 0xc0000000;
126 /* method adapted to cortex A : reused arm v4 v5 method*/
127 int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
129 uint32_t first_lvl_descriptor = 0x0;
130 uint32_t second_lvl_descriptor = 0x0;
133 struct armv7a_common *armv7a = target_to_armv7a(target);
134 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
135 uint32_t ttb = 0; /* default ttb0 */
136 if (armv7a->armv7a_mmu.ttbr1_used == -1) armv7a_read_ttbcr(target);
137 if ((armv7a->armv7a_mmu.ttbr1_used) &&
138 (va > (0xffffffff & armv7a->armv7a_mmu.ttbr0_mask)))
143 retval = dpm->prepare(dpm);
144 if (retval != ERROR_OK)
147 /* MRC p15,0,<Rt>,c2,c0,ttb */
148 retval = dpm->instr_read_data_r0(dpm,
149 ARMV4_5_MRC(15, 0, 0, 2, 0, ttb),
151 retval = armv7a->armv7a_mmu.read_physical_memory(target,
152 (ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
153 4, 1, (uint8_t*)&first_lvl_descriptor);
154 if (retval != ERROR_OK)
156 first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)
157 &first_lvl_descriptor);
158 /* reuse armv4_5 piece of code, specific armv7a changes may come later */
159 LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
161 if ((first_lvl_descriptor & 0x3) == 0)
163 LOG_ERROR("Address translation failure");
164 return ERROR_TARGET_TRANSLATION_FAULT;
168 if ((first_lvl_descriptor & 0x3) == 2)
170 /* section descriptor */
171 cb = (first_lvl_descriptor & 0xc) >> 2;
172 *val = (first_lvl_descriptor & 0xfff00000) | (va & 0x000fffff);
176 if ((first_lvl_descriptor & 0x3) == 1)
178 /* coarse page table */
179 retval = armv7a->armv7a_mmu.read_physical_memory(target,
180 (first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
181 4, 1, (uint8_t*)&second_lvl_descriptor);
182 if (retval != ERROR_OK)
185 else if ((first_lvl_descriptor & 0x3) == 3)
187 /* fine page table */
188 retval = armv7a->armv7a_mmu.read_physical_memory(target,
189 (first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
190 4, 1, (uint8_t*)&second_lvl_descriptor);
191 if (retval != ERROR_OK)
195 second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)
196 &second_lvl_descriptor);
198 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
200 if ((second_lvl_descriptor & 0x3) == 0)
202 LOG_ERROR("Address translation failure");
203 return ERROR_TARGET_TRANSLATION_FAULT;
206 /* cacheable/bufferable is always specified in bits 3-2 */
207 cb = (second_lvl_descriptor & 0xc) >> 2;
209 if ((second_lvl_descriptor & 0x3) == 1)
211 /* large page descriptor */
212 *val = (second_lvl_descriptor & 0xffff0000) | (va & 0x0000ffff);
216 if ((second_lvl_descriptor & 0x3) == 2)
218 /* small page descriptor */
219 *val = (second_lvl_descriptor & 0xfffff000) | (va & 0x00000fff);
223 if ((second_lvl_descriptor & 0x3) == 3)
225 *val = (second_lvl_descriptor & 0xfffffc00) | (va & 0x000003ff);
229 /* should not happen */
230 LOG_ERROR("Address translation failure");
231 return ERROR_TARGET_TRANSLATION_FAULT;
238 /* V7 method VA TO PA */
239 int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
240 uint32_t *val, int meminfo)
242 int retval = ERROR_FAIL;
243 struct armv7a_common *armv7a = target_to_armv7a(target);
244 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
245 uint32_t virt = va & ~0xfff;
246 uint32_t NOS,NS,SH,INNER,OUTER;
248 retval = dpm->prepare(dpm);
249 if (retval != ERROR_OK)
251 /* mmu must be enable in order to get a correct translation */
252 /* use VA to PA CP15 register for conversion */
253 retval = dpm->instr_write_data_r0(dpm,
254 ARMV4_5_MCR(15, 0, 0, 7, 8, 0),
256 if (retval!=ERROR_OK) goto done;
257 retval = dpm->instr_read_data_r0(dpm,
258 ARMV4_5_MRC(15, 0, 0, 7, 4, 0),
260 /* decode memory attribute */
261 NOS = (*val >> 10) & 1; /* Not Outer shareable */
262 NS = (*val >> 9) & 1; /* Non secure */
263 SH = (*val >> 7 )& 1; /* shareable */
264 INNER = (*val >> 4) & 0x7;
265 OUTER = (*val >> 2) & 0x3;
267 if (retval!=ERROR_OK) goto done;
268 *val = (*val & ~0xfff) + (va & 0xfff);
270 LOG_WARNING("virt = phys : MMU disable !!");
273 LOG_INFO("%x : %x %s outer shareable %s secured",
275 NOS == 1 ? "not" : " ",
276 NS == 1 ? "not" :"");
278 case 0 : LOG_INFO("outer: Non-Cacheable");
280 case 1 : LOG_INFO("outer: Write-Back, Write-Allocate");
282 case 2 : LOG_INFO("outer: Write-Through, No Write-Allocate");
284 case 3 : LOG_INFO("outer: Write-Back, no Write-Allocate");
288 case 0 : LOG_INFO("inner: Non-Cacheable");
290 case 1 : LOG_INFO("inner: Strongly-ordered");
292 case 3 : LOG_INFO("inner: Device");
294 case 5 : LOG_INFO("inner: Write-Back, Write-Allocate");
296 case 6 : LOG_INFO("inner: Write-Through");
298 case 7 : LOG_INFO("inner: Write-Back, no Write-Allocate");
300 default: LOG_INFO("inner: %x ???",INNER);
310 static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ctx,
311 struct armv7a_cache_common *armv7a_cache)
313 if (armv7a_cache->ctype == -1)
315 command_print(cmd_ctx, "cache not yet identified");
319 command_print(cmd_ctx,
320 "D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
321 armv7a_cache->d_u_size.linelen,
322 armv7a_cache->d_u_size.associativity,
323 armv7a_cache->d_u_size.nsets,
324 armv7a_cache->d_u_size.cachesize);
326 command_print(cmd_ctx,
327 "I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
328 armv7a_cache->i_size.linelen,
329 armv7a_cache->i_size.associativity,
330 armv7a_cache->i_size.nsets,
331 armv7a_cache->i_size.cachesize);
336 static int _armv7a_flush_all_data(struct target *target)
338 struct armv7a_common *armv7a = target_to_armv7a(target);
339 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
340 struct armv7a_cachesize *d_u_size =
341 &(armv7a->armv7a_mmu.armv7a_cache.d_u_size);
342 int32_t c_way, c_index = d_u_size->index;
344 /* check that cache data is on at target halt */
345 if (!armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled)
347 LOG_INFO("flushed not performed :cache not on at target halt");
350 retval = dpm->prepare(dpm);
351 if (retval != ERROR_OK) goto done;
353 c_way = d_u_size->way;
355 uint32_t value = (c_index << d_u_size->index_shift)
356 | (c_way << d_u_size->way_shift);
358 //LOG_INFO ("%d %d %x",c_way,c_index,value);
359 retval = dpm->instr_write_data_r0(dpm,
360 ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
362 if (retval!= ERROR_OK) goto done;
366 } while (c_index >=0);
369 LOG_ERROR("flushed failed");
374 static int armv7a_flush_all_data( struct target * target)
376 int retval = ERROR_FAIL;
377 /* check that armv7a_cache is correctly identify */
378 struct armv7a_common *armv7a = target_to_armv7a(target);
379 if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1)
381 LOG_ERROR("trying to flush un-identified cache");
387 /* look if all the other target have been flushed in order to flush level
389 struct target_list *head;
392 while(head != (struct target_list*)NULL)
395 if ((curr->state == TARGET_HALTED))
396 { LOG_INFO("Wait flushing data l1 on core %d",curr->coreid);
397 retval = _armv7a_flush_all_data(curr);
402 else retval = _armv7a_flush_all_data(target);
407 /* L2 is not specific to armv7a a specific file is needed */
408 static int armv7a_l2x_flush_all_data(struct target * target)
411 #define L2X0_CLEAN_INV_WAY 0x7FC
412 int retval = ERROR_FAIL;
413 struct armv7a_common *armv7a = target_to_armv7a(target);
414 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache*)
415 (armv7a->armv7a_mmu.armv7a_cache.l2_cache);
416 uint32_t base = l2x_cache->base;
417 uint32_t l2_way = l2x_cache->way;
418 uint32_t l2_way_val = (1<<l2_way) -1;
419 retval = armv7a_flush_all_data(target);
420 if (retval!=ERROR_OK) return retval;
421 retval = target->type->write_phys_memory(target,
422 (uint32_t)(base+(uint32_t)L2X0_CLEAN_INV_WAY),
425 (uint8_t*)&l2_way_val);
429 static int armv7a_handle_l2x_cache_info_command(struct command_context *cmd_ctx,
430 struct armv7a_cache_common *armv7a_cache)
433 struct armv7a_l2x_cache *l2x_cache = (struct armv7a_l2x_cache*)
434 (armv7a_cache->l2_cache);
436 if (armv7a_cache->ctype == -1)
438 command_print(cmd_ctx, "cache not yet identified");
442 command_print(cmd_ctx,
443 "L1 D-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
444 armv7a_cache->d_u_size.linelen,
445 armv7a_cache->d_u_size.associativity,
446 armv7a_cache->d_u_size.nsets,
447 armv7a_cache->d_u_size.cachesize);
449 command_print(cmd_ctx,
450 "L1 I-Cache: linelen %i, associativity %i, nsets %i, cachesize %d KBytes",
451 armv7a_cache->i_size.linelen,
452 armv7a_cache->i_size.associativity,
453 armv7a_cache->i_size.nsets,
454 armv7a_cache->i_size.cachesize);
455 command_print(cmd_ctx, "L2 unified cache Base Address 0x%x, %d ways",
456 l2x_cache->base, l2x_cache->way);
463 int armv7a_l2x_cache_init(struct target *target, uint32_t base, uint32_t way)
465 struct armv7a_l2x_cache *l2x_cache;
466 struct target_list *head = target->head;
469 struct armv7a_common *armv7a = target_to_armv7a(target);
471 LOG_ERROR("not an armv7a target");
472 l2x_cache = calloc(1, sizeof(struct armv7a_l2x_cache));
473 l2x_cache->base = base;
474 l2x_cache->way = way;
475 /*LOG_INFO("cache l2 initialized base %x way %d",
476 l2x_cache->base,l2x_cache->way);*/
477 if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
479 LOG_INFO("cache l2 already initialized\n");
481 armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void*) l2x_cache;
482 /* initialize l1 / l2x cache function */
483 armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache
484 = armv7a_l2x_flush_all_data;
485 armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
486 armv7a_handle_l2x_cache_info_command;
487 /* initialize all target in this cluster (smp target)*/
488 /* l2 cache must be configured after smp declaration */
489 while(head != (struct target_list*)NULL)
494 armv7a = target_to_armv7a(curr);
495 if (armv7a->armv7a_mmu.armv7a_cache.l2_cache)
497 LOG_ERROR("smp target : cache l2 already initialized\n");
499 armv7a->armv7a_mmu.armv7a_cache.l2_cache = (void*) l2x_cache;
500 armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
501 armv7a_l2x_flush_all_data;
502 armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
503 armv7a_handle_l2x_cache_info_command;
510 COMMAND_HANDLER(handle_cache_l2x)
512 struct target *target = get_current_target(CMD_CTX);
516 return ERROR_COMMAND_SYNTAX_ERROR;
519 //command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]);
522 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], base);
523 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], way);
525 /* AP address is in bits 31:24 of DP_SELECT */
526 armv7a_l2x_cache_init(target, base, way);
529 return ERROR_COMMAND_SYNTAX_ERROR;
535 int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
536 struct armv7a_cache_common *armv7a_cache)
538 if (armv7a_cache->ctype == -1)
540 command_print(cmd_ctx, "cache not yet identified");
544 if (armv7a_cache->display_cache_info)
545 armv7a_cache->display_cache_info(cmd_ctx, armv7a_cache);
550 /* retrieve core id cluster id */
551 int arnv7a_read_mpidr(struct target *target)
553 int retval = ERROR_FAIL;
554 struct armv7a_common *armv7a = target_to_armv7a(target);
555 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
557 retval = dpm->prepare(dpm);
558 if (retval!=ERROR_OK) goto done;
559 /* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
561 retval = dpm->instr_read_data_r0(dpm,
562 ARMV4_5_MRC(15, 0, 0, 0, 0, 5),
564 if (retval!=ERROR_OK) goto done;
567 armv7a->multi_processor_system = (mpidr >> 30) & 1;
568 armv7a->cluster_id = (mpidr >> 8) & 0xf;
569 armv7a->cpu_id = mpidr & 0x3;
570 LOG_INFO("%s cluster %x core %x %s", target->cmd_name,
573 armv7a->multi_processor_system == 0 ? "multi core": "mono core");
577 LOG_ERROR("mpdir not in multiprocessor format");
587 int armv7a_identify_cache(struct target *target)
589 /* read cache descriptor */
590 int retval = ERROR_FAIL;
591 struct armv7a_common *armv7a = target_to_armv7a(target);
592 struct arm_dpm *dpm = armv7a->armv4_5_common.dpm;
593 uint32_t cache_selected,clidr;
594 uint32_t cache_i_reg, cache_d_reg;
595 struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache);
596 armv7a_read_ttbcr(target);
597 retval = dpm->prepare(dpm);
599 if (retval!=ERROR_OK) goto done;
601 /* mrc p15, 1, r0, c0, c0, 1 @ read clidr */
602 retval = dpm->instr_read_data_r0(dpm,
603 ARMV4_5_MRC(15, 1, 0, 0, 0, 1),
605 if (retval!=ERROR_OK) goto done;
606 clidr = (clidr & 0x7000000) >> 23;
607 LOG_INFO("number of cache level %d",clidr /2 );
610 // FIXME not supported present in cortex A8 and later
612 LOG_ERROR("cache l2 present :not supported");
614 /* retrieve selected cache */
615 /* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
616 retval = dpm->instr_read_data_r0(dpm,
617 ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
619 if (retval!=ERROR_OK) goto done;
621 retval = armv7a->armv4_5_common.mrc(target, 15,
625 /* select instruction cache*/
626 /* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR */
627 /* [0] : 1 instruction cache selection , 0 data cache selection */
628 retval = dpm->instr_write_data_r0(dpm,
629 ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
631 if (retval!=ERROR_OK) goto done;
634 /* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR */
635 /* [2:0] line size 001 eight word per line */
636 /* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
637 retval = dpm->instr_read_data_r0(dpm,
638 ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
640 if (retval!=ERROR_OK) goto done;
642 /* select data cache*/
643 retval = dpm->instr_write_data_r0(dpm,
644 ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
646 if (retval!=ERROR_OK) goto done;
648 retval = dpm->instr_read_data_r0(dpm,
649 ARMV4_5_MRC(15, 1, 0, 0, 0, 0),
651 if (retval!=ERROR_OK) goto done;
653 /* restore selected cache */
654 dpm->instr_write_data_r0(dpm,
655 ARMV4_5_MRC(15, 2, 0, 0, 0, 0),
658 if (retval != ERROR_OK) goto done;
662 cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
663 cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
664 cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
665 cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) +1;
666 /* compute info for set way operation on cache */
667 cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
668 cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
669 cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
670 cache->d_u_size.way_shift = cache->d_u_size.way+1;
673 while(((cache->d_u_size.way_shift >> i) & 1)!=1) i++;
674 cache->d_u_size.way_shift = 32-i;
676 /*LOG_INFO("data cache index %d << %d, way %d << %d",
677 cache->d_u_size.index, cache->d_u_size.index_shift,
678 cache->d_u_size.way, cache->d_u_size.way_shift);
680 LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
681 cache->d_u_size.linelen,
682 cache->d_u_size.cachesize,
683 cache->d_u_size.associativity
685 cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
686 cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) +1;
687 cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
688 cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
689 /* compute info for set way operation on cache */
690 cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
691 cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
692 cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
693 cache->i_size.way_shift = cache->i_size.way+1;
696 while(((cache->i_size.way_shift >> i) & 1)!=1) i++;
697 cache->i_size.way_shift = 32-i;
699 /*LOG_INFO("instruction cache index %d << %d, way %d << %d",
700 cache->i_size.index, cache->i_size.index_shift,
701 cache->i_size.way, cache->i_size.way_shift);
703 LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
704 cache->i_size.linelen,
705 cache->i_size.cachesize,
706 cache->i_size.associativity
708 /* if no l2 cache initialize l1 data cache flush function function */
709 if (armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache == NULL)
711 armv7a->armv7a_mmu.armv7a_cache.display_cache_info =
712 armv7a_handle_inner_cache_info_command;
713 armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache =
714 armv7a_flush_all_data;
716 armv7a->armv7a_mmu.armv7a_cache.ctype = 0;
720 arnv7a_read_mpidr(target);
727 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
729 struct armv7a_common *again;
730 struct arm *armv4_5 = &armv7a->armv4_5_common;
731 armv4_5->arch_info = armv7a;
732 target->arch_info = &armv7a->armv4_5_common;
733 /* target is useful in all function arm v4 5 compatible */
734 armv7a->armv4_5_common.target = target;
735 armv7a->armv4_5_common.common_magic = ARM_COMMON_MAGIC;
736 armv7a->common_magic = ARMV7_COMMON_MAGIC;
737 armv7a->armv7a_mmu.armv7a_cache.l2_cache = NULL;
738 armv7a->armv7a_mmu.armv7a_cache.ctype = -1;
739 armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
740 armv7a->armv7a_mmu.armv7a_cache.display_cache_info = NULL;
741 again =target_to_armv7a(target);
745 int armv7a_arch_state(struct target *target)
747 static const char *state[] =
749 "disabled", "enabled"
752 struct armv7a_common *armv7a = target_to_armv7a(target);
753 struct arm *armv4_5 = &armv7a->armv4_5_common;
755 if (armv7a->common_magic != ARMV7_COMMON_MAGIC)
757 LOG_ERROR("BUG: called for a non-ARMv7A target");
758 return ERROR_INVALID_ARGUMENTS;
761 arm_arch_state(target);
763 LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
764 state[armv7a->armv7a_mmu.mmu_enabled],
765 state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
766 state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
768 if (armv4_5->core_mode == ARM_MODE_ABT)
769 armv7a_show_fault_registers(target);
770 if (target->debug_reason == DBG_REASON_WATCHPOINT)
771 LOG_USER("Watchpoint triggered at PC %#08x",
772 (unsigned) armv7a->dpm.wp_pc);
777 static const struct command_registration l2_cache_commands[] = {
780 .handler = handle_cache_l2x,
781 .mode = COMMAND_EXEC,
782 .help = "configure l2x cache "
784 .usage = "[base_addr] [number_of_way]",
786 COMMAND_REGISTRATION_DONE
790 const struct command_registration l2x_cache_command_handlers[] = {
792 .name = "cache_config",
793 .mode = COMMAND_EXEC,
794 .help = "cache configuation for a target",
795 .chain = l2_cache_commands,
797 COMMAND_REGISTRATION_DONE
801 const struct command_registration armv7a_command_handlers[] = {
803 .chain = dap_command_handlers,
806 .chain = l2x_cache_command_handlers,
808 COMMAND_REGISTRATION_DONE