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   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /***************************************************************************
   4  *   Copyright (C) 2005 by Dominic Rath                                    *
   5  *   Dominic.Rath@gmx.de                                                   *
   6  ***************************************************************************/
   7
   8 #ifndef OPENOCD_TARGET_ARMV4_5_CACHE_H
   9 #define OPENOCD_TARGET_ARMV4_5_CACHE_H
  10
  11 #include "helper/types.h"
  12
  13 struct command_invocation;
  14
  15 struct armv4_5_cachesize {
  16         int linelen;
  17         int associativity;
  18         int nsets;
  19         int cachesize;
  20 };
  21
  22 struct armv4_5_cache_common {
  23         int ctype;      /* specify supported cache operations */
  24         int separate;   /* separate caches or unified cache */
  25         struct armv4_5_cachesize d_u_size;      /* data cache */
  26         struct armv4_5_cachesize i_size; /* instruction cache */
  27         int i_cache_enabled;
  28         int d_u_cache_enabled;
  29 };
  30
  31 int armv4_5_identify_cache(uint32_t cache_type_reg,
  32                 struct armv4_5_cache_common *cache);
  33 int armv4_5_cache_state(uint32_t cp15_control_reg,
  34                 struct armv4_5_cache_common *cache);
  35
  36 int armv4_5_handle_cache_info_command(struct command_invocation *cmd,
  37                 struct armv4_5_cache_common *armv4_5_cache);
  38
  39 enum {
  40         ARMV4_5_D_U_CACHE_ENABLED = 0x4,
  41         ARMV4_5_I_CACHE_ENABLED = 0x1000,
  42         ARMV4_5_WRITE_BUFFER_ENABLED = 0x8,
  43         ARMV4_5_CACHE_RR_BIT = 0x5000,
  44 };
  45
  46 #endif /* OPENOCD_TARGET_ARMV4_5_CACHE_H */