1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
31 typedef enum armv4_5_mode
33 ARMV4_5_MODE_USR = 16,
34 ARMV4_5_MODE_FIQ = 17,
35 ARMV4_5_MODE_IRQ = 18,
36 ARMV4_5_MODE_SVC = 19,
37 ARMV4_5_MODE_ABT = 23,
39 ARMV4_5_MODE_UND = 27,
40 ARMV4_5_MODE_SYS = 31,
44 const char *arm_mode_name(unsigned psr_mode);
45 bool is_arm_mode(unsigned psr_mode);
47 int armv4_5_mode_to_number(enum armv4_5_mode mode);
48 enum armv4_5_mode armv4_5_number_to_mode(int number);
50 typedef enum armv4_5_state
54 ARMV4_5_STATE_JAZELLE,
58 extern char* armv4_5_state_strings[];
60 extern const int armv4_5_core_reg_map[8][17];
62 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
63 cache->reg_list[armv4_5_core_reg_map[armv4_5_mode_to_number(mode)][num]]
65 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
66 enum { ARMV4_5_CPSR = 31, };
68 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
70 /* NOTE: this is being morphed into a generic toplevel holder for ARMs. */
71 #define armv4_5_common_s arm
74 * Represents a generic ARM core, with standard application registers.
76 * There are sixteen application registers (including PC, SP, LR) and a PSR.
77 * Cortex-M series cores do not support as many core states or shadowed
78 * registers as traditional ARM cores, and only support Thumb2 instructions.
83 struct reg_cache *core_cache;
85 /** Handle to the CPSR; valid in all core modes. */
89 * Indicates what registers are in the ARM state core register set.
90 * ARMV4_5_MODE_ANY indicates the standard set of 37 registers,
91 * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
92 * more registers are shadowed, for "Secure Monitor" mode.
94 enum armv4_5_mode core_type;
96 enum armv4_5_mode core_mode;
97 enum armv4_5_state core_state;
99 /** Flag reporting unavailability of the BKPT instruction. */
102 /** Handle for the Embedded Trace Module, if one is present. */
103 struct etm_context *etm;
105 int (*full_context)(struct target *target);
106 int (*read_core_reg)(struct target *target, struct reg *reg,
107 int num, enum armv4_5_mode mode);
108 int (*write_core_reg)(struct target *target, struct reg *reg,
109 int num, enum armv4_5_mode mode, uint32_t value);
113 #define target_to_armv4_5 target_to_arm
115 /** Convert target handle to generic ARM target state handle. */
116 static inline struct arm *target_to_arm(struct target *target)
118 return target->arch_info;
121 static inline bool is_arm(struct arm *arm)
123 return arm && arm->common_magic == ARMV4_5_COMMON_MAGIC;
126 struct armv4_5_algorithm
130 enum armv4_5_mode core_mode;
131 enum armv4_5_state core_state;
137 enum armv4_5_mode mode;
138 struct target *target;
139 struct arm *armv4_5_common;
143 struct reg_cache* armv4_5_build_reg_cache(struct target *target,
144 struct arm *armv4_5_common);
146 int armv4_5_arch_state(struct target *target);
147 int armv4_5_get_gdb_reg_list(struct target *target,
148 struct reg **reg_list[], int *reg_list_size);
150 int armv4_5_register_commands(struct command_context *cmd_ctx);
151 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
153 int armv4_5_run_algorithm(struct target *target,
154 int num_mem_params, struct mem_param *mem_params,
155 int num_reg_params, struct reg_param *reg_params,
156 uint32_t entry_point, uint32_t exit_point,
157 int timeout_ms, void *arch_info);
159 int arm_checksum_memory(struct target *target,
160 uint32_t address, uint32_t count, uint32_t *checksum);
161 int arm_blank_check_memory(struct target *target,
162 uint32_t address, uint32_t count, uint32_t *blank);
164 extern struct reg arm_gdb_dummy_fp_reg;
165 extern struct reg arm_gdb_dummy_fps_reg;
167 /* ARM mode instructions
170 /* Store multiple increment after
172 * List: for each bit in list: store register
173 * S: in priviledged mode: store user-mode registers
174 * W = 1: update the base register. W = 0: leave the base register untouched
176 #define ARMV4_5_STMIA(Rn, List, S, W) (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
178 /* Load multiple increment after
180 * List: for each bit in list: store register
181 * S: in priviledged mode: store user-mode registers
182 * W = 1: update the base register. W = 0: leave the base register untouched
184 #define ARMV4_5_LDMIA(Rn, List, S, W) (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
187 #define ARMV4_5_NOP (0xe1a08008)
189 /* Move PSR to general purpose register
190 * R = 1: SPSR R = 0: CPSR
191 * Rn: target register
193 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
196 * Rd: register to store
199 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
202 * Rd: register to load
205 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
207 /* Move general purpose register to PSR
208 * R = 1: SPSR R = 0: CPSR
210 * 1: control field 2: extension field 4: status field 8: flags field
211 * Rm: source register
213 #define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
214 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
216 /* Load Register Halfword Immediate Post-Index
217 * Rd: register to load
220 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
222 /* Load Register Byte Immediate Post-Index
223 * Rd: register to load
226 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
228 /* Store register Halfword Immediate Post-Index
229 * Rd: register to store
232 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
234 /* Store register Byte Immediate Post-Index
235 * Rd: register to store
238 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
241 * Im: Branch target (left-shifted by 2 bits, added to PC)
242 * L: 1: branch and link 0: branch only
244 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
246 /* Branch and exchange (ARM state)
247 * Rm: register holding branch target address
249 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
251 /* Move to ARM register from coprocessor
252 * CP: Coprocessor number
253 * op1: Coprocessor opcode
254 * Rd: destination register
255 * CRn: first coprocessor operand
256 * CRm: second coprocessor operand
257 * op2: Second coprocessor opcode
259 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
261 /* Move to coprocessor from ARM register
262 * CP: Coprocessor number
263 * op1: Coprocessor opcode
264 * Rd: destination register
265 * CRn: first coprocessor operand
266 * CRm: second coprocessor operand
267 * op2: Second coprocessor opcode
269 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
271 /* Breakpoint instruction (ARMv5)
272 * Im: 16-bit immediate
274 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
277 /* Thumb mode instructions
280 /* Store register (Thumb mode)
281 * Rd: source register
284 #define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
286 /* Load register (Thumb state)
287 * Rd: destination register
290 #define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
292 /* Load multiple (Thumb state)
294 * List: for each bit in list: store register
296 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
298 /* Load register with PC relative addressing
299 * Rd: register to load
301 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
303 /* Move hi register (Thumb mode)
304 * Rd: destination register
305 * Rm: source register
307 #define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
309 /* No operation (Thumb mode)
311 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
313 /* Move immediate to register (Thumb state)
314 * Rd: destination register
315 * Im: 8-bit immediate value
317 #define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
319 /* Branch and Exchange
320 * Rm: register containing branch target
322 #define ARMV4_5_T_BX(Rm) ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
324 /* Branch (Thumb state)
327 #define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
329 /* Breakpoint instruction (ARMv5) (Thumb state)
330 * Im: 8-bit immediate
332 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
334 /* build basic mrc/mcr opcode */
336 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
346 #endif /* ARMV4_5_H */