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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #include "config.h"
  21
  22 #include "arm_disassembler.h"
  23
  24 #include "armv4_5.h"
  25
  26 #include "target.h"
  27 #include "register.h"
  28 #include "log.h"
  29 #include "binarybuffer.h"
  30 #include "command.h"
  31
  32 #include <stdlib.h>
  33 #include <string.h>
  34 #include <unistd.h>
  35
  36 bitfield_desc_t armv4_5_psr_bitfield_desc[] =
  37 {
  38         {"M[4:0]", 5},
  39         {"T", 1},
  40         {"F", 1},
  41         {"I", 1},
  42         {"reserved", 16},
  43         {"J", 1},
  44         {"reserved", 2},
  45         {"Q", 1},
  46         {"V", 1},
  47         {"C", 1},
  48         {"Z", 1},
  49         {"N", 1},
  50 };
  51
  52 char* armv4_5_core_reg_list[] =
  53 {
  54         "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
  55
  56         "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
  57
  58         "r13_irq", "lr_irq",
  59
  60         "r13_svc", "lr_svc",
  61
  62         "r13_abt", "lr_abt",
  63
  64         "r13_und", "lr_und",
  65
  66         "cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und"
  67 };
  68
  69 char* armv4_5_mode_strings[] =
  70 {
  71         "User", "FIQ", "IRQ", "Supervisor", "Abort", "Undefined", "System"
  72 };
  73
  74 char* armv4_5_state_strings[] =
  75 {
  76         "ARM", "Thumb", "Jazelle"
  77 };
  78
  79 int armv4_5_core_reg_arch_type = -1;
  80
  81 armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
  82 {
  83         {0, ARMV4_5_MODE_ANY, NULL, NULL},
  84         {1, ARMV4_5_MODE_ANY, NULL, NULL},
  85         {2, ARMV4_5_MODE_ANY, NULL, NULL},
  86         {3, ARMV4_5_MODE_ANY, NULL, NULL},
  87         {4, ARMV4_5_MODE_ANY, NULL, NULL},
  88         {5, ARMV4_5_MODE_ANY, NULL, NULL},
  89         {6, ARMV4_5_MODE_ANY, NULL, NULL},
  90         {7, ARMV4_5_MODE_ANY, NULL, NULL},
  91         {8, ARMV4_5_MODE_ANY, NULL, NULL},
  92         {9, ARMV4_5_MODE_ANY, NULL, NULL},
  93         {10, ARMV4_5_MODE_ANY, NULL, NULL},
  94         {11, ARMV4_5_MODE_ANY, NULL, NULL},
  95         {12, ARMV4_5_MODE_ANY, NULL, NULL},
  96         {13, ARMV4_5_MODE_USR, NULL, NULL},
  97         {14, ARMV4_5_MODE_USR, NULL, NULL},
  98         {15, ARMV4_5_MODE_ANY, NULL, NULL},
  99
 100         {8, ARMV4_5_MODE_FIQ, NULL, NULL},
 101         {9, ARMV4_5_MODE_FIQ, NULL, NULL},
 102         {10, ARMV4_5_MODE_FIQ, NULL, NULL},
 103         {11, ARMV4_5_MODE_FIQ, NULL, NULL},
 104         {12, ARMV4_5_MODE_FIQ, NULL, NULL},
 105         {13, ARMV4_5_MODE_FIQ, NULL, NULL},
 106         {14, ARMV4_5_MODE_FIQ, NULL, NULL},
 107
 108         {13, ARMV4_5_MODE_IRQ, NULL, NULL},
 109         {14, ARMV4_5_MODE_IRQ, NULL, NULL},
 110
 111         {13, ARMV4_5_MODE_SVC, NULL, NULL},
 112         {14, ARMV4_5_MODE_SVC, NULL, NULL},
 113
 114         {13, ARMV4_5_MODE_ABT, NULL, NULL},
 115         {14, ARMV4_5_MODE_ABT, NULL, NULL},
 116
 117         {13, ARMV4_5_MODE_UND, NULL, NULL},
 118         {14, ARMV4_5_MODE_UND, NULL, NULL},
 119
 120         {16, ARMV4_5_MODE_ANY, NULL, NULL},
 121         {16, ARMV4_5_MODE_FIQ, NULL, NULL},
 122         {16, ARMV4_5_MODE_IRQ, NULL, NULL},
 123         {16, ARMV4_5_MODE_SVC, NULL, NULL},
 124         {16, ARMV4_5_MODE_ABT, NULL, NULL},
 125         {16, ARMV4_5_MODE_UND, NULL, NULL}
 126 };
 127
 128 /* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
 129 int armv4_5_core_reg_map[7][17] =
 130 {
 131         {       /* USR */
 132                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
 133         },
 134         {       /* FIQ */
 135                 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
 136         },
 137         {       /* IRQ */
 138                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
 139         },
 140         {       /* SVC */
 141                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
 142         },
 143         {       /* ABT */
 144                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
 145         },
 146         {       /* UND */
 147                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
 148         },
 149         {       /* SYS */
 150                 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
 151         }
 152 };
 153
 154 u8 armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
 155
 156 reg_t armv4_5_gdb_dummy_fp_reg =
 157 {
 158         "GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
 159 };
 160
 161 u8 armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
 162
 163 reg_t armv4_5_gdb_dummy_fps_reg =
 164 {
 165         "GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
 166 };
 167
 168 /* map psr mode bits to linear number */
 169 int armv4_5_mode_to_number(enum armv4_5_mode mode)
 170 {
 171         switch (mode)
 172         {
 173                 case 16: return 0; break;
 174                 case 17: return 1; break;
 175                 case 18: return 2; break;
 176                 case 19: return 3; break;
 177                 case 23: return 4; break;
 178                 case 27: return 5; break;
 179                 case 31: return 6; break;
 180                 case -1: return 0; break;       /* map MODE_ANY to user mode */
 181                 default:
 182                         ERROR("invalid mode value encountered");
 183                         return -1;
 184         }
 185 }
 186
 187 /* map linear number to mode bits */
 188 enum armv4_5_mode armv4_5_number_to_mode(int number)
 189 {
 190         switch(number)
 191         {
 192                 case 0: return ARMV4_5_MODE_USR; break;
 193                 case 1: return ARMV4_5_MODE_FIQ; break;
 194                 case 2: return ARMV4_5_MODE_IRQ; break;
 195                 case 3: return ARMV4_5_MODE_SVC; break;
 196                 case 4: return ARMV4_5_MODE_ABT; break;
 197                 case 5: return ARMV4_5_MODE_UND; break;
 198                 case 6: return ARMV4_5_MODE_SYS; break;
 199                 default:
 200                         ERROR("mode index out of bounds");
 201                         return -1;
 202         }
 203 };
 204
 205 int armv4_5_get_core_reg(reg_t *reg)
 206 {
 207         int retval;
 208         armv4_5_core_reg_t *armv4_5 = reg->arch_info;
 209         target_t *target = armv4_5->target;
 210
 211         if (target->state != TARGET_HALTED)
 212         {
 213                 return ERROR_TARGET_NOT_HALTED;
 214         }
 215
 216         //retval = armv4_5->armv4_5_common->full_context(target);
 217         retval = armv4_5->armv4_5_common->read_core_reg(target, armv4_5->num, armv4_5->mode);
 218
 219         return retval;
 220 }
 221
 222 int armv4_5_set_core_reg(reg_t *reg, u32 value)
 223 {
 224         armv4_5_core_reg_t *armv4_5 = reg->arch_info;
 225         target_t *target = armv4_5->target;
 226
 227         if (target->state != TARGET_HALTED)
 228         {
 229                 return ERROR_TARGET_NOT_HALTED;
 230         }
 231
 232         buf_set_u32(reg->value, 0, 32, value);
 233         reg->dirty = 1;
 234         reg->valid = 1;
 235
 236         return ERROR_OK;
 237 }
 238
 239 int armv4_5_invalidate_core_regs(target_t *target)
 240 {
 241         armv4_5_common_t *armv4_5 = target->arch_info;
 242         int i;
 243
 244         for (i = 0; i < 37; i++)
 245         {
 246                 armv4_5->core_cache->reg_list[i].valid = 0;
 247                 armv4_5->core_cache->reg_list[i].dirty = 0;
 248         }
 249
 250         return ERROR_OK;
 251 }
 252
 253 reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
 254 {
 255         int num_regs = 37;
 256         reg_cache_t *cache = malloc(sizeof(reg_cache_t));
 257         reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
 258         armv4_5_core_reg_t *arch_info = malloc(sizeof(reg_t) * num_regs);
 259         int i;
 260
 261         cache->name = "arm v4/5 registers";
 262         cache->next = NULL;
 263         cache->reg_list = reg_list;
 264         cache->num_regs = num_regs;
 265
 266         if (armv4_5_core_reg_arch_type == -1)
 267                 armv4_5_core_reg_arch_type = register_reg_arch_type(armv4_5_get_core_reg, armv4_5_set_core_reg);
 268
 269         for (i = 0; i < 37; i++)
 270         {
 271                 arch_info[i] = armv4_5_core_reg_list_arch_info[i];
 272                 arch_info[i].target = target;
 273                 arch_info[i].armv4_5_common = armv4_5_common;
 274                 reg_list[i].name = armv4_5_core_reg_list[i];
 275                 reg_list[i].size = 32;
 276                 reg_list[i].value = calloc(1, 4);
 277                 reg_list[i].dirty = 0;
 278                 reg_list[i].valid = 0;
 279                 reg_list[i].bitfield_desc = NULL;
 280                 reg_list[i].num_bitfields = 0;
 281                 reg_list[i].arch_type = armv4_5_core_reg_arch_type;
 282                 reg_list[i].arch_info = &arch_info[i];
 283         }
 284
 285         return cache;
 286 }
 287
 288 int armv4_5_arch_state(struct target_s *target, char *buf, int buf_size)
 289 {
 290         armv4_5_common_t *armv4_5 = target->arch_info;
 291
 292         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 293         {
 294                 ERROR("BUG: called for a non-ARMv4/5 target");
 295                 exit(-1);
 296         }
 297
 298         snprintf(buf, buf_size,
 299                          "target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
 300                          armv4_5_state_strings[armv4_5->core_state],
 301                          target_debug_reason_strings[target->debug_reason],
 302                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 303                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 304                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 305
 306         return ERROR_OK;
 307 }
 308
 309 int handle_armv4_5_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 310 {
 311         char output[128];
 312         int output_len;
 313         int mode, num;
 314         target_t *target = get_current_target(cmd_ctx);
 315         armv4_5_common_t *armv4_5 = target->arch_info;
 316
 317         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 318         {
 319                 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
 320                 return ERROR_OK;
 321         }
 322
 323         if (target->state != TARGET_HALTED)
 324         {
 325                 command_print(cmd_ctx, "error: target must be halted for register accesses");
 326                 return ERROR_OK;
 327         }
 328
 329         for (num = 0; num <= 15; num++)
 330         {
 331                 output_len = 0;
 332                 for (mode = 0; mode < 6; mode++)
 333                 {
 334                         if (!ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).valid)
 335                         {
 336                                 armv4_5->full_context(target);
 337                         }
 338                         output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
 339                                 buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
 340                 }
 341                 command_print(cmd_ctx, output);
 342         }
 343         command_print(cmd_ctx, "    cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
 344                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 345                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
 346                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
 347                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_SVC].value, 0, 32),
 348                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_ABT].value, 0, 32),
 349                           buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_UND].value, 0, 32));
 350
 351         return ERROR_OK;
 352 }
 353
 354 int handle_armv4_5_core_state_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 355 {
 356         target_t *target = get_current_target(cmd_ctx);
 357         armv4_5_common_t *armv4_5 = target->arch_info;
 358
 359         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 360         {
 361                 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
 362                 return ERROR_OK;
 363         }
 364
 365         if (argc > 0)
 366         {
 367                 if (strcmp(args[0], "arm") == 0)
 368                 {
 369                         armv4_5->core_state = ARMV4_5_STATE_ARM;
 370                 }
 371                 if (strcmp(args[0], "thumb") == 0)
 372                 {
 373                         armv4_5->core_state = ARMV4_5_STATE_THUMB;
 374                 }
 375         }
 376
 377         command_print(cmd_ctx, "core state: %s", armv4_5_state_strings[armv4_5->core_state]);
 378
 379         return ERROR_OK;
 380 }
 381
 382 int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 383 {
 384         target_t *target = get_current_target(cmd_ctx);
 385         armv4_5_common_t *armv4_5 = target->arch_info;
 386         u32 address;
 387         int count;
 388         int i;
 389         arm_instruction_t cur_instruction;
 390         u32 opcode;
 391         int thumb;
 392
 393         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 394         {
 395                 command_print(cmd_ctx, "current target isn't an ARMV4/5 target");
 396                 return ERROR_OK;
 397         }
 398
 399         if (argc < 2)
 400         {
 401                 command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
 402                 return ERROR_OK;
 403         }
 404
 405         address = strtoul(args[0], NULL, 0);
 406         count = strtoul(args[1], NULL, 0);
 407
 408         if (argc >= 3)
 409                 if (strcmp(args[2], "thumb") == 0)
 410                         thumb = 1;
 411
 412         for (i = 0; i < count; i++)
 413         {
 414                 target->type->read_memory(target, address, 4, 1, (u8*)&opcode);
 415                 evaluate_opcode(opcode, address, &cur_instruction);
 416                 command_print(cmd_ctx, "%s", cur_instruction.text);
 417                 address += (thumb) ? 2 : 4;
 418         }
 419
 420         return ERROR_OK;
 421 }
 422
 423 int armv4_5_register_commands(struct command_context_s *cmd_ctx)
 424 {
 425         command_t *armv4_5_cmd;
 426
 427         armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, NULL);
 428
 429         register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
 430         register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm|thumb>");
 431
 432         register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
 433         return ERROR_OK;
 434 }
 435
 436 int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
 437 {
 438         armv4_5_common_t *armv4_5 = target->arch_info;
 439         int i;
 440
 441         if (target->state != TARGET_HALTED)
 442         {
 443                 return ERROR_TARGET_NOT_HALTED;
 444         }
 445
 446         *reg_list_size = 26;
 447         *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
 448
 449         for (i = 0; i < 16; i++)
 450         {
 451                 (*reg_list)[i] = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i);
 452         }
 453
 454         for (i = 16; i < 24; i++)
 455         {
 456                 (*reg_list)[i] = &armv4_5_gdb_dummy_fp_reg;
 457         }
 458
 459         (*reg_list)[24] = &armv4_5_gdb_dummy_fps_reg;
 460         (*reg_list)[25] = &armv4_5->core_cache->reg_list[ARMV4_5_CPSR];
 461
 462         return ERROR_OK;
 463 }
 464
 465 int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info)
 466 {
 467         armv4_5_common_t *armv4_5 = target->arch_info;
 468         armv4_5_algorithm_t *armv4_5_algorithm_info = arch_info;
 469         enum armv4_5_state core_state = armv4_5->core_state;
 470         enum armv4_5_mode core_mode = armv4_5->core_mode;
 471         u32 context[17];
 472         u32 cpsr;
 473         int exit_breakpoint_size = 0;
 474         int i;
 475         int retval = ERROR_OK;
 476
 477         if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
 478         {
 479                 ERROR("current target isn't an ARMV4/5 target");
 480                 return ERROR_TARGET_INVALID;
 481         }
 482
 483         if (target->state != TARGET_HALTED)
 484         {
 485                 WARNING("target not halted");
 486                 return ERROR_TARGET_NOT_HALTED;
 487         }
 488
 489         for (i = 0; i <= 16; i++)
 490         {
 491                 if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
 492                         armv4_5->read_core_reg(target, i, armv4_5_algorithm_info->core_mode);
 493                 context[i] = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
 494         }
 495         cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32);
 496
 497         for (i = 0; i < num_mem_params; i++)
 498         {
 499                 target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 500         }
 501
 502         for (i = 0; i < num_reg_params; i++)
 503         {
 504                 reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
 505                 if (!reg)
 506                 {
 507                         ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 508                         exit(-1);
 509                 }
 510
 511                 if (reg->size != reg_params[i].size)
 512                 {
 513                         ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 514                         exit(-1);
 515                 }
 516
 517                 armv4_5_set_core_reg(reg, buf_get_u32(reg_params[i].value, 0, 32));
 518         }
 519
 520         armv4_5->core_state = armv4_5_algorithm_info->core_state;
 521         if (armv4_5->core_state == ARMV4_5_STATE_ARM)
 522                 exit_breakpoint_size = 4;
 523         else if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
 524                 exit_breakpoint_size = 2;
 525         else
 526         {
 527                 ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
 528                 exit(-1);
 529         }
 530
 531         if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
 532         {
 533                 DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
 534                 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
 535                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 536                 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 537         }
 538
 539         if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
 540         {
 541                 ERROR("can't add breakpoint to finish algorithm execution");
 542                 return ERROR_TARGET_FAILURE;
 543         }
 544
 545         target->type->resume(target, 0, entry_point, 1, 1);
 546         target->type->poll(target);
 547
 548         while (target->state != TARGET_HALTED)
 549         {
 550                 usleep(10000);
 551                 target->type->poll(target);
 552                 if ((timeout_ms -= 10) <= 0)
 553                 {
 554                         ERROR("timeout waiting for algorithm to complete, trying to halt target");
 555                         target->type->halt(target);
 556                         timeout_ms = 1000;
 557                         while (target->state != TARGET_HALTED)
 558                         {
 559                                 usleep(10000);
 560                                 target->type->poll(target);
 561                                 if ((timeout_ms -= 10) <= 0)
 562                                 {
 563                                         ERROR("target didn't reenter debug state, exiting");
 564                                         exit(-1);
 565                                 }
 566                         }
 567                         retval = ERROR_TARGET_TIMEOUT;
 568                 }
 569         }
 570
 571         breakpoint_remove(target, exit_point);
 572
 573         for (i = 0; i < num_mem_params; i++)
 574         {
 575                 if (mem_params[i].direction != PARAM_OUT)
 576                         target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
 577         }
 578
 579         for (i = 0; i < num_reg_params; i++)
 580         {
 581                 if (reg_params[i].direction != PARAM_OUT)
 582                 {
 583
 584                         reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
 585                         if (!reg)
 586                         {
 587                                 ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
 588                                 exit(-1);
 589                         }
 590
 591                         if (reg->size != reg_params[i].size)
 592                         {
 593                                 ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
 594                                 exit(-1);
 595                         }
 596
 597                         buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
 598                 }
 599         }
 600
 601         for (i = 0; i <= 16; i++)
 602         {
 603                 DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32));
 604                 buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
 605                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
 606                 ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;
 607         }
 608         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, cpsr);
 609         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 610         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 611
 612         armv4_5->core_state = core_state;
 613         armv4_5->core_mode = core_mode;
 614
 615         return retval;
 616 }
 617
 618 int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
 619 {
 620         target->arch_info = armv4_5;
 621
 622         armv4_5->common_magic = ARMV4_5_COMMON_MAGIC;
 623         armv4_5->core_state = ARMV4_5_STATE_ARM;
 624         armv4_5->core_mode = ARMV4_5_MODE_USR;
 625
 626         return ERROR_OK;
 627 }