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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Hongtao Zheng                                   *
   6  *   hontor@126.com                                                        *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "armv4_5.h"
  28 #include "arm_disassembler.h"
  29 #include "arm_simulator.h"
  30 #include "log.h"
  31 #include "binarybuffer.h"
  32
  33
  34 uint32_t arm_shift(uint8_t shift, uint32_t Rm, uint32_t shift_amount, uint8_t *carry)
  35 {
  36         uint32_t return_value = 0;
  37         shift_amount &= 0xff;
  38
  39         if (shift == 0x0) /* LSL */
  40         {
  41                 if ((shift_amount > 0) && (shift_amount <= 32))
  42                 {
  43                         return_value = Rm << shift_amount;
  44                         *carry = Rm >> (32 - shift_amount);
  45                 }
  46                 else if (shift_amount > 32)
  47                 {
  48                         return_value = 0x0;
  49                         *carry = 0x0;
  50                 }
  51                 else /* (shift_amount == 0) */
  52                 {
  53                         return_value = Rm;
  54                 }
  55         }
  56         else if (shift == 0x1) /* LSR */
  57         {
  58                 if ((shift_amount > 0) && (shift_amount <= 32))
  59                 {
  60                         return_value = Rm >> shift_amount;
  61                         *carry = (Rm >> (shift_amount - 1)) & 1;
  62                 }
  63                 else if (shift_amount > 32)
  64                 {
  65                         return_value = 0x0;
  66                         *carry = 0x0;
  67                 }
  68                 else /* (shift_amount == 0) */
  69                 {
  70                         return_value = Rm;
  71                 }
  72         }
  73         else if (shift == 0x2) /* ASR */
  74         {
  75                 if ((shift_amount > 0) && (shift_amount <= 32))
  76                 {
  77                         /* right shifts of unsigned values are guaranteed to be logical (shift in zeroes)
  78                          * simulate an arithmetic shift (shift in signed-bit) by adding the signed-bit manually */
  79                         return_value = Rm >> shift_amount;
  80                         if (Rm & 0x80000000)
  81                                 return_value |= 0xffffffff << (32 - shift_amount);
  82                 }
  83                 else if (shift_amount > 32)
  84                 {
  85                         if (Rm & 0x80000000)
  86                         {
  87                                 return_value = 0xffffffff;
  88                                 *carry = 0x1;
  89                         }
  90                         else
  91                         {
  92                                 return_value = 0x0;
  93                                 *carry = 0x0;
  94                         }
  95                 }
  96                 else /* (shift_amount == 0) */
  97                 {
  98                         return_value = Rm;
  99                 }
 100         }
 101         else if (shift == 0x3) /* ROR */
 102         {
 103                 if (shift_amount == 0)
 104                 {
 105                         return_value = Rm;
 106                 }
 107                 else
 108                 {
 109                         shift_amount = shift_amount % 32;
 110                         return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount));
 111                         *carry = (return_value >> 31) & 0x1;
 112                 }
 113         }
 114         else if (shift == 0x4) /* RRX */
 115         {
 116                 return_value = Rm >> 1;
 117                 if (*carry)
 118                         Rm |= 0x80000000;
 119                 *carry = Rm & 0x1;
 120         }
 121
 122         return return_value;
 123 }
 124
 125
 126 uint32_t arm_shifter_operand(struct arm_sim_interface *sim, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out)
 127 {
 128         uint32_t return_value;
 129         int instruction_size;
 130
 131         if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
 132                 instruction_size = 4;
 133         else
 134                 instruction_size = 2;
 135
 136         *shifter_carry_out = sim->get_cpsr(sim, 29, 1);
 137
 138         if (variant == 0) /* 32-bit immediate */
 139         {
 140                 return_value = shifter_operand.immediate.immediate;
 141         }
 142         else if (variant == 1) /* immediate shift */
 143         {
 144                 uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm);
 145
 146                 /* adjust RM in case the PC is being read */
 147                 if (shifter_operand.immediate_shift.Rm == 15)
 148                         Rm += 2 * instruction_size;
 149
 150                 return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, shifter_operand.immediate_shift.shift_imm, shifter_carry_out);
 151         }
 152         else if (variant == 2) /* register shift */
 153         {
 154                 uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm);
 155                 uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs);
 156
 157                 /* adjust RM in case the PC is being read */
 158                 if (shifter_operand.register_shift.Rm == 15)
 159                         Rm += 2 * instruction_size;
 160
 161                 return_value = arm_shift(shifter_operand.immediate_shift.shift, Rm, Rs, shifter_carry_out);
 162         }
 163         else
 164         {
 165                 LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
 166                 return_value = 0xffffffff;
 167         }
 168
 169         return return_value;
 170 }
 171
 172 int pass_condition(uint32_t cpsr, uint32_t opcode)
 173 {
 174         switch ((opcode & 0xf0000000) >> 28)
 175         {
 176                 case 0x0:       /* EQ */
 177                         if (cpsr & 0x40000000)
 178                                 return 1;
 179                         else
 180                                 return 0;
 181                 case 0x1:       /* NE */
 182                         if (!(cpsr & 0x40000000))
 183                                 return 1;
 184                         else
 185                                 return 0;
 186                 case 0x2:       /* CS */
 187                         if (cpsr & 0x20000000)
 188                                 return 1;
 189                         else
 190                                 return 0;
 191                 case 0x3:       /* CC */
 192                         if (!(cpsr & 0x20000000))
 193                                 return 1;
 194                         else
 195                                 return 0;
 196                 case 0x4:       /* MI */
 197                         if (cpsr & 0x80000000)
 198                                 return 1;
 199                         else
 200                                 return 0;
 201                 case 0x5:       /* PL */
 202                         if (!(cpsr & 0x80000000))
 203                                 return 1;
 204                         else
 205                                 return 0;
 206                 case 0x6:       /* VS */
 207                         if (cpsr & 0x10000000)
 208                                 return 1;
 209                         else
 210                                 return 0;
 211                 case 0x7:       /* VC */
 212                         if (!(cpsr & 0x10000000))
 213                                 return 1;
 214                         else
 215                                 return 0;
 216                 case 0x8:       /* HI */
 217                         if ((cpsr & 0x20000000) && !(cpsr & 0x40000000))
 218                                 return 1;
 219                         else
 220                                 return 0;
 221                 case 0x9:       /* LS */
 222                         if (!(cpsr & 0x20000000) || (cpsr & 0x40000000))
 223                                 return 1;
 224                         else
 225                                 return 0;
 226                 case 0xa:       /* GE */
 227                         if (((cpsr & 0x80000000) && (cpsr & 0x10000000))
 228                                 || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))
 229                                 return 1;
 230                         else
 231                                 return 0;
 232                 case 0xb:       /* LT */
 233                         if (((cpsr & 0x80000000) && !(cpsr & 0x10000000))
 234                                 || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
 235                                 return 1;
 236                         else
 237                                 return 0;
 238                 case 0xc:       /* GT */
 239                         if (!(cpsr & 0x40000000) &&
 240                                 (((cpsr & 0x80000000) && (cpsr & 0x10000000))
 241                                 || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))))
 242                                 return 1;
 243                         else
 244                                 return 0;
 245                 case 0xd:       /* LE */
 246                         if ((cpsr & 0x40000000) ||
 247                                 ((cpsr & 0x80000000) && !(cpsr & 0x10000000))
 248                                 || (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
 249                                 return 1;
 250                         else
 251                                 return 0;
 252                 case 0xe:
 253                 case 0xf:
 254                         return 1;
 255
 256         }
 257
 258         LOG_ERROR("BUG: should never get here");
 259         return 0;
 260 }
 261
 262 int thumb_pass_branch_condition(uint32_t cpsr, uint16_t opcode)
 263 {
 264         return pass_condition(cpsr, (opcode & 0x0f00) << 20);
 265 }
 266
 267 /* simulate a single step (if possible)
 268  * if the dry_run_pc argument is provided, no state is changed,
 269  * but the new pc is stored in the variable pointed at by the argument
 270  */
 271 int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_sim_interface *sim)
 272 {
 273         uint32_t current_pc = sim->get_reg(sim, 15);
 274         arm_instruction_t instruction;
 275         int instruction_size;
 276         int retval = ERROR_OK;
 277
 278         if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
 279         {
 280                 uint32_t opcode;
 281
 282                 /* get current instruction, and identify it */
 283                 if ((retval = target_read_u32(target, current_pc, &opcode)) != ERROR_OK)
 284                 {
 285                         return retval;
 286                 }
 287                 if ((retval = arm_evaluate_opcode(opcode, current_pc, &instruction)) != ERROR_OK)
 288                 {
 289                         return retval;
 290                 }
 291                 instruction_size = 4;
 292
 293                 /* check condition code (for all instructions) */
 294                 if (!pass_condition(sim->get_cpsr(sim, 0, 32), opcode))
 295                 {
 296                         if (dry_run_pc)
 297                         {
 298                                 *dry_run_pc = current_pc + instruction_size;
 299                         }
 300                         else
 301                         {
 302                                 sim->set_reg(sim, 15, current_pc + instruction_size);
 303                         }
 304
 305                         return ERROR_OK;
 306                 }
 307         }
 308         else
 309         {
 310                 uint16_t opcode;
 311
 312                 retval = target_read_u16(target, current_pc, &opcode);
 313                 if (retval != ERROR_OK)
 314                         return retval;
 315                 retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
 316                  if (retval != ERROR_OK)
 317                         return retval;
 318                 instruction_size = 2;
 319
 320                 /* check condition code (only for branch instructions) */
 321                 if (instruction.type == ARM_B &&
 322                     !thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode))
 323                 {
 324                         if (dry_run_pc)
 325                         {
 326                                 *dry_run_pc = current_pc + instruction_size;
 327                         }
 328                         else
 329                         {
 330                                 sim->set_reg(sim, 15, current_pc + instruction_size);
 331                         }
 332
 333                         return ERROR_OK;
 334                 }
 335
 336                 /* Deal with 32-bit BL/BLX */
 337                 if ((opcode & 0xf800) == 0xf000) {
 338                         uint32_t high = instruction.info.b_bl_bx_blx.target_address;
 339                         retval = target_read_u16(target, current_pc+2, &opcode);
 340                         if (retval != ERROR_OK)
 341                                 return retval;
 342                         retval = thumb_evaluate_opcode(opcode, current_pc, &instruction);
 343                         if (retval != ERROR_OK)
 344                                 return retval;
 345                         instruction.info.b_bl_bx_blx.target_address += high;
 346                 }
 347         }
 348
 349         /* examine instruction type */
 350
 351         /* branch instructions */
 352         if ((instruction.type >= ARM_B) && (instruction.type <= ARM_BLX))
 353         {
 354                 uint32_t target;
 355
 356                 if (instruction.info.b_bl_bx_blx.reg_operand == -1)
 357                 {
 358                         target = instruction.info.b_bl_bx_blx.target_address;
 359                 }
 360                 else
 361                 {
 362                         target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
 363                         if (instruction.info.b_bl_bx_blx.reg_operand == 15)
 364                         {
 365                                 target += 2 * instruction_size;
 366                         }
 367                 }
 368
 369                 if (dry_run_pc)
 370                 {
 371                         *dry_run_pc = target & ~1;
 372                         return ERROR_OK;
 373                 }
 374                 else
 375                 {
 376                         if (instruction.type == ARM_B)
 377                         {
 378                                 sim->set_reg(sim, 15, target);
 379                         }
 380                         else if (instruction.type == ARM_BL)
 381                         {
 382                                 uint32_t old_pc = sim->get_reg(sim, 15);
 383                                 sim->set_reg_mode(sim, 14, old_pc + 4);
 384                                 sim->set_reg(sim, 15, target);
 385                         }
 386                         else if (instruction.type == ARM_BX)
 387                         {
 388                                 if (target & 0x1)
 389                                 {
 390                                         sim->set_state(sim, ARMV4_5_STATE_THUMB);
 391                                 }
 392                                 else
 393                                 {
 394                                         sim->set_state(sim, ARMV4_5_STATE_ARM);
 395                                 }
 396                                 sim->set_reg(sim, 15, target & 0xfffffffe);
 397                         }
 398                         else if (instruction.type == ARM_BLX)
 399                         {
 400                                 uint32_t old_pc = sim->get_reg(sim, 15);
 401                                 sim->set_reg_mode(sim, 14, old_pc + 4);
 402
 403                                 if (target & 0x1)
 404                                 {
 405                                         sim->set_state(sim, ARMV4_5_STATE_THUMB);
 406                                 }
 407                                 else
 408                                 {
 409                                         sim->set_state(sim, ARMV4_5_STATE_ARM);
 410                                 }
 411                                 sim->set_reg(sim, 15, target & 0xfffffffe);
 412                         }
 413
 414                         return ERROR_OK;
 415                 }
 416         }
 417         /* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
 418         else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
 419                         || ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
 420         {
 421                 uint32_t Rd, Rn, shifter_operand;
 422                 uint8_t C = sim->get_cpsr(sim, 29, 1);
 423                 uint8_t carry_out;
 424
 425                 Rd = 0x0;
 426                 /* ARM_MOV and ARM_MVN does not use Rn */
 427                 if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
 428                         Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn);
 429                 else
 430                         Rn = 0;
 431
 432                 shifter_operand = arm_shifter_operand(sim, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
 433
 434                 /* adjust Rn in case the PC is being read */
 435                 if (instruction.info.data_proc.Rn == 15)
 436                         Rn += 2 * instruction_size;
 437
 438                 if (instruction.type == ARM_AND)
 439                         Rd = Rn & shifter_operand;
 440                 else if (instruction.type == ARM_EOR)
 441                         Rd = Rn ^ shifter_operand;
 442                 else if (instruction.type == ARM_SUB)
 443                         Rd = Rn - shifter_operand;
 444                 else if (instruction.type == ARM_RSB)
 445                         Rd = shifter_operand - Rn;
 446                 else if (instruction.type == ARM_ADD)
 447                         Rd = Rn + shifter_operand;
 448                 else if (instruction.type == ARM_ADC)
 449                         Rd = Rn + shifter_operand + (C & 1);
 450                 else if (instruction.type == ARM_SBC)
 451                         Rd = Rn - shifter_operand - (C & 1) ? 0 : 1;
 452                 else if (instruction.type == ARM_RSC)
 453                         Rd = shifter_operand - Rn - (C & 1) ? 0 : 1;
 454                 else if (instruction.type == ARM_ORR)
 455                         Rd = Rn | shifter_operand;
 456                 else if (instruction.type == ARM_BIC)
 457                         Rd = Rn & ~(shifter_operand);
 458                 else if (instruction.type == ARM_MOV)
 459                         Rd = shifter_operand;
 460                 else if (instruction.type == ARM_MVN)
 461                         Rd = ~shifter_operand;
 462                 else
 463                         LOG_WARNING("unhandled instruction type");
 464
 465                 if (dry_run_pc)
 466                 {
 467                         if (instruction.info.data_proc.Rd == 15)
 468                         {
 469                                 *dry_run_pc = Rd;
 470                                 return ERROR_OK;
 471                         }
 472                         else
 473                         {
 474                                 *dry_run_pc = current_pc + instruction_size;
 475                         }
 476
 477                         return ERROR_OK;
 478                 }
 479                 else
 480                 {
 481                         sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
 482                         LOG_WARNING("no updating of flags yet");
 483
 484                         if (instruction.info.data_proc.Rd == 15)
 485                                 return ERROR_OK;
 486                 }
 487         }
 488         /* compare instructions (CMP, CMN, TST, TEQ) */
 489         else if ((instruction.type >= ARM_TST) && (instruction.type <= ARM_CMN))
 490         {
 491                 if (dry_run_pc)
 492                 {
 493                         *dry_run_pc = current_pc + instruction_size;
 494                         return ERROR_OK;
 495                 }
 496                 else
 497                 {
 498                         LOG_WARNING("no updating of flags yet");
 499                 }
 500         }
 501         /* load register instructions */
 502         else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
 503         {
 504                 uint32_t load_address = 0, modified_address = 0, load_value;
 505                 uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
 506
 507                 /* adjust Rn in case the PC is being read */
 508                 if (instruction.info.load_store.Rn == 15)
 509                         Rn += 2 * instruction_size;
 510
 511                 if (instruction.info.load_store.offset_mode == 0)
 512                 {
 513                         if (instruction.info.load_store.U)
 514                                 modified_address = Rn + instruction.info.load_store.offset.offset;
 515                         else
 516                                 modified_address = Rn - instruction.info.load_store.offset.offset;
 517                 }
 518                 else if (instruction.info.load_store.offset_mode == 1)
 519                 {
 520                         uint32_t offset;
 521                         uint32_t Rm = sim->get_reg_mode(sim, instruction.info.load_store.offset.reg.Rm);
 522                         uint8_t shift = instruction.info.load_store.offset.reg.shift;
 523                         uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
 524                         uint8_t carry = sim->get_cpsr(sim, 29, 1);
 525
 526                         offset = arm_shift(shift, Rm, shift_imm, &carry);
 527
 528                         if (instruction.info.load_store.U)
 529                                 modified_address = Rn + offset;
 530                         else
 531                                 modified_address = Rn - offset;
 532                 }
 533                 else
 534                 {
 535                         LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
 536                 }
 537
 538                 if (instruction.info.load_store.index_mode == 0)
 539                 {
 540                         /* offset mode
 541                          * we load from the modified address, but don't change the base address register */
 542                         load_address = modified_address;
 543                         modified_address = Rn;
 544                 }
 545                 else if (instruction.info.load_store.index_mode == 1)
 546                 {
 547                         /* pre-indexed mode
 548                          * we load from the modified address, and write it back to the base address register */
 549                         load_address = modified_address;
 550                 }
 551                 else if (instruction.info.load_store.index_mode == 2)
 552                 {
 553                         /* post-indexed mode
 554                          * we load from the unmodified address, and write the modified address back */
 555                          load_address = Rn;
 556                 }
 557
 558                 if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15))
 559                 {
 560                         if ((retval = target_read_u32(target, load_address, &load_value)) != ERROR_OK)
 561                         {
 562                                 return retval;
 563                         }
 564                 }
 565
 566                 if (dry_run_pc)
 567                 {
 568                         if (instruction.info.load_store.Rd == 15)
 569                         {
 570                                 *dry_run_pc = load_value;
 571                                 return ERROR_OK;
 572                         }
 573                         else
 574                         {
 575                                 *dry_run_pc = current_pc + instruction_size;
 576                         }
 577
 578                         return ERROR_OK;
 579                 }
 580                 else
 581                 {
 582                         if ((instruction.info.load_store.index_mode == 1) ||
 583                                 (instruction.info.load_store.index_mode == 2))
 584                         {
 585                                 sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
 586                         }
 587                         sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
 588
 589                         if (instruction.info.load_store.Rd == 15)
 590                                 return ERROR_OK;
 591                 }
 592         }
 593         /* load multiple instruction */
 594         else if (instruction.type == ARM_LDM)
 595         {
 596                 int i;
 597                 uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
 598                 uint32_t load_values[16];
 599                 int bits_set = 0;
 600
 601                 for (i = 0; i < 16; i++)
 602                 {
 603                         if (instruction.info.load_store_multiple.register_list & (1 << i))
 604                                 bits_set++;
 605                 }
 606
 607                 switch (instruction.info.load_store_multiple.addressing_mode)
 608                 {
 609                         case 0: /* Increment after */
 610                                 Rn = Rn;
 611                                 break;
 612                         case 1: /* Increment before */
 613                                 Rn = Rn + 4;
 614                                 break;
 615                         case 2: /* Decrement after */
 616                                 Rn = Rn - (bits_set * 4) + 4;
 617                                 break;
 618                         case 3: /* Decrement before */
 619                                 Rn = Rn - (bits_set * 4);
 620                                 break;
 621                 }
 622
 623                 for (i = 0; i < 16; i++)
 624                 {
 625                         if (instruction.info.load_store_multiple.register_list & (1 << i))
 626                         {
 627                                 if ((!dry_run_pc) || (i == 15))
 628                                 {
 629                                         target_read_u32(target, Rn, &load_values[i]);
 630                                 }
 631                                 Rn += 4;
 632                         }
 633                 }
 634
 635                 if (dry_run_pc)
 636                 {
 637                         if (instruction.info.load_store_multiple.register_list & 0x8000)
 638                         {
 639                                 *dry_run_pc = load_values[15];
 640                                 return ERROR_OK;
 641                         }
 642                 }
 643                 else
 644                 {
 645                         enum armv4_5_mode mode = sim->get_mode(sim);
 646                         int update_cpsr = 0;
 647
 648                         if (instruction.info.load_store_multiple.S)
 649                         {
 650                                 if (instruction.info.load_store_multiple.register_list & 0x8000)
 651                                         update_cpsr = 1;
 652                                 else
 653                                         mode = ARMV4_5_MODE_USR;
 654                         }
 655
 656                         for (i = 0; i < 16; i++)
 657                         {
 658                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 659                                 {
 660                                         sim->set_reg_mode(sim, i, load_values[i]);
 661                                 }
 662                         }
 663
 664                         if (update_cpsr)
 665                         {
 666                                 uint32_t spsr = sim->get_reg_mode(sim, 16);
 667                                 sim->set_reg(sim, ARMV4_5_CPSR, spsr);
 668                         }
 669
 670                         /* base register writeback */
 671                         if (instruction.info.load_store_multiple.W)
 672                                 sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
 673
 674                         if (instruction.info.load_store_multiple.register_list & 0x8000)
 675                                 return ERROR_OK;
 676                 }
 677         }
 678         /* store multiple instruction */
 679         else if (instruction.type == ARM_STM)
 680         {
 681                 int i;
 682
 683                 if (dry_run_pc)
 684                 {
 685                         /* STM wont affect PC (advance by instruction size */
 686                 }
 687                 else
 688                 {
 689                         uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
 690                         int bits_set = 0;
 691                         enum armv4_5_mode mode = sim->get_mode(sim);
 692
 693                         for (i = 0; i < 16; i++)
 694                         {
 695                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 696                                         bits_set++;
 697                         }
 698
 699                         if (instruction.info.load_store_multiple.S)
 700                         {
 701                                 mode = ARMV4_5_MODE_USR;
 702                         }
 703
 704                         switch (instruction.info.load_store_multiple.addressing_mode)
 705                         {
 706                                 case 0: /* Increment after */
 707                                         Rn = Rn;
 708                                         break;
 709                                 case 1: /* Increment before */
 710                                         Rn = Rn + 4;
 711                                         break;
 712                                 case 2: /* Decrement after */
 713                                         Rn = Rn - (bits_set * 4) + 4;
 714                                         break;
 715                                 case 3: /* Decrement before */
 716                                         Rn = Rn - (bits_set * 4);
 717                                         break;
 718                         }
 719
 720                         for (i = 0; i < 16; i++)
 721                         {
 722                                 if (instruction.info.load_store_multiple.register_list & (1 << i))
 723                                 {
 724                                         target_write_u32(target, Rn, sim->get_reg_mode(sim, i));
 725                                         Rn += 4;
 726                                 }
 727                         }
 728
 729                         /* base register writeback */
 730                         if (instruction.info.load_store_multiple.W)
 731                                 sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
 732
 733                 }
 734         }
 735         else if (!dry_run_pc)
 736         {
 737                 /* the instruction wasn't handled, but we're supposed to simulate it
 738                  */
 739                 LOG_ERROR("Unimplemented instruction, could not simulate it.");
 740                 return ERROR_FAIL;
 741         }
 742
 743         if (dry_run_pc)
 744         {
 745                 *dry_run_pc = current_pc + instruction_size;
 746                 return ERROR_OK;
 747         }
 748         else
 749         {
 750                 sim->set_reg(sim, 15, current_pc + instruction_size);
 751                 return ERROR_OK;
 752         }
 753
 754 }
 755
 756 static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
 757 {
 758         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 759
 760         return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
 761 }
 762
 763 static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
 764 {
 765         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 766
 767         buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
 768 }
 769
 770 static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
 771 {
 772         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 773
 774         return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32);
 775 }
 776
 777 static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
 778 {
 779         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 780
 781         buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32, value);
 782 }
 783
 784 static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
 785 {
 786         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 787
 788         return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
 789 }
 790
 791 static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
 792 {
 793         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 794
 795         return armv4_5->core_state;
 796 }
 797
 798 static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
 799 {
 800         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 801
 802         armv4_5->core_state = mode;
 803 }
 804
 805
 806 static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
 807 {
 808         armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
 809
 810         return armv4_5->core_mode;
 811 }
 812
 813
 814
 815 int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
 816 {
 817         armv4_5_common_t *armv4_5 = target->arch_info;
 818
 819         struct arm_sim_interface sim;
 820
 821         sim.user_data=armv4_5;
 822         sim.get_reg=&armv4_5_get_reg;
 823         sim.set_reg=&armv4_5_set_reg;
 824         sim.get_reg_mode=&armv4_5_get_reg_mode;
 825         sim.set_reg_mode=&armv4_5_set_reg_mode;
 826         sim.get_cpsr=&armv4_5_get_cpsr;
 827         sim.get_mode=&armv4_5_get_mode;
 828         sim.get_state=&armv4_5_get_state;
 829         sim.set_state=&armv4_5_set_state;
 830
 831         return arm_simulate_step_core(target, dry_run_pc, &sim);
 832
 833 }
 834