2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2006 by Magnus Lundin
8 * Copyright (C) 2008 by Spencer Oliver
11 * Copyright (C) 2009 by Øyvind Harboe
12 * oyvind.harboe@zylin.com
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
27 #ifndef __ARM_OPCODES_H
28 #define __ARM_OPCODES_H
32 * Macros used to generate various ARM or Thumb opcodes.
35 /* ARM mode instructions */
37 /* Store multiple increment after
39 * List: for each bit in list: store register
40 * S: in priviledged mode: store user-mode registers
41 * W = 1: update the base register. W = 0: leave the base register untouched
43 #define ARMV4_5_STMIA(Rn, List, S, W) \
44 (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
46 /* Load multiple increment after
48 * List: for each bit in list: store register
49 * S: in priviledged mode: store user-mode registers
50 * W = 1: update the base register. W = 0: leave the base register untouched
52 #define ARMV4_5_LDMIA(Rn, List, S, W) \
53 (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
56 #define ARMV4_5_NOP (0xe1a08008)
58 /* Move PSR to general purpose register
59 * R = 1: SPSR R = 0: CPSR
62 #define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
65 * Rd: register to store
68 #define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
71 * Rd: register to load
74 #define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
76 /* Move general purpose register to PSR
77 * R = 1: SPSR R = 0: CPSR
79 * 1: control field 2: extension field 4: status field 8: flags field
82 #define ARMV4_5_MSR_GP(Rm, Field, R) \
83 (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
84 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
85 (0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
87 /* Load Register Word Immediate Post-Index
88 * Rd: register to load
91 #define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
93 /* Load Register Halfword Immediate Post-Index
94 * Rd: register to load
97 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
99 /* Load Register Byte Immediate Post-Index
100 * Rd: register to load
103 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
105 /* Store register Word Immediate Post-Index
106 * Rd: register to store
109 #define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
111 /* Store register Halfword Immediate Post-Index
112 * Rd: register to store
115 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
117 /* Store register Byte Immediate Post-Index
118 * Rd: register to store
121 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
124 * Im: Branch target (left-shifted by 2 bits, added to PC)
125 * L: 1: branch and link 0: branch only
127 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
129 /* Branch and exchange (ARM state)
130 * Rm: register holding branch target address
132 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
134 /* Store data from coprocessor to consecutive memory
135 * See Armv7-A arch doc section A8.6.187
136 * P: 1=index mode (offset from Rn)
137 * U: 1=add, 0=subtract Rn address with imm
138 * D: Opcode D encoding
139 * W: write back the offset start address to the Rn register
140 * CP: Coprocessor number (4 bits)
141 * CRd: Coprocessor source register (4 bits)
142 * Rn: Base register for memory address (4 bits)
143 * imm: Immediate value (0 - 1020, must be divisible by 4)
145 #define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
146 (0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
147 ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
149 /* Loads data from consecutive memory to coprocessor
150 * See Armv7-A arch doc section A8.6.51
151 * P: 1=index mode (offset from Rn)
152 * U: 1=add, 0=subtract Rn address with imm
153 * D: Opcode D encoding
154 * W: write back the offset start address to the Rn register
155 * CP: Coprocessor number (4 bits)
156 * CRd: Coprocessor dest register (4 bits)
157 * Rn: Base register for memory address (4 bits)
158 * imm: Immediate value (0 - 1020, must be divisible by 4)
160 #define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
161 (0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
162 ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
164 /* Move to ARM register from coprocessor
165 * CP: Coprocessor number
166 * op1: Coprocessor opcode
167 * Rd: destination register
168 * CRn: first coprocessor operand
169 * CRm: second coprocessor operand
170 * op2: Second coprocessor opcode
172 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
173 (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
174 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
176 /* Move to coprocessor from ARM register
177 * CP: Coprocessor number
178 * op1: Coprocessor opcode
179 * Rd: destination register
180 * CRn: first coprocessor operand
181 * CRm: second coprocessor operand
182 * op2: Second coprocessor opcode
184 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
185 (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
186 | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
188 /* Breakpoint instruction (ARMv5)
189 * Im: 16-bit immediate
191 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
194 /* Thumb mode instructions
196 * NOTE: these 16-bit opcodes fill both halves of a word with the same
197 * value. The reason for this is that when we need to execute Thumb
198 * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
199 * we must shift 32 bits to the bus using scan chain 1 ... if we write
200 * both halves, we don't need to track which half matters. On ARMv6 and
201 * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
202 * register does not accept Thumb (or Thumb2) opcodes.
205 /* Store register (Thumb mode)
206 * Rd: source register
209 #define ARMV4_5_T_STR(Rd, Rn) \
210 ((0x6000 | (Rd) | ((Rn) << 3)) | \
211 ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
213 /* Load register (Thumb state)
214 * Rd: destination register
217 #define ARMV4_5_T_LDR(Rd, Rn) \
218 ((0x6800 | ((Rn) << 3) | (Rd)) \
219 | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
221 /* Load multiple (Thumb state)
223 * List: for each bit in list: store register
225 #define ARMV4_5_T_LDMIA(Rn, List) \
226 ((0xc800 | ((Rn) << 8) | (List)) \
227 | ((0xc800 | ((Rn) << 8) | (List)) << 16))
229 /* Load register with PC relative addressing
230 * Rd: register to load
232 #define ARMV4_5_T_LDR_PCREL(Rd) \
233 ((0x4800 | ((Rd) << 8)) \
234 | ((0x4800 | ((Rd) << 8)) << 16))
236 /* Move hi register (Thumb mode)
237 * Rd: destination register
238 * Rm: source register
240 #define ARMV4_5_T_MOV(Rd, Rm) \
241 ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
242 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
243 | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
244 (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
246 /* No operation (Thumb mode)
247 * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
248 * architected NOPs, 16-bit and 32-bit.
250 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
252 /* Move immediate to register (Thumb state)
253 * Rd: destination register
254 * Im: 8-bit immediate value
256 #define ARMV4_5_T_MOV_IM(Rd, Im) \
257 ((0x2000 | ((Rd) << 8) | (Im)) \
258 | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
260 /* Branch and Exchange
261 * Rm: register containing branch target
263 #define ARMV4_5_T_BX(Rm) \
264 ((0x4700 | ((Rm) << 3)) \
265 | ((0x4700 | ((Rm) << 3)) << 16))
267 /* Branch (Thumb state)
270 #define ARMV4_5_T_B(Imm) \
272 | ((0xe000 | (Imm)) << 16))
274 /* Breakpoint instruction (ARMv5) (Thumb state)
275 * Im: 8-bit immediate
277 #define ARMV5_T_BKPT(Im) \
279 | ((0xbe00 | (Im)) << 16))
281 /* Move to Register from Special Register
282 * 32 bit Thumb2 instruction
283 * Rd: destination register
284 * SYSm: source special register
286 #define ARM_T2_MRS(Rd, SYSm) \
287 ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
289 /* Move from Register from Special Register
290 * 32 bit Thumb2 instruction
291 * Rd: source register
292 * SYSm: destination special register
294 #define ARM_T2_MSR(SYSm, Rn) \
295 ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
297 /* Change Processor State.
298 * 16 bit Thumb2 instruction
299 * Rd: source register
300 * IF: A_FLAG and/or I_FLAG and/or F_FLAG
305 #define ARM_T2_CPSID(IF) \
306 ((0xB660 | (1 << 8) | ((IF)&0x3)) \
307 | ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
308 #define ARM_T2_CPSIE(IF) \
309 ((0xB660 | (0 << 8) | ((IF)&0x3)) \
310 | ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
312 #endif /* __ARM_OPCODES_H */