2 * Copyright (C) 2005 by Dominic Rath
5 * Copyright (C) 2006 by Magnus Lundin
8 * Copyright (C) 2008 by Spencer Oliver
11 * Copyright (C) 2009 by Øyvind Harboe
12 * oyvind.harboe@zylin.com
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program. If not, see <http://www.gnu.org/licenses/>.
28 #ifndef OPENOCD_TARGET_ARM_OPCODES_H
29 #define OPENOCD_TARGET_ARM_OPCODES_H
33 * Macros used to generate various ARM or Thumb opcodes.
36 /* ARM mode instructions */
38 /* Store multiple increment after
40 * list: for each bit in list: store register
41 * s: in privileged mode: store user-mode registers
42 * w = 1: update the base register. w = 0: leave the base register untouched
44 #define ARMV4_5_STMIA(rn, list, s, w) \
45 (0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
47 /* Load multiple increment after
49 * list: for each bit in list: store register
50 * s: in privileged mode: store user-mode registers
51 * w = 1: update the base register. w = 0: leave the base register untouched
53 #define ARMV4_5_LDMIA(rn, list, s, w) \
54 (0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
57 #define ARMV4_5_NOP (0xe1a08008)
59 /* Move PSR to general purpose register
60 * r = 1: SPSR r = 0: CPSR
63 #define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
66 * rd: register to store
69 #define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
72 * rd: register to load
75 #define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
77 /* Move general purpose register to PSR
78 * r = 1: SPSR r = 0: CPSR
80 * 1: control field 2: extension field 4: status field 8: flags field
83 #define ARMV4_5_MSR_GP(rm, field, r) \
84 (0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
85 #define ARMV4_5_MSR_IM(im, rotate, field, r) \
86 (0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
88 /* Load Register Word Immediate Post-Index
89 * rd: register to load
92 #define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
94 /* Load Register Halfword Immediate Post-Index
95 * rd: register to load
98 #define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
100 /* Load Register Byte Immediate Post-Index
101 * rd: register to load
104 #define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
106 /* Store register Word Immediate Post-Index
107 * rd: register to store
110 #define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
112 /* Store register Halfword Immediate Post-Index
113 * rd: register to store
116 #define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
118 /* Store register Byte Immediate Post-Index
119 * rd: register to store
122 #define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
125 * im: Branch target (left-shifted by 2 bits, added to PC)
126 * l: 1: branch and link 0: branch only
128 #define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
130 /* Branch and exchange (ARM state)
131 * rm: register holding branch target address
133 #define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
135 /* Copies two words from two ARM core registers
136 * into a doubleword extension register, or
137 * from a doubleword extension register to two ARM core registers.
138 * See Armv7-A arch reference manual section A8.8.345
139 * rt: Arm core register 1
140 * rt2: Arm core register 2
141 * vm: The doubleword extension register
143 * op: to_arm_registers = (op == ‘1’);
145 #define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
146 (0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
147 ((rt) << 12) | ((m) << 5) | (vm))
149 /* Moves the value of the FPSCR to an ARM core register
150 * rt: Arm core register
152 #define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
154 /* Moves the value of an ARM core register to the FPSCR.
155 * rt: Arm core register
157 #define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
159 /* Store data from coprocessor to consecutive memory
160 * See Armv7-A arch doc section A8.6.187
161 * p: 1=index mode (offset from rn)
162 * u: 1=add, 0=subtract rn address with imm
163 * d: Opcode D encoding
164 * w: write back the offset start address to the rn register
165 * cp: Coprocessor number (4 bits)
166 * crd: Coprocessor source register (4 bits)
167 * rn: Base register for memory address (4 bits)
168 * imm: Immediate value (0 - 1020, must be divisible by 4)
170 #define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
171 (0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
172 ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
174 /* Loads data from consecutive memory to coprocessor
175 * See Armv7-A arch doc section A8.6.51
176 * p: 1=index mode (offset from rn)
177 * u: 1=add, 0=subtract rn address with imm
178 * d: Opcode D encoding
179 * w: write back the offset start address to the rn register
180 * cp: Coprocessor number (4 bits)
181 * crd: Coprocessor dest register (4 bits)
182 * rn: Base register for memory address (4 bits)
183 * imm: Immediate value (0 - 1020, must be divisible by 4)
185 #define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
186 (0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
187 ((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
189 /* Move to ARM register from coprocessor
190 * cp: Coprocessor number
191 * op1: Coprocessor opcode
192 * rd: destination register
193 * crn: first coprocessor operand
194 * crm: second coprocessor operand
195 * op2: Second coprocessor opcode
197 #define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
198 (0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
199 | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
201 /* Move to coprocessor from ARM register
202 * cp: Coprocessor number
203 * op1: Coprocessor opcode
204 * rd: destination register
205 * crn: first coprocessor operand
206 * crm: second coprocessor operand
207 * op2: Second coprocessor opcode
209 #define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
210 (0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
211 | ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
213 /* Breakpoint instruction (ARMv5)
214 * im: 16-bit immediate
216 #define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
219 /* Thumb mode instructions
221 * NOTE: these 16-bit opcodes fill both halves of a word with the same
222 * value. The reason for this is that when we need to execute Thumb
223 * opcodes on ARM7/ARM9 cores (to switch to ARM state on debug entry),
224 * we must shift 32 bits to the bus using scan chain 1 ... if we write
225 * both halves, we don't need to track which half matters. On ARMv6 and
226 * ARMv7 we don't execute Thumb instructions in debug mode; the ITR
227 * register does not accept Thumb (or Thumb2) opcodes.
230 /* Store register (Thumb mode)
231 * rd: source register
234 #define ARMV4_5_T_STR(rd, rn) \
235 ((0x6000 | (rd) | ((rn) << 3)) | \
236 ((0x6000 | (rd) | ((rn) << 3)) << 16))
238 /* Load register (Thumb state)
239 * rd: destination register
242 #define ARMV4_5_T_LDR(rd, rn) \
243 ((0x6800 | ((rn) << 3) | (rd)) \
244 | ((0x6800 | ((rn) << 3) | (rd)) << 16))
246 /* Load multiple (Thumb state)
248 * list: for each bit in list: store register
250 #define ARMV4_5_T_LDMIA(rn, list) \
251 ((0xc800 | ((rn) << 8) | (list)) \
252 | ((0xc800 | ((rn) << 8) | (list)) << 16))
254 /* Load register with PC relative addressing
255 * rd: register to load
257 #define ARMV4_5_T_LDR_PCREL(rd) \
258 ((0x4800 | ((rd) << 8)) \
259 | ((0x4800 | ((rd) << 8)) << 16))
261 /* Move hi register (Thumb mode)
262 * rd: destination register
263 * rm: source register
265 #define ARMV4_5_T_MOV(rd, rm) \
266 ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
267 (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
268 | ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
269 (((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
271 /* No operation (Thumb mode)
272 * NOTE: this is "MOV r8, r8" ... Thumb2 adds two
273 * architected NOPs, 16-bit and 32-bit.
275 #define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
277 /* Move immediate to register (Thumb state)
278 * rd: destination register
279 * im: 8-bit immediate value
281 #define ARMV4_5_T_MOV_IM(rd, im) \
282 ((0x2000 | ((rd) << 8) | (im)) \
283 | ((0x2000 | ((rd) << 8) | (im)) << 16))
285 /* Branch and Exchange
286 * rm: register containing branch target
288 #define ARMV4_5_T_BX(rm) \
289 ((0x4700 | ((rm) << 3)) \
290 | ((0x4700 | ((rm) << 3)) << 16))
292 /* Branch (Thumb state)
295 #define ARMV4_5_T_B(imm) \
297 | ((0xe000 | (imm)) << 16))
299 /* Breakpoint instruction (ARMv5) (Thumb state)
300 * Im: 8-bit immediate
302 #define ARMV5_T_BKPT(im) \
304 | ((0xbe00 | (im)) << 16))
306 /* Move to Register from Special Register
307 * 32 bit Thumb2 instruction
308 * rd: destination register
309 * sysm: source special register
311 #define ARM_T2_MRS(rd, sysm) \
312 ((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
314 /* Move from Register from Special Register
315 * 32 bit Thumb2 instruction
316 * rd: source register
317 * sysm: destination special register
319 #define ARM_T2_MSR(sysm, rn) \
320 ((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
322 /* Change Processor State.
323 * 16 bit Thumb2 instruction
324 * rd: source register
325 * IF: A_FLAG and/or I_FLAG and/or F_FLAG
330 #define ARM_T2_CPSID(_if) \
331 ((0xB660 | (1 << 8) | ((_if)&0x3)) \
332 | ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
333 #define ARM_T2_CPSIE(_if) \
334 ((0xB660 | (0 << 8) | ((_if)&0x3)) \
335 | ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
337 #endif /* OPENOCD_TARGET_ARM_OPCODES_H */