1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2009 by David Brownell
7 #ifndef OPENOCD_TARGET_ARM_DPM_H
8 #define OPENOCD_TARGET_ARM_DPM_H
12 * This is the interface to the Debug Programmers Model for ARMv6 and
13 * ARMv7 processors. ARMv6 processors (such as ARM11xx implementations)
14 * introduced a model which became part of the ARMv7-AR architecture
15 * which is most familiar through the Cortex-A series parts. While
16 * specific details differ (like how to write the instruction register),
17 * the high level models easily support shared code because those
18 * registers are compatible.
25 /* true if hardware state needs flushing */
30 struct breakpoint *bp;
35 struct watchpoint *wp;
40 * This wraps an implementation of DPM primitives. Each interface
41 * provider supplies a structure like this, which is the glue between
42 * upper level code and the lower level hardware access.
44 * It is a PRELIMINARY AND INCOMPLETE set of primitives, starting with
45 * support for CPU register access.
53 /** Invoke before a series of instruction operations */
54 int (*prepare)(struct arm_dpm *dpm);
56 /** Invoke after a series of instruction operations */
57 int (*finish)(struct arm_dpm *dpm);
59 /** Runs one instruction. */
60 int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
64 /** Runs one instruction, writing data to DCC before execution. */
65 int (*instr_write_data_dcc)(struct arm_dpm *dpm,
66 uint32_t opcode, uint32_t data);
68 int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
69 uint32_t opcode, uint64_t data);
71 /** Runs one instruction, writing data to R0 before execution. */
72 int (*instr_write_data_r0)(struct arm_dpm *dpm,
73 uint32_t opcode, uint32_t data);
75 /** Runs one instruction, writing data to R0 before execution. */
76 int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
77 uint32_t opcode, uint64_t data);
79 /** Optional core-specific operation invoked after CPSR writes. */
80 int (*instr_cpsr_sync)(struct arm_dpm *dpm);
84 /** Runs one instruction, reading data from dcc after execution. */
85 int (*instr_read_data_dcc)(struct arm_dpm *dpm,
86 uint32_t opcode, uint32_t *data);
88 int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
89 uint32_t opcode, uint64_t *data);
91 /** Runs one instruction, reading data from r0 after execution. */
92 int (*instr_read_data_r0)(struct arm_dpm *dpm,
93 uint32_t opcode, uint32_t *data);
95 int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
96 uint32_t opcode, uint64_t *data);
98 struct reg *(*arm_reg_current)(struct arm *arm,
101 /* BREAKPOINT/WATCHPOINT SUPPORT */
104 * Enables one breakpoint or watchpoint by writing to the
105 * hardware registers. The specified breakpoint/watchpoint
106 * must currently be disabled. Indices 0..15 are used for
107 * breakpoints; indices 16..31 are for watchpoints.
109 int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
110 uint32_t addr, uint32_t control);
113 * Disables one breakpoint or watchpoint by clearing its
114 * hardware control registers. Indices are the same ones
115 * accepted by bpwp_enable().
117 int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
119 /* The breakpoint and watchpoint arrays are private to the
120 * DPM infrastructure. There are nbp indices in the dbp
121 * array. There are nwp indices in the dwp array.
130 * Target dependent watchpoint address.
131 * Either the address of the instruction which triggered a watchpoint
132 * or the memory address whose access triggered a watchpoint.
134 target_addr_t wp_addr;
136 /** Recent value of DSCR. */
139 /** Recent exception level on armv8 */
140 unsigned int last_el;
142 /* FIXME -- read/write DCSR methods and symbols */
145 int arm_dpm_setup(struct arm_dpm *dpm);
146 int arm_dpm_initialize(struct arm_dpm *dpm);
148 int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
149 int arm_dpm_read_current_registers(struct arm_dpm *dpm);
150 int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
152 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
154 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
156 /* DSCR bits; see ARMv7a arch spec section C10.3.1.
157 * Not all v7 bits are valid in v6.
159 #define DSCR_CORE_HALTED (0x1 << 0)
160 #define DSCR_CORE_RESTARTED (0x1 << 1)
161 #define DSCR_ENTRY_MASK (0xF << 2)
162 #define DSCR_STICKY_ABORT_PRECISE (0x1 << 6)
163 #define DSCR_STICKY_ABORT_IMPRECISE (0x1 << 7)
164 #define DSCR_STICKY_UNDEFINED (0x1 << 8)
165 #define DSCR_DBG_NOPWRDWN (0x1 << 9) /* v6 only */
166 #define DSCR_DBG_ACK (0x1 << 10)
167 #define DSCR_INT_DIS (0x1 << 11)
168 #define DSCR_CP14_USR_COMMS (0x1 << 12)
169 #define DSCR_ITR_EN (0x1 << 13)
170 #define DSCR_HALT_DBG_MODE (0x1 << 14)
171 #define DSCR_MON_DBG_MODE (0x1 << 15)
172 #define DSCR_SEC_PRIV_INVASV_DIS (0x1 << 16)
173 #define DSCR_SEC_PRIV_NINVASV_DIS (0x1 << 17)
174 #define DSCR_NON_SECURE (0x1 << 18)
175 #define DSCR_DSCRD_IMPRECISE_ABORT (0x1 << 19)
176 #define DSCR_EXT_DCC_MASK (0x3 << 20) /* DTR mode */ /* bits 22, 23 are reserved */
177 #define DSCR_INSTR_COMP (0x1 << 24)
178 #define DSCR_PIPE_ADVANCE (0x1 << 25)
179 #define DSCR_DTRTX_FULL_LATCHED (0x1 << 26)
180 #define DSCR_DTRRX_FULL_LATCHED (0x1 << 27) /* bit 28 is reserved */
181 #define DSCR_DTR_TX_FULL (0x1 << 29)
182 #define DSCR_DTR_RX_FULL (0x1 << 30) /* bit 31 is reserved */
184 #define DSCR_ENTRY(dscr) ((dscr) & 0x3f)
185 #define DSCR_RUN_MODE(dscr) ((dscr) & 0x03)
188 /* Methods of entry into debug mode */
189 #define DSCR_ENTRY_HALT_REQ (0x03)
190 #define DSCR_ENTRY_BREAKPOINT (0x07)
191 #define DSCR_ENTRY_IMPRECISE_WATCHPT (0x0B)
192 #define DSCR_ENTRY_BKPT_INSTR (0x0F)
193 #define DSCR_ENTRY_EXT_DBG_REQ (0x13)
194 #define DSCR_ENTRY_VECT_CATCH (0x17)
195 #define DSCR_ENTRY_D_SIDE_ABORT (0x1B) /* v6 only */
196 #define DSCR_ENTRY_I_SIDE_ABORT (0x1F) /* v6 only */
197 #define DSCR_ENTRY_OS_UNLOCK (0x23)
198 #define DSCR_ENTRY_PRECISE_WATCHPT (0x2B)
201 #define DSCR_EXT_DCC_NON_BLOCKING (0x0 << 20)
202 #define DSCR_EXT_DCC_STALL_MODE (0x1 << 20)
203 #define DSCR_EXT_DCC_FAST_MODE (0x2 << 20) /* bits 22, 23 are reserved */
209 /* DRCR (debug run control register) bits */
210 #define DRCR_HALT (1 << 0)
211 #define DRCR_RESTART (1 << 1)
212 #define DRCR_CLEAR_EXCEPTIONS (1 << 2)
214 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dcsr);
216 /* PRCR (Device Power-down and Reset Control Register) bits */
217 #define PRCR_DEBUG_NO_POWER_DOWN (1 << 0)
218 #define PRCR_WARM_RESET (1 << 1)
219 #define PRCR_HOLD_NON_DEBUG_RESET (1 << 2)
221 /* PRSR (Device Power-down and Reset Status Register) bits */
222 #define PRSR_POWERUP_STATUS (1 << 0)
223 #define PRSR_STICKY_POWERDOWN_STATUS (1 << 1)
224 #define PRSR_RESET_STATUS (1 << 2)
225 #define PRSR_STICKY_RESET_STATUS (1 << 3)
226 #define PRSR_HALTED (1 << 4) /* v7.1 Debug only */
227 #define PRSR_OSLK (1 << 5) /* v7.1 Debug only */
228 #define PRSR_DLK (1 << 6) /* v7.1 Debug only */
230 /* OSLSR (OS Lock Status Register) bits */
231 #define OSLSR_OSLM0 (1 << 0)
232 #define OSLSR_OSLK (1 << 1)
233 #define OSLSR_NTT (1 << 2)
234 #define OSLSR_OSLM1 (1 << 3)
235 #define OSLSR_OSLM (OSLSR_OSLM0|OSLSR_OSLM1)
237 #endif /* OPENOCD_TARGET_ARM_DPM_H */