2 * Copyright (C) 2009 by David Brownell
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #include "armv4_5.h" /* REVISIT to become arm.h */
26 #include <jtag/jtag.h>
28 #include "breakpoints.h"
29 #include "target_type.h"
34 * Implements various ARM DPM operations using architectural debug registers.
35 * These routines layer over core-specific communication methods to cope with
36 * implementation differences between cores like ARM1136 and Cortex-A8.
39 /*----------------------------------------------------------------------*/
45 /* Read coprocessor */
46 static int dpm_mrc(struct target *target, int cpnum,
47 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
50 struct arm *arm = target_to_arm(target);
51 struct arm_dpm *dpm = arm->dpm;
54 retval = dpm->prepare(dpm);
55 if (retval != ERROR_OK)
58 LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
60 (int) CRm, (int) op2);
62 /* read coprocessor register into R0; return via DCC */
63 retval = dpm->instr_read_data_r0(dpm,
64 ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
67 /* (void) */ dpm->finish(dpm);
71 static int dpm_mcr(struct target *target, int cpnum,
72 uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
75 struct arm *arm = target_to_arm(target);
76 struct arm_dpm *dpm = arm->dpm;
79 retval = dpm->prepare(dpm);
80 if (retval != ERROR_OK)
83 LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
85 (int) CRm, (int) op2);
87 /* read DCC into r0; then write coprocessor register from R0 */
88 retval = dpm->instr_write_data_r0(dpm,
89 ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
92 /* (void) */ dpm->finish(dpm);
96 /*----------------------------------------------------------------------*/
99 * Register access utilities
102 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
103 * Routines *must* restore the original mode before returning!!
105 static int dpm_modeswitch(struct arm_dpm *dpm, enum armv4_5_mode mode)
110 /* restore previous mode */
111 if (mode == ARM_MODE_ANY)
112 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
114 /* else force to the specified mode */
118 retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
120 if (dpm->instr_cpsr_sync)
121 retval = dpm->instr_cpsr_sync(dpm);
126 /* just read the register -- rely on the core mode being right */
127 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
134 /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */
135 retval = dpm->instr_read_data_dcc(dpm,
136 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
140 /* "MOV r0, pc"; then return via DCC */
141 retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
143 /* NOTE: this seems like a slightly awkward place to update
144 * this value ... but if the PC gets written (the only way
145 * to change what we compute), the arch spec says subsequent
146 * reads return values which are "unpredictable". So this
147 * is always right except in those broken-by-intent cases.
149 switch (dpm->arm->core_state) {
153 case ARM_STATE_THUMB:
154 case ARM_STATE_THUMB_EE:
157 case ARM_STATE_JAZELLE:
158 /* core-specific ... ? */
159 LOG_WARNING("Jazelle PC adjustment unknown");
164 /* 16: "MRS r0, CPSR"; then return via DCC
165 * 17: "MRS r0, SPSR"; then return via DCC
167 retval = dpm->instr_read_data_r0(dpm,
168 ARMV4_5_MRS(0, regnum & 1),
173 if (retval == ERROR_OK) {
174 buf_set_u32(r->value, 0, 32, value);
177 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
183 /* just write the register -- rely on the core mode being right */
184 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
187 uint32_t value = buf_get_u32(r->value, 0, 32);
191 /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */
192 retval = dpm->instr_write_data_dcc(dpm,
193 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
197 /* read r0 from DCC; then "MOV pc, r0" */
198 retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
201 /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
202 * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
204 retval = dpm->instr_write_data_r0(dpm,
205 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
208 if (regnum == 16 && dpm->instr_cpsr_sync)
209 retval = dpm->instr_cpsr_sync(dpm);
214 if (retval == ERROR_OK) {
216 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
223 * Read basic registers of the the current context: R0 to R15, and CPSR;
224 * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
225 * In normal operation this is called on entry to halting debug state,
226 * possibly after some other operations supporting restore of debug state
227 * or making sure the CPU is fully idle (drain write buffer, etc).
229 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
231 struct arm *arm = dpm->arm;
236 retval = dpm->prepare(dpm);
237 if (retval != ERROR_OK)
240 /* read R0 first (it's used for scratch), then CPSR */
241 r = arm->core_cache->reg_list + 0;
243 retval = dpm_read_reg(dpm, r, 0);
244 if (retval != ERROR_OK)
249 retval = dpm->instr_read_data_r0(dpm, ARMV4_5_MRS(0, 0), &cpsr);
250 if (retval != ERROR_OK)
253 /* update core mode and state, plus shadow mapping for R8..R14 */
254 arm_set_cpsr(arm, cpsr);
256 /* REVISIT we can probably avoid reading R1..R14, saving time... */
257 for (unsigned i = 1; i < 16; i++) {
258 r = arm_reg_current(arm, i);
262 retval = dpm_read_reg(dpm, r, i);
263 if (retval != ERROR_OK)
267 /* NOTE: SPSR ignored (if it's even relevant). */
269 /* REVISIT the debugger can trigger various exceptions. See the
270 * ARMv7A architecture spec, section C5.7, for more info about
271 * what defenses are needed; v6 debug has the most issues.
275 /* (void) */ dpm->finish(dpm);
280 * Writes all modified core registers for all processor modes. In normal
281 * operation this is called on exit from halting debug state.
283 * @param dpm: represents the processor
284 * @param bpwp: true ensures breakpoints and watchpoints are set,
285 * false ensures they are cleared
287 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
289 struct arm *arm = dpm->arm;
290 struct reg_cache *cache = arm->core_cache;
294 retval = dpm->prepare(dpm);
295 if (retval != ERROR_OK)
298 /* enable/disable watchpoints */
299 for (unsigned i = 0; i < dpm->nwp; i++) {
300 struct dpm_wp *dwp = dpm->dwp + i;
301 struct watchpoint *wp = dwp->wp;
304 /* Avoid needless I/O ... leave watchpoints alone
305 * unless they're removed, or need updating because
306 * of single-stepping or running debugger code.
312 /* removed or startup; we must disable it */
317 /* disabled, but we must set it */
318 dwp->dirty = disable = false;
323 /* set, but we must temporarily disable it */
324 dwp->dirty = disable = true;
329 retval = dpm->bpwp_disable(dpm, 16 + i);
331 retval = dpm->bpwp_enable(dpm, 16 + i,
332 wp->address, dwp->control);
334 if (retval != ERROR_OK)
335 LOG_ERROR("%s: can't %s HW watchpoint %d",
336 target_name(arm->target),
337 disable ? "disable" : "enable",
341 /* NOTE: writes to breakpoint and watchpoint registers might
342 * be queued, and need (efficient/batched) flushing later.
345 /* Scan the registers until we find one that's both dirty and
346 * eligible for flushing. Flush that and everything else that
347 * shares the same core mode setting. Typically this won't
348 * actually find anything to do...
351 enum armv4_5_mode mode = ARM_MODE_ANY;
355 /* check everything except our scratch register R0 */
356 for (unsigned i = 1; i < cache->num_regs; i++) {
360 /* also skip PC, CPSR, and non-dirty */
363 if (arm->cpsr == cache->reg_list + i)
365 if (!cache->reg_list[i].dirty)
368 r = cache->reg_list[i].arch_info;
371 /* may need to pick and set a mode */
373 enum armv4_5_mode tmode;
376 mode = tmode = r->mode;
378 /* cope with special cases */
381 /* r8..r12 "anything but FIQ" case;
382 * we "know" core mode is accurate
383 * since we haven't changed it yet
385 if (arm->core_mode == ARM_MODE_FIQ
388 tmode = ARM_MODE_USR;
396 /* REVISIT error checks */
397 if (tmode != ARM_MODE_ANY)
398 retval = dpm_modeswitch(dpm, tmode);
403 retval = dpm_write_reg(dpm,
411 /* Restore original CPSR ... assuming either that we changed it,
412 * or it's dirty. Must write PC to ensure the return address is
413 * defined, and must not write it before CPSR.
415 retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
416 arm->cpsr->dirty = false;
418 retval = dpm_write_reg(dpm, &cache->reg_list[15], 15);
419 cache->reg_list[15].dirty = false;
421 /* flush R0 -- it's *very* dirty by now */
422 retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
423 cache->reg_list[0].dirty = false;
425 /* (void) */ dpm->finish(dpm);
430 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
431 * specified register ... works around flakiness from ARM core calls.
432 * Caller already filtered out SPSR access; mode is never MODE_SYS
435 static enum armv4_5_mode dpm_mapmode(struct arm *arm,
436 unsigned num, enum armv4_5_mode mode)
438 enum armv4_5_mode amode = arm->core_mode;
440 /* don't switch if the mode is already correct */
441 if (amode == ARM_MODE_SYS)
442 amode = ARM_MODE_USR;
447 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
452 /* r8..r12 aren't shadowed for anything except FIQ */
454 if (mode == ARM_MODE_FIQ)
457 /* r13/sp, and r14/lr are always shadowed */
462 LOG_WARNING("invalid register #%u", num);
470 * Standard ARM register accessors ... there are three methods
471 * in "struct arm", to support individual read/write and bulk read
475 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
476 int regnum, enum armv4_5_mode mode)
478 struct arm_dpm *dpm = target_to_arm(target)->dpm;
481 if (regnum < 0 || regnum > 16)
482 return ERROR_INVALID_ARGUMENTS;
485 if (mode != ARM_MODE_ANY)
488 mode = dpm_mapmode(dpm->arm, regnum, mode);
490 /* REVISIT what happens if we try to read SPSR in a core mode
491 * which has no such register?
494 retval = dpm->prepare(dpm);
495 if (retval != ERROR_OK)
498 if (mode != ARM_MODE_ANY) {
499 retval = dpm_modeswitch(dpm, mode);
500 if (retval != ERROR_OK)
504 retval = dpm_read_reg(dpm, r, regnum);
505 /* always clean up, regardless of error */
507 if (mode != ARM_MODE_ANY)
508 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
511 /* (void) */ dpm->finish(dpm);
515 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
516 int regnum, enum armv4_5_mode mode, uint32_t value)
518 struct arm_dpm *dpm = target_to_arm(target)->dpm;
522 if (regnum < 0 || regnum > 16)
523 return ERROR_INVALID_ARGUMENTS;
526 if (mode != ARM_MODE_ANY)
529 mode = dpm_mapmode(dpm->arm, regnum, mode);
531 /* REVISIT what happens if we try to write SPSR in a core mode
532 * which has no such register?
535 retval = dpm->prepare(dpm);
536 if (retval != ERROR_OK)
539 if (mode != ARM_MODE_ANY) {
540 retval = dpm_modeswitch(dpm, mode);
541 if (retval != ERROR_OK)
545 retval = dpm_write_reg(dpm, r, regnum);
546 /* always clean up, regardless of error */
548 if (mode != ARM_MODE_ANY)
549 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
552 /* (void) */ dpm->finish(dpm);
556 static int arm_dpm_full_context(struct target *target)
558 struct arm *arm = target_to_arm(target);
559 struct arm_dpm *dpm = arm->dpm;
560 struct reg_cache *cache = arm->core_cache;
564 retval = dpm->prepare(dpm);
565 if (retval != ERROR_OK)
569 enum armv4_5_mode mode = ARM_MODE_ANY;
573 /* We "know" arm_dpm_read_current_registers() was called so
574 * the unmapped registers (R0..R7, PC, AND CPSR) and some
575 * view of R8..R14 are current. We also "know" oddities of
576 * register mapping: special cases for R8..R12 and SPSR.
578 * Pick some mode with unread registers and read them all.
581 for (unsigned i = 0; i < cache->num_regs; i++) {
584 if (cache->reg_list[i].valid)
586 r = cache->reg_list[i].arch_info;
588 /* may need to pick a mode and set CPSR */
593 /* For R8..R12 when we've entered debug
594 * state in FIQ mode... patch mode.
596 if (mode == ARM_MODE_ANY)
599 /* REVISIT error checks */
600 retval = dpm_modeswitch(dpm, mode);
605 /* CPSR was read, so "R16" must mean SPSR */
606 retval = dpm_read_reg(dpm,
608 (r->num == 16) ? 17 : r->num);
614 retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
615 /* (void) */ dpm->finish(dpm);
621 /*----------------------------------------------------------------------*/
624 * Breakpoint and Watchpoint support.
626 * Hardware {break,watch}points are usually left active, to minimize
627 * debug entry/exit costs. When they are set or cleared, it's done in
628 * batches. Also, DPM-conformant hardware can update debug registers
629 * regardless of whether the CPU is running or halted ... though that
630 * fact isn't currently leveraged.
633 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index,
634 struct watchpoint *wp)
636 uint32_t addr = wp->address;
639 /* this hardware doesn't support data value matching or masking */
640 if (wp->value || wp->mask != ~(uint32_t)0) {
641 LOG_DEBUG("watchpoint values and masking not supported");
642 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
645 control = (1 << 0) /* enable */
646 | (3 << 1); /* both user and privileged access */
660 /* Match 1, 2, or all 4 byte addresses in this word.
662 * FIXME: v7 hardware allows lengths up to 2 GB, and has eight
663 * byte address select bits. Support larger wp->length, if addr
664 * is suitably aligned.
666 switch (wp->length) {
668 control |= (1 << (addr & 3)) << 5;
672 /* require 2-byte alignment */
674 control |= (3 << (addr & 2)) << 5;
679 /* require 4-byte alignment */
686 LOG_DEBUG("bad watchpoint length or alignment");
687 return ERROR_INVALID_ARGUMENTS;
690 /* other control bits:
691 * bits 9:12 == 0 ... only checking up to four byte addresses (v7 only)
692 * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
693 * bit 20 == 0 ... not linked to a context ID
694 * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
697 dpm->dwp[index].wp = wp;
698 dpm->dwp[index].control = control;
699 dpm->dwp[index].dirty = true;
701 /* hardware is updated in write_dirty_registers() */
706 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
708 struct arm *arm = target_to_arm(target);
709 struct arm_dpm *dpm = arm->dpm;
710 int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
712 if (dpm->bpwp_enable) {
713 for (unsigned i = 0; i < dpm->nwp; i++) {
714 if (!dpm->dwp[i].wp) {
715 retval = dpm_watchpoint_setup(dpm, i, wp);
724 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
726 struct arm *arm = target_to_arm(target);
727 struct arm_dpm *dpm = arm->dpm;
728 int retval = ERROR_INVALID_ARGUMENTS;
730 for (unsigned i = 0; i < dpm->nwp; i++) {
731 if (dpm->dwp[i].wp == wp) {
732 dpm->dwp[i].wp = NULL;
733 dpm->dwp[i].dirty = true;
735 /* hardware is updated in write_dirty_registers() */
744 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
746 switch (dpm->arm->core_state) {
750 case ARM_STATE_THUMB:
751 case ARM_STATE_THUMB_EE:
754 case ARM_STATE_JAZELLE:
761 /*----------------------------------------------------------------------*/
764 * Other debug and support utilities
767 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
769 struct target *target = dpm->arm->target;
773 /* Examine debug reason */
774 switch (DSCR_ENTRY(dscr)) {
775 case 6: /* Data abort (v6 only) */
776 case 7: /* Prefetch abort (v6 only) */
777 /* FALL THROUGH -- assume a v6 core in abort mode */
778 case 0: /* HALT request from debugger */
780 target->debug_reason = DBG_REASON_DBGRQ;
782 case 1: /* HW breakpoint */
783 case 3: /* SW BKPT */
784 case 5: /* vector catch */
785 target->debug_reason = DBG_REASON_BREAKPOINT;
787 case 2: /* asynch watchpoint */
788 case 10: /* precise watchpoint */
789 target->debug_reason = DBG_REASON_WATCHPOINT;
792 target->debug_reason = DBG_REASON_UNDEFINED;
797 /*----------------------------------------------------------------------*/
800 * Setup and management support.
804 * Hooks up this DPM to its associated target; call only once.
805 * Initially this only covers the register cache.
807 * Oh, and watchpoints. Yeah.
809 int arm_dpm_setup(struct arm_dpm *dpm)
811 struct arm *arm = dpm->arm;
812 struct target *target = arm->target;
813 struct reg_cache *cache;
817 /* register access setup */
818 arm->full_context = arm_dpm_full_context;
819 arm->read_core_reg = arm_dpm_read_core_reg;
820 arm->write_core_reg = arm_dpm_write_core_reg;
822 cache = armv4_5_build_reg_cache(target, arm);
826 *register_get_last_cache_p(&target->reg_cache) = cache;
828 /* coprocessor access setup */
832 /* breakpoint and watchpoint setup */
833 target->type->add_watchpoint = dpm_add_watchpoint;
834 target->type->remove_watchpoint = dpm_remove_watchpoint;
836 /* FIXME add breakpoint support */
837 /* FIXME add vector catch support */
839 dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
840 dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
842 dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
843 dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
845 if (!dpm->dbp || !dpm->dwp) {
851 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
852 target_name(target), dpm->nbp, dpm->nwp);
854 /* REVISIT ... and some of those breakpoints could match
855 * execution context IDs...
862 * Reinitializes DPM state at the beginning of a new debug session
863 * or after a reset which may have affected the debug module.
865 int arm_dpm_initialize(struct arm_dpm *dpm)
867 /* Disable all breakpoints and watchpoints at startup. */
868 if (dpm->bpwp_disable) {
871 for (i = 0; i < dpm->nbp; i++)
872 (void) dpm->bpwp_disable(dpm, i);
873 for (i = 0; i < dpm->nwp; i++)
874 (void) dpm->bpwp_disable(dpm, 16 + i);
876 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
877 target_name(dpm->arm->target));