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   1 /*
   2  * Copyright (C) 2009 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifdef HAVE_CONFIG_H
  19 #include "config.h"
  20 #endif
  21
  22 #include "arm.h"
  23 #include "arm_dpm.h"
  24 #include <jtag/jtag.h>
  25 #include "register.h"
  26 #include "breakpoints.h"
  27 #include "target_type.h"
  28 #include "arm_opcodes.h"
  29
  30
  31 /**
  32  * @file
  33  * Implements various ARM DPM operations using architectural debug registers.
  34  * These routines layer over core-specific communication methods to cope with
  35  * implementation differences between cores like ARM1136 and Cortex-A8.
  36  *
  37  * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
  38  * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
  39  * ARMv7-A and ARMv7-R edition (ARM DDI 0406B).  In OpenOCD, DPM operations
  40  * are abstracted through internal programming interfaces to share code and
  41  * to minimize needless differences in debug behavior between cores.
  42  */
  43
  44 /*----------------------------------------------------------------------*/
  45
  46 /*
  47  * Coprocessor support
  48  */
  49
  50 /* Read coprocessor */
  51 static int dpm_mrc(struct target *target, int cpnum,
  52         uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  53         uint32_t *value)
  54 {
  55         struct arm *arm = target_to_arm(target);
  56         struct arm_dpm *dpm = arm->dpm;
  57         int retval;
  58
  59         retval = dpm->prepare(dpm);
  60         if (retval != ERROR_OK)
  61                 return retval;
  62
  63         LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
  64                 (int) op1, (int) CRn,
  65                 (int) CRm, (int) op2);
  66
  67         /* read coprocessor register into R0; return via DCC */
  68         retval = dpm->instr_read_data_r0(dpm,
  69                         ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2),
  70                         value);
  71
  72         /* (void) */ dpm->finish(dpm);
  73         return retval;
  74 }
  75
  76 static int dpm_mcr(struct target *target, int cpnum,
  77         uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
  78         uint32_t value)
  79 {
  80         struct arm *arm = target_to_arm(target);
  81         struct arm_dpm *dpm = arm->dpm;
  82         int retval;
  83
  84         retval = dpm->prepare(dpm);
  85         if (retval != ERROR_OK)
  86                 return retval;
  87
  88         LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
  89                 (int) op1, (int) CRn,
  90                 (int) CRm, (int) op2);
  91
  92         /* read DCC into r0; then write coprocessor register from R0 */
  93         retval = dpm->instr_write_data_r0(dpm,
  94                         ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2),
  95                         value);
  96
  97         /* (void) */ dpm->finish(dpm);
  98         return retval;
  99 }
 100
 101 /*----------------------------------------------------------------------*/
 102
 103 /*
 104  * Register access utilities
 105  */
 106
 107 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
 108  * Routines *must* restore the original mode before returning!!
 109  */
 110 int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 111 {
 112         int retval;
 113         uint32_t cpsr;
 114
 115         /* restore previous mode */
 116         if (mode == ARM_MODE_ANY)
 117                 cpsr = buf_get_u32(dpm->arm->cpsr->value, 0, 32);
 118
 119         /* else force to the specified mode */
 120         else
 121                 cpsr = mode;
 122
 123         retval = dpm->instr_write_data_r0(dpm, ARMV4_5_MSR_GP(0, 0xf, 0), cpsr);
 124         if (retval != ERROR_OK)
 125                 return retval;
 126
 127         if (dpm->instr_cpsr_sync)
 128                 retval = dpm->instr_cpsr_sync(dpm);
 129
 130         return retval;
 131 }
 132
 133
 134 static int dpm_read_reg32(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 135 {
 136         uint32_t value;
 137         int retval = ERROR_FAIL;
 138
 139         switch (regnum) {
 140                 case 0 ... 14:
 141                         /* return via DCC:  "MCR p14, 0, Rnum, c0, c5, 0" */
 142                         retval = dpm->instr_read_data_dcc(dpm,
 143                                 ARMV4_5_MCR(14, 0, regnum, 0, 5, 0),
 144                                 &value);
 145                         break;
 146                 case 15:/* PC
 147                          * "MOV r0, pc"; then return via DCC */
 148                         retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value);
 149
 150                         /* NOTE: this seems like a slightly awkward place to update
 151                          * this value ... but if the PC gets written (the only way
 152                          * to change what we compute), the arch spec says subsequent
 153                          * reads return values which are "unpredictable".  So this
 154                          * is always right except in those broken-by-intent cases.
 155                          */
 156                         switch (dpm->arm->core_state) {
 157                                 case ARM_STATE_ARM:
 158                                         value -= 8;
 159                                         break;
 160                                 case ARM_STATE_THUMB:
 161                                 case ARM_STATE_THUMB_EE:
 162                                         value -= 4;
 163                                         break;
 164                                 case ARM_STATE_JAZELLE:
 165                                         /* core-specific ... ? */
 166                                         LOG_WARNING("Jazelle PC adjustment unknown");
 167                                         break;
 168                                 case ARM_STATE_AARCH64:
 169                                         LOG_ERROR("AARCH64: 32bit read requested");
 170                                         break;
 171                         }
 172                         break;
 173                 default:
 174                         /* 16: "MRS r0, CPSR"; then return via DCC
 175                          * 17: "MRS r0, SPSR"; then return via DCC
 176                          */
 177                         retval = dpm->instr_read_data_r0(dpm,
 178                                 ARMV4_5_MRS(0, regnum & 1),
 179                                 &value);
 180                         break;
 181         }
 182
 183         if (retval == ERROR_OK) {
 184                 buf_set_u32(r->value, 0, 32, value);
 185                 r->valid = true;
 186                 r->dirty = false;
 187                 LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
 188         }
 189
 190         return retval;
 191 }
 192
 193 static int dpm_read_reg64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 194 {
 195         uint64_t value;
 196         uint32_t i;
 197         int retval = ERROR_FAIL;
 198
 199         switch (regnum) {
 200                 case 0 ... 30:
 201                         i = 0xd5130400 + regnum; /* msr dbgdtr_el0,reg */
 202                         retval = dpm->instr_read_data_dcc_64(dpm, i, &value);
 203                         break;
 204                 case 31: /* SP */
 205                         i = 0x910003e0;
 206                         retval = dpm->instr_read_data_r0_64(dpm, i, &value);
 207                         break;
 208                 case 32: /* PC */
 209                         i = 0xd53b4520;
 210                         retval = dpm->instr_read_data_r0_64(dpm, i, &value);
 211                         break;
 212                 case 33: /* CPSR */
 213                         i = 0xd53b4500;
 214                         retval = dpm->instr_read_data_r0_64(dpm, i, &value);
 215                         break;
 216
 217                 default:
 218                         break;
 219         }
 220
 221         if (retval == ERROR_OK) {
 222                 buf_set_u64(r->value, 0, 64, value);
 223                 r->valid = true;
 224                 r->dirty = false;
 225                 LOG_DEBUG("READ: %s, %16.16llx", r->name, (long long)value);
 226         }
 227
 228         return retval;
 229 }
 230
 231
 232 /* just read the register -- rely on the core mode being right */
 233 static int dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 234 {
 235         if (r->size == 64)
 236                 return dpm_read_reg64(dpm, r, regnum);
 237         else
 238                 return dpm_read_reg32(dpm, r, regnum);
 239 }
 240
 241 static int dpm_write_reg32(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 242 {
 243         int retval = ERROR_FAIL;
 244         uint32_t value = buf_get_u32(r->value, 0, 32);
 245
 246         switch (regnum) {
 247                 case 0 ... 14:
 248                         /* load register from DCC:  "MRC p14, 0, Rnum, c0, c5, 0" */
 249                         retval = dpm->instr_write_data_dcc(dpm,
 250                                 ARMV4_5_MRC(14, 0, regnum, 0, 5, 0),
 251                                 value);
 252                         break;
 253                 case 15:/* PC
 254                          * read r0 from DCC; then "MOV pc, r0" */
 255                         retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value);
 256                         break;
 257                 default:
 258                         /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf"
 259                          * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf"
 260                          */
 261                         retval = dpm->instr_write_data_r0(dpm,
 262                                 ARMV4_5_MSR_GP(0, 0xf, regnum & 1),
 263                                 value);
 264                         if (retval != ERROR_OK)
 265                                 return retval;
 266
 267                         if (regnum == 16 && dpm->instr_cpsr_sync)
 268                                 retval = dpm->instr_cpsr_sync(dpm);
 269
 270                         break;
 271         }
 272
 273         if (retval == ERROR_OK) {
 274                 r->dirty = false;
 275                 LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
 276         }
 277
 278         return retval;
 279 }
 280
 281 /**
 282  * Write to program counter and switch the core state (arm/thumb) according to
 283  * the address.
 284  */
 285 static int dpm_write_pc_core_state(struct arm_dpm *dpm, struct reg *r)
 286 {
 287         uint32_t value = buf_get_u32(r->value, 0, 32);
 288
 289         /* read r0 from DCC; then "BX r0" */
 290         return dpm->instr_write_data_r0(dpm, ARMV4_5_BX(0), value);
 291 }
 292
 293 static int dpm_write_reg64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 294 {
 295         int retval = ERROR_FAIL;
 296         uint32_t i;
 297         uint64_t value = buf_get_u64(r->value, 0, 64);
 298
 299         switch (regnum) {
 300                 case 0 ... 30:
 301                         i = 0xd5330400 + regnum;
 302                         retval = dpm->instr_write_data_dcc(dpm, i, value);
 303                         break;
 304
 305                 default:
 306                         break;
 307         }
 308
 309         if (retval == ERROR_OK) {
 310                 r->dirty = false;
 311                 LOG_DEBUG("WRITE: %s, %16.16llx", r->name, (unsigned long long)value);
 312         }
 313
 314         return retval;
 315 }
 316
 317 /* just write the register -- rely on the core mode being right */
 318 static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 319 {
 320         if (r->size == 64)
 321                 return dpm_write_reg64(dpm, r, regnum);
 322         else
 323                 return dpm_write_reg32(dpm, r, regnum);
 324 }
 325
 326 static int arm_dpm_read_current_registers_i(struct arm_dpm *dpm)
 327 {
 328         struct arm *arm = dpm->arm;
 329         uint32_t cpsr, instr, core_regs;
 330         int retval;
 331         struct reg *r;
 332         enum arm_state core_state = arm->core_state;
 333
 334         retval = dpm->prepare(dpm);
 335         if (retval != ERROR_OK)
 336                 return retval;
 337
 338         /* read R0 first (it's used for scratch), then CPSR */
 339         r = arm->core_cache->reg_list + 0;
 340         if (!r->valid) {
 341                 retval = dpm_read_reg(dpm, r, 0);
 342                 if (retval != ERROR_OK)
 343                         goto fail;
 344         }
 345         r->dirty = true;
 346
 347         if (core_state == ARM_STATE_AARCH64)
 348                 instr = 0xd53b4500;  /* mrs x0, dspsr_el0 */
 349         else
 350                 instr = ARMV4_5_MRS(0, 0);
 351         retval = dpm->instr_read_data_r0(dpm, instr, &cpsr);
 352         if (retval != ERROR_OK)
 353                 goto fail;
 354
 355         /* update core mode and state, plus shadow mapping for R8..R14 */
 356         arm_set_cpsr(arm, cpsr);
 357
 358         core_regs = arm->core_cache->num_regs;
 359
 360         /* REVISIT we can probably avoid reading R1..R14, saving time... */
 361         for (unsigned i = 1; i < core_regs; i++) {
 362                 r = dpm->arm_reg_current(arm, i);
 363                 if (r->valid)
 364                         continue;
 365
 366                 retval = dpm_read_reg(dpm, r, i);
 367                 if (retval != ERROR_OK)
 368                         goto fail;
 369         }
 370
 371         /* NOTE: SPSR ignored (if it's even relevant). */
 372
 373         /* REVISIT the debugger can trigger various exceptions.  See the
 374          * ARMv7A architecture spec, section C5.7, for more info about
 375          * what defenses are needed; v6 debug has the most issues.
 376          */
 377
 378 fail:
 379         /* (void) */ dpm->finish(dpm);
 380         return retval;
 381 }
 382
 383 /**
 384  * Read basic registers of the the current context:  R0 to R15, and CPSR;
 385  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
 386  * In normal operation this is called on entry to halting debug state,
 387  * possibly after some other operations supporting restore of debug state
 388  * or making sure the CPU is fully idle (drain write buffer, etc).
 389  */
 390 int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 391 {
 392         return arm_dpm_read_current_registers_i(dpm);
 393 }
 394
 395 int arm_dpm_read_current_registers_64(struct arm_dpm *dpm)
 396 {
 397         return arm_dpm_read_current_registers_i(dpm);
 398 }
 399
 400 /* Avoid needless I/O ... leave breakpoints and watchpoints alone
 401  * unless they're removed, or need updating because of single-stepping
 402  * or running debugger code.
 403  */
 404 static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
 405         struct dpm_bpwp *xp, int *set_p)
 406 {
 407         int retval = ERROR_OK;
 408         bool disable;
 409
 410         if (!set_p) {
 411                 if (!xp->dirty)
 412                         goto done;
 413                 xp->dirty = false;
 414                 /* removed or startup; we must disable it */
 415                 disable = true;
 416         } else if (bpwp) {
 417                 if (!xp->dirty)
 418                         goto done;
 419                 /* disabled, but we must set it */
 420                 xp->dirty = disable = false;
 421                 *set_p = true;
 422         } else {
 423                 if (!*set_p)
 424                         goto done;
 425                 /* set, but we must temporarily disable it */
 426                 xp->dirty = disable = true;
 427                 *set_p = false;
 428         }
 429
 430         if (disable)
 431                 retval = dpm->bpwp_disable(dpm, xp->number);
 432         else
 433                 retval = dpm->bpwp_enable(dpm, xp->number,
 434                                 xp->address, xp->control);
 435
 436         if (retval != ERROR_OK)
 437                 LOG_ERROR("%s: can't %s HW %spoint %d",
 438                         disable ? "disable" : "enable",
 439                         target_name(dpm->arm->target),
 440                         (xp->number < 16) ? "break" : "watch",
 441                         xp->number & 0xf);
 442 done:
 443         return retval;
 444 }
 445
 446 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp);
 447
 448
 449 static int arm_dpm_write_dirty_registers_32(struct arm_dpm *dpm)
 450 {
 451         struct arm *arm = dpm->arm;
 452         struct reg_cache *cache = arm->core_cache;
 453         int retval;
 454         bool did_write;
 455
 456         /* Scan the registers until we find one that's both dirty and
 457          * eligible for flushing.  Flush that and everything else that
 458          * shares the same core mode setting.  Typically this won't
 459          * actually find anything to do...
 460          */
 461         do {
 462                 enum arm_mode mode = ARM_MODE_ANY;
 463
 464                 did_write = false;
 465
 466                 /* check everything except our scratch register R0 */
 467                 for (unsigned i = 1; i < cache->num_regs; i++) {
 468                         struct arm_reg *r;
 469                         unsigned regnum;
 470
 471                         /* also skip PC, CPSR, and non-dirty */
 472                         if (i == 15)
 473                                 continue;
 474                         if (arm->cpsr == cache->reg_list + i)
 475                                 continue;
 476                         if (!cache->reg_list[i].dirty)
 477                                 continue;
 478
 479                         r = cache->reg_list[i].arch_info;
 480                         regnum = r->num;
 481
 482                         /* may need to pick and set a mode */
 483                         if (!did_write) {
 484                                 enum arm_mode tmode;
 485
 486                                 did_write = true;
 487                                 mode = tmode = r->mode;
 488
 489                                 /* cope with special cases */
 490                                 switch (regnum) {
 491                                 case 8 ... 12:
 492                                         /* r8..r12 "anything but FIQ" case;
 493                                          * we "know" core mode is accurate
 494                                          * since we haven't changed it yet
 495                                          */
 496                                         if (arm->core_mode == ARM_MODE_FIQ
 497                                             && ARM_MODE_ANY
 498                                             != mode)
 499                                                 tmode = ARM_MODE_USR;
 500                                         break;
 501                                 case 16:
 502                                         /* SPSR */
 503                                         regnum++;
 504                                         break;
 505                                 }
 506
 507                                 /* REVISIT error checks */
 508                                 if (tmode != ARM_MODE_ANY) {
 509                                         retval = dpm_modeswitch(dpm, tmode);
 510                                         if (retval != ERROR_OK)
 511                                                 goto done;
 512                                 }
 513                         }
 514                         if (r->mode != mode)
 515                                 continue;
 516
 517                         retval = dpm_write_reg(dpm,
 518                                                &cache->reg_list[i],
 519                                                regnum);
 520                         if (retval != ERROR_OK)
 521                                 goto done;
 522                 }
 523
 524         } while (did_write);
 525
 526         /* Restore original CPSR ... assuming either that we changed it,
 527          * or it's dirty.  Must write PC to ensure the return address is
 528          * defined, and must not write it before CPSR.
 529          */
 530         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 531         if (retval != ERROR_OK)
 532                 goto done;
 533         arm->cpsr->dirty = false;
 534
 535         /* restore the PC, make sure to also switch the core state
 536          * to whatever it was set to with "arm core_state" command.
 537          * target code will have set PC to an appropriate resume address.
 538          */
 539         retval = dpm_write_pc_core_state(dpm, arm->pc);
 540         if (retval != ERROR_OK)
 541                 goto done;
 542         /* on Cortex-A5 (as found on NXP VF610 SoC), BX instruction
 543          * executed in debug state doesn't appear to set the PC,
 544          * explicitly set it with a "MOV pc, r0". This doesn't influence
 545          * CPSR on Cortex-A9 so it should be OK. Maybe due to different
 546          * debug version?
 547          */
 548         retval = dpm_write_reg(dpm, arm->pc, 15);
 549         if (retval != ERROR_OK)
 550                 goto done;
 551         arm->pc->dirty = false;
 552
 553         /* flush R0 -- it's *very* dirty by now */
 554         retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
 555         if (retval != ERROR_OK)
 556                 goto done;
 557         cache->reg_list[0].dirty = false;
 558
 559 done:
 560         return retval;
 561 }
 562
 563 static int arm_dpm_write_dirty_registers_64(struct arm_dpm *dpm)
 564 {
 565         struct arm *arm = dpm->arm;
 566         struct reg_cache *cache = arm->core_cache;
 567         int retval;
 568
 569         /* Scan the registers until we find one that's both dirty and
 570          * eligible for flushing.  Flush that and everything else that
 571          * shares the same core mode setting.  Typically this won't
 572          * actually find anything to do...
 573          */
 574
 575         /* check everything except our scratch register R0 */
 576         for (unsigned i = 1; i < 32; i++) {
 577                 struct arm_reg *r;
 578                 unsigned regnum;
 579
 580                 if (!cache->reg_list[i].dirty)
 581                         continue;
 582
 583                 r = cache->reg_list[i].arch_info;
 584                 regnum = r->num;
 585                 retval = dpm_write_reg(dpm,
 586                                        &cache->reg_list[i],
 587                                        regnum);
 588                 if (retval != ERROR_OK)
 589                         goto done;
 590         }
 591
 592         /* flush R0 -- it's *very* dirty by now */
 593         retval = dpm_write_reg(dpm, &cache->reg_list[0], 0);
 594         if (retval != ERROR_OK)
 595                 goto done;
 596         cache->reg_list[0].dirty = false;
 597
 598 done:
 599         return retval;
 600 }
 601
 602 /**
 603  * Writes all modified core registers for all processor modes.  In normal
 604  * operation this is called on exit from halting debug state.
 605  *
 606  * @param dpm: represents the processor
 607  * @param bpwp: true ensures breakpoints and watchpoints are set,
 608  *      false ensures they are cleared
 609  */
 610 int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 611 {
 612         struct arm *arm = dpm->arm;
 613         struct reg_cache *cache = arm->core_cache;
 614         int retval;
 615
 616         retval = dpm->prepare(dpm);
 617         if (retval != ERROR_OK)
 618                 goto done;
 619
 620         /* If we're managing hardware breakpoints for this core, enable
 621          * or disable them as requested.
 622          *
 623          * REVISIT We don't yet manage them for ANY cores.  Eventually
 624          * we should be able to assume we handle them; but until then,
 625          * cope with the hand-crafted breakpoint code.
 626          */
 627         if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
 628                 for (unsigned i = 0; i < dpm->nbp; i++) {
 629                         struct dpm_bp *dbp = dpm->dbp + i;
 630                         struct breakpoint *bp = dbp->bp;
 631
 632                         retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
 633                                         bp ? &bp->set : NULL);
 634                         if (retval != ERROR_OK)
 635                                 goto done;
 636                 }
 637         }
 638
 639         /* enable/disable watchpoints */
 640         for (unsigned i = 0; i < dpm->nwp; i++) {
 641                 struct dpm_wp *dwp = dpm->dwp + i;
 642                 struct watchpoint *wp = dwp->wp;
 643
 644                 retval = dpm_maybe_update_bpwp(dpm, bpwp, &dwp->bpwp,
 645                                 wp ? &wp->set : NULL);
 646                 if (retval != ERROR_OK)
 647                         goto done;
 648         }
 649
 650         /* NOTE:  writes to breakpoint and watchpoint registers might
 651          * be queued, and need (efficient/batched) flushing later.
 652          */
 653
 654         if (cache->reg_list[0].size == 64)
 655                 retval = arm_dpm_write_dirty_registers_64(dpm);
 656         else
 657                 retval = arm_dpm_write_dirty_registers_32(dpm);
 658
 659         /* (void) */ dpm->finish(dpm);
 660 done:
 661         return retval;
 662 }
 663
 664 /* Returns ARM_MODE_ANY or temporary mode to use while reading the
 665  * specified register ... works around flakiness from ARM core calls.
 666  * Caller already filtered out SPSR access; mode is never MODE_SYS
 667  * or MODE_ANY.
 668  */
 669 static enum arm_mode dpm_mapmode(struct arm *arm,
 670         unsigned num, enum arm_mode mode)
 671 {
 672         enum arm_mode amode = arm->core_mode;
 673
 674         /* don't switch if the mode is already correct */
 675         if (amode == ARM_MODE_SYS)
 676                 amode = ARM_MODE_USR;
 677         if (mode == amode)
 678                 return ARM_MODE_ANY;
 679
 680         switch (num) {
 681                 /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */
 682                 case 0 ... 7:
 683                 case 15:
 684                 case 16:
 685                         break;
 686                 /* r8..r12 aren't shadowed for anything except FIQ */
 687                 case 8 ... 12:
 688                         if (mode == ARM_MODE_FIQ)
 689                                 return mode;
 690                         break;
 691                 /* r13/sp, and r14/lr are always shadowed */
 692                 case 13:
 693                 case 14:
 694                         return mode;
 695                 default:
 696                         LOG_WARNING("invalid register #%u", num);
 697                         break;
 698         }
 699         return ARM_MODE_ANY;
 700 }
 701
 702
 703 /*
 704  * Standard ARM register accessors ... there are three methods
 705  * in "struct arm", to support individual read/write and bulk read
 706  * of registers.
 707  */
 708
 709 static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
 710         int regnum, enum arm_mode mode)
 711 {
 712         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 713         int retval;
 714
 715         if (regnum < 0 || regnum > 16)
 716                 return ERROR_COMMAND_SYNTAX_ERROR;
 717
 718         if (regnum == 16) {
 719                 if (mode != ARM_MODE_ANY)
 720                         regnum = 17;
 721         } else
 722                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 723
 724         /* REVISIT what happens if we try to read SPSR in a core mode
 725          * which has no such register?
 726          */
 727
 728         retval = dpm->prepare(dpm);
 729         if (retval != ERROR_OK)
 730                 return retval;
 731
 732         if (mode != ARM_MODE_ANY) {
 733                 retval = dpm_modeswitch(dpm, mode);
 734                 if (retval != ERROR_OK)
 735                         goto fail;
 736         }
 737
 738         retval = dpm_read_reg(dpm, r, regnum);
 739         if (retval != ERROR_OK)
 740                 goto fail;
 741         /* always clean up, regardless of error */
 742
 743         if (mode != ARM_MODE_ANY)
 744                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 745
 746 fail:
 747         /* (void) */ dpm->finish(dpm);
 748         return retval;
 749 }
 750
 751 static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
 752         int regnum, enum arm_mode mode, uint8_t *value)
 753 {
 754         struct arm_dpm *dpm = target_to_arm(target)->dpm;
 755         int retval;
 756
 757
 758         if (regnum < 0 || regnum > 16)
 759                 return ERROR_COMMAND_SYNTAX_ERROR;
 760
 761         if (regnum == 16) {
 762                 if (mode != ARM_MODE_ANY)
 763                         regnum = 17;
 764         } else
 765                 mode = dpm_mapmode(dpm->arm, regnum, mode);
 766
 767         /* REVISIT what happens if we try to write SPSR in a core mode
 768          * which has no such register?
 769          */
 770
 771         retval = dpm->prepare(dpm);
 772         if (retval != ERROR_OK)
 773                 return retval;
 774
 775         if (mode != ARM_MODE_ANY) {
 776                 retval = dpm_modeswitch(dpm, mode);
 777                 if (retval != ERROR_OK)
 778                         goto fail;
 779         }
 780
 781         retval = dpm_write_reg(dpm, r, regnum);
 782         /* always clean up, regardless of error */
 783
 784         if (mode != ARM_MODE_ANY)
 785                 /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
 786
 787 fail:
 788         /* (void) */ dpm->finish(dpm);
 789         return retval;
 790 }
 791
 792 static int arm_dpm_full_context(struct target *target)
 793 {
 794         struct arm *arm = target_to_arm(target);
 795         struct arm_dpm *dpm = arm->dpm;
 796         struct reg_cache *cache = arm->core_cache;
 797         int retval;
 798         bool did_read;
 799
 800         retval = dpm->prepare(dpm);
 801         if (retval != ERROR_OK)
 802                 goto done;
 803
 804         do {
 805                 enum arm_mode mode = ARM_MODE_ANY;
 806
 807                 did_read = false;
 808
 809                 /* We "know" arm_dpm_read_current_registers() was called so
 810                  * the unmapped registers (R0..R7, PC, AND CPSR) and some
 811                  * view of R8..R14 are current.  We also "know" oddities of
 812                  * register mapping: special cases for R8..R12 and SPSR.
 813                  *
 814                  * Pick some mode with unread registers and read them all.
 815                  * Repeat until done.
 816                  */
 817                 for (unsigned i = 0; i < cache->num_regs; i++) {
 818                         struct arm_reg *r;
 819
 820                         if (cache->reg_list[i].valid)
 821                                 continue;
 822                         r = cache->reg_list[i].arch_info;
 823
 824                         /* may need to pick a mode and set CPSR */
 825                         if (!did_read) {
 826                                 did_read = true;
 827                                 mode = r->mode;
 828
 829                                 /* For regular (ARM_MODE_ANY) R8..R12
 830                                  * in case we've entered debug state
 831                                  * in FIQ mode we need to patch mode.
 832                                  */
 833                                 if (mode != ARM_MODE_ANY)
 834                                         retval = dpm_modeswitch(dpm, mode);
 835                                 else
 836                                         retval = dpm_modeswitch(dpm, ARM_MODE_USR);
 837
 838                                 if (retval != ERROR_OK)
 839                                         goto done;
 840                         }
 841                         if (r->mode != mode)
 842                                 continue;
 843
 844                         /* CPSR was read, so "R16" must mean SPSR */
 845                         retval = dpm_read_reg(dpm,
 846                                         &cache->reg_list[i],
 847                                         (r->num == 16) ? 17 : r->num);
 848                         if (retval != ERROR_OK)
 849                                 goto done;
 850                 }
 851
 852         } while (did_read);
 853
 854         retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
 855         /* (void) */ dpm->finish(dpm);
 856 done:
 857         return retval;
 858 }
 859
 860
 861 /*----------------------------------------------------------------------*/
 862
 863 /*
 864  * Breakpoint and Watchpoint support.
 865  *
 866  * Hardware {break,watch}points are usually left active, to minimize
 867  * debug entry/exit costs.  When they are set or cleared, it's done in
 868  * batches.  Also, DPM-conformant hardware can update debug registers
 869  * regardless of whether the CPU is running or halted ... though that
 870  * fact isn't currently leveraged.
 871  */
 872
 873 static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 874         uint32_t addr, uint32_t length)
 875 {
 876         uint32_t control;
 877
 878         control = (1 << 0)      /* enable */
 879                 | (3 << 1);     /* both user and privileged access */
 880
 881         /* Match 1, 2, or all 4 byte addresses in this word.
 882          *
 883          * FIXME:  v7 hardware allows lengths up to 2 GB for BP and WP.
 884          * Support larger length, when addr is suitably aligned.  In
 885          * particular, allow watchpoints on 8 byte "double" values.
 886          *
 887          * REVISIT allow watchpoints on unaligned 2-bit values; and on
 888          * v7 hardware, unaligned 4-byte ones too.
 889          */
 890         switch (length) {
 891                 case 1:
 892                         control |= (1 << (addr & 3)) << 5;
 893                         break;
 894                 case 2:
 895                         /* require 2-byte alignment */
 896                         if (!(addr & 1)) {
 897                                 control |= (3 << (addr & 2)) << 5;
 898                                 break;
 899                         }
 900                 /* FALL THROUGH */
 901                 case 4:
 902                         /* require 4-byte alignment */
 903                         if (!(addr & 3)) {
 904                                 control |= 0xf << 5;
 905                                 break;
 906                         }
 907                 /* FALL THROUGH */
 908                 default:
 909                         LOG_ERROR("unsupported {break,watch}point length/alignment");
 910                         return ERROR_COMMAND_SYNTAX_ERROR;
 911         }
 912
 913         /* other shared control bits:
 914          * bits 15:14 == 0 ... both secure and nonsecure states (v6.1+ only)
 915          * bit 20 == 0 ... not linked to a context ID
 916          * bit 28:24 == 0 ... not ignoring N LSBs (v7 only)
 917          */
 918
 919         xp->address = addr & ~3;
 920         xp->control = control;
 921         xp->dirty = true;
 922
 923         LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
 924                 xp->address, control, xp->number);
 925
 926         /* hardware is updated in write_dirty_registers() */
 927         return ERROR_OK;
 928 }
 929
 930 static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
 931 {
 932         struct arm *arm = target_to_arm(target);
 933         struct arm_dpm *dpm = arm->dpm;
 934         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 935
 936         if (bp->length < 2)
 937                 return ERROR_COMMAND_SYNTAX_ERROR;
 938         if (!dpm->bpwp_enable)
 939                 return retval;
 940
 941         /* FIXME we need a generic solution for software breakpoints. */
 942         if (bp->type == BKPT_SOFT)
 943                 LOG_DEBUG("using HW bkpt, not SW...");
 944
 945         for (unsigned i = 0; i < dpm->nbp; i++) {
 946                 if (!dpm->dbp[i].bp) {
 947                         retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
 948                                         bp->address, bp->length);
 949                         if (retval == ERROR_OK)
 950                                 dpm->dbp[i].bp = bp;
 951                         break;
 952                 }
 953         }
 954
 955         return retval;
 956 }
 957
 958 static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
 959 {
 960         struct arm *arm = target_to_arm(target);
 961         struct arm_dpm *dpm = arm->dpm;
 962         int retval = ERROR_COMMAND_SYNTAX_ERROR;
 963
 964         for (unsigned i = 0; i < dpm->nbp; i++) {
 965                 if (dpm->dbp[i].bp == bp) {
 966                         dpm->dbp[i].bp = NULL;
 967                         dpm->dbp[i].bpwp.dirty = true;
 968
 969                         /* hardware is updated in write_dirty_registers() */
 970                         retval = ERROR_OK;
 971                         break;
 972                 }
 973         }
 974
 975         return retval;
 976 }
 977
 978 static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
 979         struct watchpoint *wp)
 980 {
 981         int retval;
 982         struct dpm_wp *dwp = dpm->dwp + index_t;
 983         uint32_t control;
 984
 985         /* this hardware doesn't support data value matching or masking */
 986         if (wp->value || wp->mask != ~(uint32_t)0) {
 987                 LOG_DEBUG("watchpoint values and masking not supported");
 988                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 989         }
 990
 991         retval = dpm_bpwp_setup(dpm, &dwp->bpwp, wp->address, wp->length);
 992         if (retval != ERROR_OK)
 993                 return retval;
 994
 995         control = dwp->bpwp.control;
 996         switch (wp->rw) {
 997                 case WPT_READ:
 998                         control |= 1 << 3;
 999                         break;
1000                 case WPT_WRITE:
1001                         control |= 2 << 3;
1002                         break;
1003                 case WPT_ACCESS:
1004                         control |= 3 << 3;
1005                         break;
1006         }
1007         dwp->bpwp.control = control;
1008
1009         dpm->dwp[index_t].wp = wp;
1010
1011         return retval;
1012 }
1013
1014 static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
1015 {
1016         struct arm *arm = target_to_arm(target);
1017         struct arm_dpm *dpm = arm->dpm;
1018         int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1019
1020         if (dpm->bpwp_enable) {
1021                 for (unsigned i = 0; i < dpm->nwp; i++) {
1022                         if (!dpm->dwp[i].wp) {
1023                                 retval = dpm_watchpoint_setup(dpm, i, wp);
1024                                 break;
1025                         }
1026                 }
1027         }
1028
1029         return retval;
1030 }
1031
1032 static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
1033 {
1034         struct arm *arm = target_to_arm(target);
1035         struct arm_dpm *dpm = arm->dpm;
1036         int retval = ERROR_COMMAND_SYNTAX_ERROR;
1037
1038         for (unsigned i = 0; i < dpm->nwp; i++) {
1039                 if (dpm->dwp[i].wp == wp) {
1040                         dpm->dwp[i].wp = NULL;
1041                         dpm->dwp[i].bpwp.dirty = true;
1042
1043                         /* hardware is updated in write_dirty_registers() */
1044                         retval = ERROR_OK;
1045                         break;
1046                 }
1047         }
1048
1049         return retval;
1050 }
1051
1052 void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
1053 {
1054         switch (dpm->arm->core_state) {
1055                 case ARM_STATE_ARM:
1056                         addr -= 8;
1057                         break;
1058                 case ARM_STATE_THUMB:
1059                 case ARM_STATE_THUMB_EE:
1060                         addr -= 4;
1061                         break;
1062                 case ARM_STATE_JAZELLE:
1063                 case ARM_STATE_AARCH64:
1064                         /* ?? */
1065                         break;
1066         }
1067         dpm->wp_pc = addr;
1068 }
1069
1070 /*----------------------------------------------------------------------*/
1071
1072 /*
1073  * Other debug and support utilities
1074  */
1075
1076 void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
1077 {
1078         struct target *target = dpm->arm->target;
1079
1080         dpm->dscr = dscr;
1081
1082         /* Examine debug reason */
1083         switch (DSCR_ENTRY(dscr)) {
1084                 case 6: /* Data abort (v6 only) */
1085                 case 7: /* Prefetch abort (v6 only) */
1086                 /* FALL THROUGH -- assume a v6 core in abort mode */
1087                 case 0: /* HALT request from debugger */
1088                 case 4: /* EDBGRQ */
1089                         target->debug_reason = DBG_REASON_DBGRQ;
1090                         break;
1091                 case 1: /* HW breakpoint */
1092                 case 3: /* SW BKPT */
1093                 case 5: /* vector catch */
1094                         target->debug_reason = DBG_REASON_BREAKPOINT;
1095                         break;
1096                 case 2: /* asynch watchpoint */
1097                 case 10:/* precise watchpoint */
1098                         target->debug_reason = DBG_REASON_WATCHPOINT;
1099                         break;
1100                 default:
1101                         target->debug_reason = DBG_REASON_UNDEFINED;
1102                         break;
1103         }
1104 }
1105
1106 /*----------------------------------------------------------------------*/
1107
1108 /*
1109  * Setup and management support.
1110  */
1111
1112 /**
1113  * Hooks up this DPM to its associated target; call only once.
1114  * Initially this only covers the register cache.
1115  *
1116  * Oh, and watchpoints.  Yeah.
1117  */
1118 int arm_dpm_setup(struct arm_dpm *dpm)
1119 {
1120         struct arm *arm = dpm->arm;
1121         struct target *target = arm->target;
1122         struct reg_cache *cache;
1123
1124         arm->dpm = dpm;
1125
1126         /* register access setup */
1127         arm->full_context = arm_dpm_full_context;
1128         arm->read_core_reg = arm->read_core_reg ? : arm_dpm_read_core_reg;
1129         arm->write_core_reg = arm->write_core_reg ? : arm_dpm_write_core_reg;
1130
1131         /* avoid duplicating the register cache */
1132         if (arm->core_cache == NULL) {
1133                 cache = arm_build_reg_cache(target, arm);
1134                 if (!cache)
1135                         return ERROR_FAIL;
1136
1137                 *register_get_last_cache_p(&target->reg_cache) = cache;
1138         }
1139
1140         /* coprocessor access setup */
1141         arm->mrc = dpm_mrc;
1142         arm->mcr = dpm_mcr;
1143
1144         /* breakpoint setup -- optional until it works everywhere */
1145         if (!target->type->add_breakpoint) {
1146                 target->type->add_breakpoint = dpm_add_breakpoint;
1147                 target->type->remove_breakpoint = dpm_remove_breakpoint;
1148         }
1149
1150         /* watchpoint setup */
1151         target->type->add_watchpoint = dpm_add_watchpoint;
1152         target->type->remove_watchpoint = dpm_remove_watchpoint;
1153
1154
1155         if (dpm->arm_reg_current == 0)
1156                 dpm->arm_reg_current = arm_reg_current;
1157
1158         /* FIXME add vector catch support */
1159
1160         if (arm->core_state == ARM_STATE_AARCH64) {
1161                 dpm->nbp = 1 + ((dpm->didr >> 24) & 0xf);
1162                 dpm->nwp = 1 + ((dpm->didr >> 28) & 0xf);
1163         } else {
1164                 dpm->nbp = 1 + ((dpm->didr >> 12) & 0xf);
1165                 dpm->nwp = 1 + ((dpm->didr >> 20) & 0xf);
1166         }
1167
1168         dpm->dbp = calloc(dpm->nbp, sizeof *dpm->dbp);
1169         dpm->dwp = calloc(dpm->nwp, sizeof *dpm->dwp);
1170
1171         if (!dpm->dbp || !dpm->dwp) {
1172                 free(dpm->dbp);
1173                 free(dpm->dwp);
1174                 return ERROR_FAIL;
1175         }
1176
1177         LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
1178                 target_name(target), dpm->nbp, dpm->nwp);
1179
1180         /* REVISIT ... and some of those breakpoints could match
1181          * execution context IDs...
1182          */
1183
1184         return ERROR_OK;
1185 }
1186
1187 /**
1188  * Reinitializes DPM state at the beginning of a new debug session
1189  * or after a reset which may have affected the debug module.
1190  */
1191 int arm_dpm_initialize(struct arm_dpm *dpm)
1192 {
1193         /* Disable all breakpoints and watchpoints at startup. */
1194         if (dpm->bpwp_disable) {
1195                 unsigned i;
1196
1197                 for (i = 0; i < dpm->nbp; i++) {
1198                         dpm->dbp[i].bpwp.number = i;
1199                         (void) dpm->bpwp_disable(dpm, i);
1200                 }
1201                 for (i = 0; i < dpm->nwp; i++) {
1202                         dpm->dwp[i].bpwp.number = 16 + i;
1203                         (void) dpm->bpwp_disable(dpm, 16 + i);
1204                 }
1205         } else
1206                 LOG_WARNING("%s: can't disable breakpoints and watchpoints",
1207                         target_name(dpm->arm->target));
1208
1209         return ERROR_OK;
1210 }