1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 #ifndef ARM_DISASSEMBLER_H
22 #define ARM_DISASSEMBLER_H
24 #include <helper/types.h>
26 enum arm_instruction_type {
27 ARM_UNKNOWN_INSTUCTION,
29 /* Branch instructions */
35 /* Data processing instructions */
53 /* Load/store instructions */
74 /* Status register access instructions */
78 /* Multiply instructions */
86 /* Miscellaneous instructions */
89 /* Exception generating instructions */
93 /* Coprocessor instructions */
100 /* Semaphore instructions */
104 /* Enhanced DSP extensions */
120 ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
123 struct arm_b_bl_bx_blx_instr {
125 uint32_t target_address;
128 union arm_shifter_operand {
134 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
144 struct arm_data_proc_instr {
145 int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
149 union arm_shifter_operand shifter_operand;
152 struct arm_load_store_instr {
156 int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
157 int offset_mode; /* 0: immediate, 1: (scaled) register */
162 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
168 struct arm_load_store_multiple_instr {
170 uint32_t register_list;
171 uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
176 struct arm_instruction {
177 enum arm_instruction_type type;
181 /* return value ... Thumb-2 sizes vary */
182 unsigned instruction_size;
185 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
186 struct arm_data_proc_instr data_proc;
187 struct arm_load_store_instr load_store;
188 struct arm_load_store_multiple_instr load_store_multiple;
193 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
194 struct arm_instruction *instruction);
195 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
196 struct arm_instruction *instruction);
197 int thumb2_opcode(struct target *target, uint32_t address,
198 struct arm_instruction *instruction);
199 int arm_access_size(struct arm_instruction *instruction);
201 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
203 #endif /* ARM_DISASSEMBLER_H */