1 /***************************************************************************
2 * Copyright (C) 2006 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
21 #ifndef ARM_DISASSEMBLER_H
22 #define ARM_DISASSEMBLER_H
24 enum arm_instruction_type {
25 ARM_UNKNOWN_INSTUCTION,
27 /* Branch instructions */
33 /* Data processing instructions */
51 /* Load/store instructions */
72 /* Status register access instructions */
76 /* Multiply instructions */
84 /* Miscellaneous instructions */
87 /* Exception return instructions */
90 /* Exception generating instructions */
96 /* Coprocessor instructions */
103 /* Semaphore instructions */
107 /* Enhanced DSP extensions */
123 ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
126 struct arm_b_bl_bx_blx_instr {
128 uint32_t target_address;
131 union arm_shifter_operand {
137 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
147 struct arm_data_proc_instr {
148 int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
152 union arm_shifter_operand shifter_operand;
155 struct arm_load_store_instr {
159 int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
160 int offset_mode; /* 0: immediate, 1: (scaled) register */
165 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
171 struct arm_load_store_multiple_instr {
173 uint32_t register_list;
174 uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
179 struct arm_instruction {
180 enum arm_instruction_type type;
184 /* return value ... Thumb-2 sizes vary */
185 unsigned instruction_size;
188 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
189 struct arm_data_proc_instr data_proc;
190 struct arm_load_store_instr load_store;
191 struct arm_load_store_multiple_instr load_store_multiple;
196 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
197 struct arm_instruction *instruction);
198 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
199 struct arm_instruction *instruction);
200 int thumb2_opcode(struct target *target, uint32_t address,
201 struct arm_instruction *instruction);
202 int arm_access_size(struct arm_instruction *instruction);
204 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
206 #endif /* ARM_DISASSEMBLER_H */