1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2006 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_ARM_DISASSEMBLER_H
9 #define OPENOCD_TARGET_ARM_DISASSEMBLER_H
11 enum arm_instruction_type {
12 ARM_UNKNOWN_INSTRUCTION,
14 /* Branch instructions */
20 /* Data processing instructions */
38 /* Load/store instructions */
59 /* Status register access instructions */
63 /* Multiply instructions */
71 /* Miscellaneous instructions */
74 /* Exception return instructions */
77 /* Exception generating instructions */
83 /* Coprocessor instructions */
90 /* Semaphore instructions */
94 /* Enhanced DSP extensions */
112 ARM_UNDEFINED_INSTRUCTION = 0xffffffff,
115 struct arm_b_bl_bx_blx_instr {
117 uint32_t target_address;
120 union arm_shifter_operand {
126 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
136 struct arm_data_proc_instr {
137 int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
141 union arm_shifter_operand shifter_operand;
144 struct arm_load_store_instr {
148 int index_mode; /* 0: offset, 1: pre-indexed, 2: post-indexed */
149 int offset_mode; /* 0: immediate, 1: (scaled) register */
154 uint8_t shift; /* 0: LSL, 1: LSR, 2: ASR, 3: ROR, 4: RRX */
160 struct arm_load_store_multiple_instr {
162 uint32_t register_list;
163 uint8_t addressing_mode; /* 0: IA, 1: IB, 2: DA, 3: DB */
168 struct arm_instruction {
169 enum arm_instruction_type type;
173 /* return value ... Thumb-2 sizes vary */
174 unsigned instruction_size;
177 struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
178 struct arm_data_proc_instr data_proc;
179 struct arm_load_store_instr load_store;
180 struct arm_load_store_multiple_instr load_store_multiple;
185 int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
186 struct arm_instruction *instruction);
187 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
188 struct arm_instruction *instruction);
189 int arm_access_size(struct arm_instruction *instruction);
191 int arm_disassemble(struct command_invocation *cmd, struct target *target,
192 target_addr_t address, size_t count, bool thumb_mode);
195 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
197 #endif /* OPENOCD_TARGET_ARM_DISASSEMBLER_H */