1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * ARM CoreSight Architecture Specification v3.0 IHI0029E
8 #ifndef OPENOCD_TARGET_ARM_CORESIGHT_H
9 #define OPENOCD_TARGET_ARM_CORESIGHT_H
14 #include <helper/bits.h>
16 #define ARM_CS_ALIGN (0x1000)
18 /* mandatory registers */
19 #define ARM_CS_PIDR0 (0xFE0)
20 #define ARM_CS_PIDR1 (0xFE4)
21 #define ARM_CS_PIDR2 (0xFE8)
22 #define ARM_CS_PIDR3 (0xFEC)
23 #define ARM_CS_PIDR4 (0xFD0)
24 #define ARM_CS_PIDR5 (0xFD4)
25 #define ARM_CS_PIDR6 (0xFD8)
26 #define ARM_CS_PIDR7 (0xFDC)
29 * When PIDR bit JEDEC is zero, only the lowers 7 bits of DESIGNER are valid
30 * and represent a legacy ASCII Identity Code.
32 #define ARM_CS_PIDR_PART(pidr) ((pidr) & 0x0FFF)
33 #define ARM_CS_PIDR_DESIGNER(pidr) \
35 typeof(pidr) _x = (pidr); \
36 ((_x >> 25) & 0x780) | ((_x >> 12) & 0x7F); \
38 #define ARM_CS_PIDR_JEDEC BIT(19)
39 #define ARM_CS_PIDR_SIZE(pidr) (((pidr) >> 36) & 0x000F)
41 #define ARM_CS_CIDR0 (0xFF0)
42 #define ARM_CS_CIDR1 (0xFF4)
43 #define ARM_CS_CIDR2 (0xFF8)
44 #define ARM_CS_CIDR3 (0xFFC)
46 #define ARM_CS_CIDR_CLASS_MASK (0x0000F000)
47 #define ARM_CS_CIDR_CLASS(cidr) (((cidr) >> 12) & 0x000F)
48 #define ARM_CS_CLASS_0X1_ROM_TABLE (0x1)
49 #define ARM_CS_CLASS_0X9_CS_COMPONENT (0x9)
51 #define ARM_CS_CIDR1_CLASS_MASK (0x000000F0)
52 #define ARM_CS_CIDR1_CLASS_SHIFT (4)
54 static inline bool is_valid_arm_cs_cidr(uint32_t cidr)
56 return (cidr & ~ARM_CS_CIDR_CLASS_MASK) == 0xB105000D;
59 /* Class 0x9 only registers */
60 #define ARM_CS_C9_DEVARCH (0xFBC)
62 #define ARM_CS_C9_DEVARCH_ARCHID_MASK (0x0000FFFF)
63 #define ARM_CS_C9_DEVARCH_ARCHID_SHIFT (0)
64 #define ARM_CS_C9_DEVARCH_REVISION_MASK (0x000F0000)
65 #define ARM_CS_C9_DEVARCH_REVISION_SHIFT (16)
66 #define ARM_CS_C9_DEVARCH_PRESENT BIT(20)
67 #define ARM_CS_C9_DEVARCH_ARCHITECT_MASK (0xFFE00000)
68 #define ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT (21)
69 #define ARM_CS_C9_DEVARCH_REVISION(devarch) \
70 (((devarch) & ARM_CS_C9_DEVARCH_REVISION_MASK) >> ARM_CS_C9_DEVARCH_REVISION_SHIFT)
71 #define ARM_CS_C9_DEVARCH_ARCHITECT(devarch) \
72 (((devarch) & ARM_CS_C9_DEVARCH_ARCHITECT_MASK) >> ARM_CS_C9_DEVARCH_ARCHITECT_SHIFT)
74 #define ARM_CS_C9_DEVID (0xFC8)
76 #define ARM_CS_C9_DEVID_FORMAT_MASK (0x0000000F)
77 #define ARM_CS_C9_DEVID_FORMAT_32BIT (0)
78 #define ARM_CS_C9_DEVID_FORMAT_64BIT (1)
79 #define ARM_CS_C9_DEVID_SYSMEM_MASK BIT(4)
80 #define ARM_CS_C9_DEVID_PRR_MASK BIT(5)
81 #define ARM_CS_C9_DEVID_CP_MASK BIT(5)
83 #define ARM_CS_C9_DEVTYPE (0xFCC)
85 #define ARM_CS_C9_DEVTYPE_MAJOR_MASK (0x0000000F)
86 #define ARM_CS_C9_DEVTYPE_MAJOR_SHIFT (0)
87 #define ARM_CS_C9_DEVTYPE_SUB_MASK (0x000000F0)
88 #define ARM_CS_C9_DEVTYPE_SUB_SHIFT (4)
90 #define ARM_CS_C9_DEVTYPE_MASK (0x000000FF)
91 #define ARM_CS_C9_DEVTYPE_CORE_DEBUG (0x00000015)
93 /* Class 0x1 only registers */
94 #define ARM_CS_C1_MEMTYPE ARM_CS_C9_DEVTYPE
96 #define ARM_CS_C1_MEMTYPE_SYSMEM_MASK BIT(0)
98 /* The coding of ROM entry present differs between Class 0x9 and Class 0x1,
99 * but we can simplify the whole management */
100 #define ARM_CS_ROMENTRY_PRESENT BIT(0)
101 #define ARM_CS_ROMENTRY_OFFSET_MASK (0xFFFFF000U)
103 #endif /* OPENOCD_TARGET_ARM_CORESIGHT_H */