1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
35 /* three-bit ACK values for SWD access (sent LSB first) */
36 #define SWD_ACK_OK 0x1
37 #define SWD_ACK_WAIT 0x2
38 #define SWD_ACK_FAULT 0x4
43 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
45 /* A[3:0] for DP registers; A[1:0] are always zero.
46 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
47 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
48 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
50 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
51 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
52 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
53 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
54 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
55 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
56 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
57 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
58 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
59 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
60 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
62 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
64 /* Fields of the DP's AP ABORT register */
65 #define DAPABORT (1UL << 0)
66 #define STKCMPCLR (1UL << 1) /* SWD-only */
67 #define STKERRCLR (1UL << 2) /* SWD-only */
68 #define WDERRCLR (1UL << 3) /* SWD-only */
69 #define ORUNERRCLR (1UL << 4) /* SWD-only */
71 /* Fields of the DP's CTRL/STAT register */
72 #define CORUNDETECT (1UL << 0)
73 #define SSTICKYORUN (1UL << 1)
74 /* 3:2 - transaction mode (e.g. pushed compare) */
75 #define SSTICKYCMP (1UL << 4)
76 #define SSTICKYERR (1UL << 5)
77 #define READOK (1UL << 6) /* SWD-only */
78 #define WDATAERR (1UL << 7) /* SWD-only */
79 /* 11:8 - mask lanes for pushed compare or verify ops */
80 /* 21:12 - transaction counter */
81 #define CDBGRSTREQ (1UL << 26)
82 #define CDBGRSTACK (1UL << 27)
83 #define CDBGPWRUPREQ (1UL << 28)
84 #define CDBGPWRUPACK (1UL << 29)
85 #define CSYSPWRUPREQ (1UL << 30)
86 #define CSYSPWRUPACK (1UL << 31)
88 #define DP_SELECT_APSEL 0xFF000000
89 #define DP_SELECT_APBANK 0x000000F0
90 #define DP_SELECT_DPBANK 0x0000000F
91 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
93 #define DP_APSEL_MAX (255)
94 #define DP_APSEL_INVALID (-1)
97 /* MEM-AP register addresses */
98 #define MEM_AP_REG_CSW 0x00
99 #define MEM_AP_REG_TAR 0x04
100 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
101 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
102 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
103 #define MEM_AP_REG_BD1 0x14
104 #define MEM_AP_REG_BD2 0x18
105 #define MEM_AP_REG_BD3 0x1C
106 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
107 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
108 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
109 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
110 /* Generic AP register address */
111 #define AP_REG_IDR 0xFC /* RO: Identification Register */
113 /* Fields of the MEM-AP's CSW register */
114 #define CSW_SIZE_MASK 7
118 #define CSW_ADDRINC_MASK (3UL << 4)
119 #define CSW_ADDRINC_OFF 0UL
120 #define CSW_ADDRINC_SINGLE (1UL << 4)
121 #define CSW_ADDRINC_PACKED (2UL << 4)
122 #define CSW_DEVICE_EN (1UL << 6)
123 #define CSW_TRIN_PROG (1UL << 7)
125 /* All fields in bits 12 and above are implementation-defined
126 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
127 * Some bits are shared between buses
129 #define CSW_SPIDEN (1UL << 23)
130 #define CSW_DBGSWENABLE (1UL << 31)
132 /* AHB: Privileged */
133 #define CSW_AHB_HPROT1 (1UL << 25)
134 /* AHB: set HMASTER signals to AHB-AP ID */
135 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
136 /* AHB5: non-secure access via HNONSEC
137 * AHB3: SBO, UNPREDICTABLE if zero */
138 #define CSW_AHB_SPROT (1UL << 30)
139 /* AHB: initial value of csw_default */
140 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
142 /* AXI: Privileged */
143 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
144 /* AXI: Non-secure */
145 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
146 /* AXI: initial value of csw_default */
147 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
149 /* APB: initial value of csw_default */
150 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
153 /* Fields of the MEM-AP's IDR register */
154 #define IDR_REV (0xFUL << 28)
155 #define IDR_JEP106 (0x7FFUL << 17)
156 #define IDR_CLASS (0xFUL << 13)
157 #define IDR_VARIANT (0xFUL << 4)
158 #define IDR_TYPE (0xFUL << 0)
160 #define IDR_JEP106_ARM 0x04760000
162 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
163 enum swd_special_seq {
173 * This represents an ARM Debug Interface (v5) Access Port (AP).
174 * Most common is a MEM-AP, for memory access.
178 * DAP this AP belongs to.
180 struct adiv5_dap *dap;
188 * Default value for (MEM-AP) AP_REG_CSW register.
190 uint32_t csw_default;
193 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
194 * configure an access mode, such as autoincrementing AP_REG_TAR during
195 * word access. "-1" indicates no cached value.
200 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
201 * configure the address being read or written
202 * "-1" indicates no cached value.
207 * Configures how many extra tck clocks are added after starting a
208 * MEM-AP access before we try to read its status (and/or result).
210 uint32_t memaccess_tck;
212 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
213 uint32_t tar_autoincr_block;
215 /* true if packed transfers are supported by the MEM-AP */
216 bool packed_transfers;
218 /* true if unaligned memory access is not supported by the MEM-AP */
219 bool unaligned_access_bad;
221 /* true if tar_value is in sync with TAR register */
227 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
228 * A DAP has two types of component: one Debug Port (DP), which is a
229 * transport agent; and at least one Access Port (AP), controlling
232 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
233 * Accordingly, this interface is responsible for hiding the transport
234 * differences so upper layer code can largely ignore them.
236 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
237 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
238 * a choice made at board design time (by only using the SWD pins), or
239 * as part of setting up a debug session (if all the dual-role JTAG/SWD
240 * signals are available).
243 const struct dap_ops *ops;
245 /* dap transaction list for WAIT support */
246 struct list_head cmd_journal;
248 /* pool for dap_cmd objects */
249 struct list_head cmd_pool;
251 /* number of dap_cmd objects in the pool */
252 size_t cmd_pool_size;
254 struct jtag_tap *tap;
256 uint32_t dp_ctrl_stat;
258 struct adiv5_ap ap[DP_APSEL_MAX + 1];
260 /* The current manually selected AP by the "dap apsel" command */
264 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
265 * indicates no cached value and forces rewrite of the register.
269 /* information about current pending SWjDP-AHBAP transaction */
273 * Holds the pointer to the destination word for the last queued read,
274 * for use with posted AP read sequence optimization.
278 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
279 * despite lack of support in the ARMv7 architecture. Memory access through
280 * the AHB-AP has strange byte ordering these processors, and we need to
281 * swizzle appropriately. */
282 bool ti_be_32_quirks;
285 * STLINK adapter need to know if last AP operation was read or write, and
286 * in case of write has to flush it with a dummy read from DP_RDBUFF
288 bool stlink_flush_ap_write;
291 * Signals that an attempt to reestablish communication afresh
292 * should be performed before the next access.
296 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
297 * do not set this bit until later in the bringup sequence */
298 bool ignore_syspwrupack;
302 * Transport-neutral representation of queued DAP transactions, supporting
303 * both JTAG and SWD transports. All submitted transactions are logically
304 * queued, until the queue is executed by run(). Some implementations might
305 * execute transactions as soon as they're submitted, but no status is made
306 * available until run().
309 /** connect operation for SWD */
310 int (*connect)(struct adiv5_dap *dap);
312 /** send a sequence to the DAP */
313 int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
315 /** DP register read. */
316 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
318 /** DP register write. */
319 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
322 /** AP register read. */
323 int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
325 /** AP register write. */
326 int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
329 /** AP operation abort. */
330 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
332 /** Executes all queued DAP operations. */
333 int (*run)(struct adiv5_dap *dap);
335 /** Executes all queued DAP operations but doesn't check
336 * sticky error conditions */
337 int (*sync)(struct adiv5_dap *dap);
339 /** Optional; called at OpenOCD exit */
340 void (*quit)(struct adiv5_dap *dap);
344 * Access Port classes
347 AP_CLASS_NONE = 0x00000, /* No class defined */
348 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
355 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
356 AP_TYPE_AHB3_AP = 0x1, /* AHB3 Memory-AP */
357 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
358 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
359 AP_TYPE_AHB5_AP = 0x5, /* AHB5 Memory-AP. */
363 * Send an adi-v5 sequence to the DAP.
365 * @param dap The DAP used for reading.
366 * @param seq The sequence to send.
368 * @return ERROR_OK for success, else a fault code.
370 static inline int dap_send_sequence(struct adiv5_dap *dap,
371 enum swd_special_seq seq)
373 assert(dap->ops != NULL);
374 return dap->ops->send_sequence(dap, seq);
378 * Queue a DP register read.
379 * Note that not all DP registers are readable; also, that JTAG and SWD
380 * have slight differences in DP register support.
382 * @param dap The DAP used for reading.
383 * @param reg The two-bit number of the DP register being read.
384 * @param data Pointer saying where to store the register's value
385 * (in host endianness).
387 * @return ERROR_OK for success, else a fault code.
389 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
390 unsigned reg, uint32_t *data)
392 assert(dap->ops != NULL);
393 return dap->ops->queue_dp_read(dap, reg, data);
397 * Queue a DP register write.
398 * Note that not all DP registers are writable; also, that JTAG and SWD
399 * have slight differences in DP register support.
401 * @param dap The DAP used for writing.
402 * @param reg The two-bit number of the DP register being written.
403 * @param data Value being written (host endianness)
405 * @return ERROR_OK for success, else a fault code.
407 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
408 unsigned reg, uint32_t data)
410 assert(dap->ops != NULL);
411 return dap->ops->queue_dp_write(dap, reg, data);
415 * Queue an AP register read.
417 * @param ap The AP used for reading.
418 * @param reg The number of the AP register being read.
419 * @param data Pointer saying where to store the register's value
420 * (in host endianness).
422 * @return ERROR_OK for success, else a fault code.
424 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
425 unsigned reg, uint32_t *data)
427 assert(ap->dap->ops != NULL);
428 return ap->dap->ops->queue_ap_read(ap, reg, data);
432 * Queue an AP register write.
434 * @param ap The AP used for writing.
435 * @param reg The number of the AP register being written.
436 * @param data Value being written (host endianness)
438 * @return ERROR_OK for success, else a fault code.
440 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
441 unsigned reg, uint32_t data)
443 assert(ap->dap->ops != NULL);
444 return ap->dap->ops->queue_ap_write(ap, reg, data);
448 * Queue an AP abort operation. The current AP transaction is aborted,
449 * including any update of the transaction counter. The AP is left in
450 * an unknown state (so it must be re-initialized). For use only after
451 * the AP has reported WAIT status for an extended period.
453 * @param dap The DAP used for writing.
454 * @param ack Pointer to where transaction status will be stored.
456 * @return ERROR_OK for success, else a fault code.
458 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
460 assert(dap->ops != NULL);
461 return dap->ops->queue_ap_abort(dap, ack);
465 * Perform all queued DAP operations, and clear any errors posted in the
466 * CTRL_STAT register when they are done. Note that if more than one AP
467 * operation will be queued, one of the first operations in the queue
468 * should probably enable CORUNDETECT in the CTRL/STAT register.
470 * @param dap The DAP used.
472 * @return ERROR_OK for success, else a fault code.
474 static inline int dap_run(struct adiv5_dap *dap)
476 assert(dap->ops != NULL);
477 return dap->ops->run(dap);
480 static inline int dap_sync(struct adiv5_dap *dap)
482 assert(dap->ops != NULL);
484 return dap->ops->sync(dap);
488 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
493 retval = dap_queue_dp_read(dap, reg, value);
494 if (retval != ERROR_OK)
500 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
501 uint32_t mask, uint32_t value, int timeout)
504 assert((value & mask) == value);
508 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
511 ret = dap_dp_read_atomic(dap, reg, ®val);
515 if ((regval & mask) == value)
522 LOG_DEBUG("DAP: poll %x timeout", reg);
529 /* Queued MEM-AP memory mapped single word transfers. */
530 int mem_ap_read_u32(struct adiv5_ap *ap,
531 uint32_t address, uint32_t *value);
532 int mem_ap_write_u32(struct adiv5_ap *ap,
533 uint32_t address, uint32_t value);
535 /* Synchronous MEM-AP memory mapped single word transfers. */
536 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
537 uint32_t address, uint32_t *value);
538 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
539 uint32_t address, uint32_t value);
541 /* Synchronous MEM-AP memory mapped bus block transfers. */
542 int mem_ap_read_buf(struct adiv5_ap *ap,
543 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
544 int mem_ap_write_buf(struct adiv5_ap *ap,
545 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
547 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
548 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
549 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
550 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
551 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
553 /* Initialisation of the debug system, power domains and registers */
554 int dap_dp_init(struct adiv5_dap *dap);
555 int dap_dp_init_or_reconnect(struct adiv5_dap *dap);
556 int mem_ap_init(struct adiv5_ap *ap);
558 /* Invalidate cached DP select and cached TAR and CSW of all APs */
559 void dap_invalidate_cache(struct adiv5_dap *dap);
561 /* Probe the AP for ROM Table location */
562 int dap_get_debugbase(struct adiv5_ap *ap,
563 uint32_t *dbgbase, uint32_t *apid);
565 /* Probe Access Ports to find a particular type */
566 int dap_find_ap(struct adiv5_dap *dap,
567 enum ap_type type_to_find,
568 struct adiv5_ap **ap_out);
570 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
572 return &dap->ap[ap_num];
575 /* Lookup CoreSight component */
576 int dap_lookup_cs_component(struct adiv5_ap *ap,
577 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
581 /* Put debug link into SWD mode */
582 int dap_to_swd(struct adiv5_dap *dap);
584 /* Put debug link into JTAG mode */
585 int dap_to_jtag(struct adiv5_dap *dap);
587 extern const struct command_registration dap_instance_commands[];
589 struct arm_dap_object;
590 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
591 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
592 extern int dap_info_command(struct command_invocation *cmd,
593 struct adiv5_ap *ap);
594 extern int dap_register_commands(struct command_context *cmd_ctx);
595 extern const char *adiv5_dap_name(struct adiv5_dap *self);
596 extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
597 extern int dap_cleanup_all(void);
599 struct adiv5_private_config {
601 struct adiv5_dap *dap;
604 extern int adiv5_verify_config(struct adiv5_private_config *pc);
605 extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
607 struct adiv5_mem_ap_spot {
608 struct adiv5_dap *dap;
613 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p);
614 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
615 Jim_GetOptInfo *goi);
617 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */