1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
20 ***************************************************************************/
22 #ifndef OPENOCD_TARGET_ARM_ADI_V5_H
23 #define OPENOCD_TARGET_ARM_ADI_V5_H
27 * This defines formats and data structures used to talk to ADIv5 entities.
28 * Those include a DAP, different types of Debug Port (DP), and memory mapped
29 * resources accessed through a MEM-AP.
32 #include <helper/list.h>
35 /* three-bit ACK values for SWD access (sent LSB first) */
36 #define SWD_ACK_OK 0x1
37 #define SWD_ACK_WAIT 0x2
38 #define SWD_ACK_FAULT 0x4
43 #define BANK_REG(bank, reg) (((bank) << 4) | (reg))
45 /* A[3:0] for DP registers; A[1:0] are always zero.
46 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
47 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
48 * - SWD accesses these directly, sometimes needing SELECT.DPBANKSEL
50 #define DP_DPIDR BANK_REG(0x0, 0x0) /* DPv1+: ro */
51 #define DP_ABORT BANK_REG(0x0, 0x0) /* DPv1+: SWD: wo */
52 #define DP_CTRL_STAT BANK_REG(0x0, 0x4) /* DPv0+: rw */
53 #define DP_DLCR BANK_REG(0x1, 0x4) /* DPv1+: SWD: rw */
54 #define DP_TARGETID BANK_REG(0x2, 0x4) /* DPv2: ro */
55 #define DP_DLPIDR BANK_REG(0x3, 0x4) /* DPv2: ro */
56 #define DP_EVENTSTAT BANK_REG(0x4, 0x4) /* DPv2: ro */
57 #define DP_RESEND BANK_REG(0x0, 0x8) /* DPv1+: SWD: ro */
58 #define DP_SELECT BANK_REG(0x0, 0x8) /* DPv0+: JTAG: rw; SWD: wo */
59 #define DP_RDBUFF BANK_REG(0x0, 0xC) /* DPv0+: ro */
60 #define DP_TARGETSEL BANK_REG(0x0, 0xC) /* DPv2: SWD: wo */
62 #define DLCR_TO_TRN(dlcr) ((uint32_t)(1 + ((3 & (dlcr)) >> 8))) /* 1..4 clocks */
64 /* Fields of the DP's AP ABORT register */
65 #define DAPABORT (1UL << 0)
66 #define STKCMPCLR (1UL << 1) /* SWD-only */
67 #define STKERRCLR (1UL << 2) /* SWD-only */
68 #define WDERRCLR (1UL << 3) /* SWD-only */
69 #define ORUNERRCLR (1UL << 4) /* SWD-only */
71 /* Fields of the DP's CTRL/STAT register */
72 #define CORUNDETECT (1UL << 0)
73 #define SSTICKYORUN (1UL << 1)
74 /* 3:2 - transaction mode (e.g. pushed compare) */
75 #define SSTICKYCMP (1UL << 4)
76 #define SSTICKYERR (1UL << 5)
77 #define READOK (1UL << 6) /* SWD-only */
78 #define WDATAERR (1UL << 7) /* SWD-only */
79 /* 11:8 - mask lanes for pushed compare or verify ops */
80 /* 21:12 - transaction counter */
81 #define CDBGRSTREQ (1UL << 26)
82 #define CDBGRSTACK (1UL << 27)
83 #define CDBGPWRUPREQ (1UL << 28)
84 #define CDBGPWRUPACK (1UL << 29)
85 #define CSYSPWRUPREQ (1UL << 30)
86 #define CSYSPWRUPACK (1UL << 31)
88 /* MEM-AP register addresses */
89 #define MEM_AP_REG_CSW 0x00
90 #define MEM_AP_REG_TAR 0x04
91 #define MEM_AP_REG_TAR64 0x08 /* RW: Large Physical Address Extension */
92 #define MEM_AP_REG_DRW 0x0C /* RW: Data Read/Write register */
93 #define MEM_AP_REG_BD0 0x10 /* RW: Banked Data register 0-3 */
94 #define MEM_AP_REG_BD1 0x14
95 #define MEM_AP_REG_BD2 0x18
96 #define MEM_AP_REG_BD3 0x1C
97 #define MEM_AP_REG_MBT 0x20 /* --: Memory Barrier Transfer register */
98 #define MEM_AP_REG_BASE64 0xF0 /* RO: Debug Base Address (LA) register */
99 #define MEM_AP_REG_CFG 0xF4 /* RO: Configuration register */
100 #define MEM_AP_REG_BASE 0xF8 /* RO: Debug Base Address register */
101 /* Generic AP register address */
102 #define AP_REG_IDR 0xFC /* RO: Identification Register */
104 /* Fields of the MEM-AP's CSW register */
105 #define CSW_SIZE_MASK 7
109 #define CSW_ADDRINC_MASK (3UL << 4)
110 #define CSW_ADDRINC_OFF 0UL
111 #define CSW_ADDRINC_SINGLE (1UL << 4)
112 #define CSW_ADDRINC_PACKED (2UL << 4)
113 #define CSW_DEVICE_EN (1UL << 6)
114 #define CSW_TRIN_PROG (1UL << 7)
116 /* All fields in bits 12 and above are implementation-defined
117 * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
118 * Some bits are shared between buses
120 #define CSW_SPIDEN (1UL << 23)
121 #define CSW_DBGSWENABLE (1UL << 31)
123 /* AHB: Privileged */
124 #define CSW_AHB_HPROT1 (1UL << 25)
125 /* AHB: set HMASTER signals to AHB-AP ID */
126 #define CSW_AHB_MASTER_DEBUG (1UL << 29)
127 /* AHB5: non-secure access via HNONSEC
128 * AHB3: SBO, UNPREDICTABLE if zero */
129 #define CSW_AHB_SPROT (1UL << 30)
130 /* AHB: initial value of csw_default */
131 #define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
133 /* AXI: Privileged */
134 #define CSW_AXI_ARPROT0_PRIV (1UL << 28)
135 /* AXI: Non-secure */
136 #define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
137 /* AXI: initial value of csw_default */
138 #define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
140 /* APB: initial value of csw_default */
141 #define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
144 /* Fields of the MEM-AP's IDR register */
145 #define IDR_REV (0xFUL << 28)
146 #define IDR_JEP106 (0x7FFUL << 17)
147 #define IDR_CLASS (0xFUL << 13)
148 #define IDR_VARIANT (0xFUL << 4)
149 #define IDR_TYPE (0xFUL << 0)
151 #define IDR_JEP106_ARM 0x04760000
153 #define DP_SELECT_APSEL 0xFF000000
154 #define DP_SELECT_APBANK 0x000000F0
155 #define DP_SELECT_DPBANK 0x0000000F
156 #define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
158 #define DP_APSEL_MAX (255)
159 #define DP_APSEL_INVALID (-1)
161 /* FIXME: not SWD specific; should be renamed, e.g. adiv5_special_seq */
162 enum swd_special_seq {
172 * This represents an ARM Debug Interface (v5) Access Port (AP).
173 * Most common is a MEM-AP, for memory access.
177 * DAP this AP belongs to.
179 struct adiv5_dap *dap;
187 * Default value for (MEM-AP) AP_REG_CSW register.
189 uint32_t csw_default;
192 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
193 * configure an access mode, such as autoincrementing AP_REG_TAR during
194 * word access. "-1" indicates no cached value.
199 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
200 * configure the address being read or written
201 * "-1" indicates no cached value.
206 * Configures how many extra tck clocks are added after starting a
207 * MEM-AP access before we try to read its status (and/or result).
209 uint32_t memaccess_tck;
211 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
212 uint32_t tar_autoincr_block;
214 /* true if packed transfers are supported by the MEM-AP */
215 bool packed_transfers;
217 /* true if unaligned memory access is not supported by the MEM-AP */
218 bool unaligned_access_bad;
220 /* true if tar_value is in sync with TAR register */
226 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
227 * A DAP has two types of component: one Debug Port (DP), which is a
228 * transport agent; and at least one Access Port (AP), controlling
231 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
232 * Accordingly, this interface is responsible for hiding the transport
233 * differences so upper layer code can largely ignore them.
235 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
236 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
237 * a choice made at board design time (by only using the SWD pins), or
238 * as part of setting up a debug session (if all the dual-role JTAG/SWD
239 * signals are available).
242 const struct dap_ops *ops;
244 /* dap transaction list for WAIT support */
245 struct list_head cmd_journal;
247 /* pool for dap_cmd objects */
248 struct list_head cmd_pool;
250 /* number of dap_cmd objects in the pool */
251 size_t cmd_pool_size;
253 struct jtag_tap *tap;
255 uint32_t dp_ctrl_stat;
257 struct adiv5_ap ap[DP_APSEL_MAX + 1];
259 /* The current manually selected AP by the "dap apsel" command */
263 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
264 * indicates no cached value and forces rewrite of the register.
268 /* information about current pending SWjDP-AHBAP transaction */
272 * Holds the pointer to the destination word for the last queued read,
273 * for use with posted AP read sequence optimization.
277 /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
278 * despite lack of support in the ARMv7 architecture. Memory access through
279 * the AHB-AP has strange byte ordering these processors, and we need to
280 * swizzle appropriately. */
281 bool ti_be_32_quirks;
284 * STLINK adapter need to know if last AP operation was read or write, and
285 * in case of write has to flush it with a dummy read from DP_RDBUFF
287 bool stlink_flush_ap_write;
290 * Signals that an attempt to reestablish communication afresh
291 * should be performed before the next access.
295 /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
296 * do not set this bit until later in the bringup sequence */
297 bool ignore_syspwrupack;
301 * Transport-neutral representation of queued DAP transactions, supporting
302 * both JTAG and SWD transports. All submitted transactions are logically
303 * queued, until the queue is executed by run(). Some implementations might
304 * execute transactions as soon as they're submitted, but no status is made
305 * available until run().
308 /** connect operation for SWD */
309 int (*connect)(struct adiv5_dap *dap);
311 /** send a sequence to the DAP */
312 int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
314 /** DP register read. */
315 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
317 /** DP register write. */
318 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
321 /** AP register read. */
322 int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
324 /** AP register write. */
325 int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
328 /** AP operation abort. */
329 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
331 /** Executes all queued DAP operations. */
332 int (*run)(struct adiv5_dap *dap);
334 /** Executes all queued DAP operations but doesn't check
335 * sticky error conditions */
336 int (*sync)(struct adiv5_dap *dap);
338 /** Optional; called at OpenOCD exit */
339 void (*quit)(struct adiv5_dap *dap);
343 * Access Port classes
346 AP_CLASS_NONE = 0x00000, /* No class defined */
347 AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
354 AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
355 AP_TYPE_AHB3_AP = 0x1, /* AHB3 Memory-AP */
356 AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
357 AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
358 AP_TYPE_AHB5_AP = 0x5, /* AHB5 Memory-AP. */
362 * Send an adi-v5 sequence to the DAP.
364 * @param dap The DAP used for reading.
365 * @param seq The sequence to send.
367 * @return ERROR_OK for success, else a fault code.
369 static inline int dap_send_sequence(struct adiv5_dap *dap,
370 enum swd_special_seq seq)
372 assert(dap->ops != NULL);
373 return dap->ops->send_sequence(dap, seq);
377 * Queue a DP register read.
378 * Note that not all DP registers are readable; also, that JTAG and SWD
379 * have slight differences in DP register support.
381 * @param dap The DAP used for reading.
382 * @param reg The two-bit number of the DP register being read.
383 * @param data Pointer saying where to store the register's value
384 * (in host endianness).
386 * @return ERROR_OK for success, else a fault code.
388 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
389 unsigned reg, uint32_t *data)
391 assert(dap->ops != NULL);
392 return dap->ops->queue_dp_read(dap, reg, data);
396 * Queue a DP register write.
397 * Note that not all DP registers are writable; also, that JTAG and SWD
398 * have slight differences in DP register support.
400 * @param dap The DAP used for writing.
401 * @param reg The two-bit number of the DP register being written.
402 * @param data Value being written (host endianness)
404 * @return ERROR_OK for success, else a fault code.
406 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
407 unsigned reg, uint32_t data)
409 assert(dap->ops != NULL);
410 return dap->ops->queue_dp_write(dap, reg, data);
414 * Queue an AP register read.
416 * @param ap The AP used for reading.
417 * @param reg The number of the AP register being read.
418 * @param data Pointer saying where to store the register's value
419 * (in host endianness).
421 * @return ERROR_OK for success, else a fault code.
423 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
424 unsigned reg, uint32_t *data)
426 assert(ap->dap->ops != NULL);
427 return ap->dap->ops->queue_ap_read(ap, reg, data);
431 * Queue an AP register write.
433 * @param ap The AP used for writing.
434 * @param reg The number of the AP register being written.
435 * @param data Value being written (host endianness)
437 * @return ERROR_OK for success, else a fault code.
439 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
440 unsigned reg, uint32_t data)
442 assert(ap->dap->ops != NULL);
443 return ap->dap->ops->queue_ap_write(ap, reg, data);
447 * Queue an AP abort operation. The current AP transaction is aborted,
448 * including any update of the transaction counter. The AP is left in
449 * an unknown state (so it must be re-initialized). For use only after
450 * the AP has reported WAIT status for an extended period.
452 * @param dap The DAP used for writing.
453 * @param ack Pointer to where transaction status will be stored.
455 * @return ERROR_OK for success, else a fault code.
457 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
459 assert(dap->ops != NULL);
460 return dap->ops->queue_ap_abort(dap, ack);
464 * Perform all queued DAP operations, and clear any errors posted in the
465 * CTRL_STAT register when they are done. Note that if more than one AP
466 * operation will be queued, one of the first operations in the queue
467 * should probably enable CORUNDETECT in the CTRL/STAT register.
469 * @param dap The DAP used.
471 * @return ERROR_OK for success, else a fault code.
473 static inline int dap_run(struct adiv5_dap *dap)
475 assert(dap->ops != NULL);
476 return dap->ops->run(dap);
479 static inline int dap_sync(struct adiv5_dap *dap)
481 assert(dap->ops != NULL);
483 return dap->ops->sync(dap);
487 static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
492 retval = dap_queue_dp_read(dap, reg, value);
493 if (retval != ERROR_OK)
499 static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
500 uint32_t mask, uint32_t value, int timeout)
503 assert((value & mask) == value);
507 LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
510 ret = dap_dp_read_atomic(dap, reg, ®val);
514 if ((regval & mask) == value)
521 LOG_DEBUG("DAP: poll %x timeout", reg);
528 /* Queued MEM-AP memory mapped single word transfers. */
529 int mem_ap_read_u32(struct adiv5_ap *ap,
530 uint32_t address, uint32_t *value);
531 int mem_ap_write_u32(struct adiv5_ap *ap,
532 uint32_t address, uint32_t value);
534 /* Synchronous MEM-AP memory mapped single word transfers. */
535 int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
536 uint32_t address, uint32_t *value);
537 int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
538 uint32_t address, uint32_t value);
540 /* Synchronous MEM-AP memory mapped bus block transfers. */
541 int mem_ap_read_buf(struct adiv5_ap *ap,
542 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
543 int mem_ap_write_buf(struct adiv5_ap *ap,
544 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
546 /* Synchronous, non-incrementing buffer functions for accessing fifos. */
547 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
548 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
549 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
550 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address);
552 /* Initialisation of the debug system, power domains and registers */
553 int dap_dp_init(struct adiv5_dap *dap);
554 int dap_dp_init_or_reconnect(struct adiv5_dap *dap);
555 int mem_ap_init(struct adiv5_ap *ap);
557 /* Invalidate cached DP select and cached TAR and CSW of all APs */
558 void dap_invalidate_cache(struct adiv5_dap *dap);
560 /* Probe the AP for ROM Table location */
561 int dap_get_debugbase(struct adiv5_ap *ap,
562 uint32_t *dbgbase, uint32_t *apid);
564 /* Probe Access Ports to find a particular type */
565 int dap_find_ap(struct adiv5_dap *dap,
566 enum ap_type type_to_find,
567 struct adiv5_ap **ap_out);
569 static inline struct adiv5_ap *dap_ap(struct adiv5_dap *dap, uint8_t ap_num)
571 return &dap->ap[ap_num];
574 /* Lookup CoreSight component */
575 int dap_lookup_cs_component(struct adiv5_ap *ap,
576 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx);
580 /* Put debug link into SWD mode */
581 int dap_to_swd(struct adiv5_dap *dap);
583 /* Put debug link into JTAG mode */
584 int dap_to_jtag(struct adiv5_dap *dap);
586 extern const struct command_registration dap_instance_commands[];
588 struct arm_dap_object;
589 extern struct adiv5_dap *dap_instance_by_jim_obj(Jim_Interp *interp, Jim_Obj *o);
590 extern struct adiv5_dap *adiv5_get_dap(struct arm_dap_object *obj);
591 extern int dap_info_command(struct command_invocation *cmd,
592 struct adiv5_ap *ap);
593 extern int dap_register_commands(struct command_context *cmd_ctx);
594 extern const char *adiv5_dap_name(struct adiv5_dap *self);
595 extern const struct swd_driver *adiv5_dap_swd_driver(struct adiv5_dap *self);
596 extern int dap_cleanup_all(void);
598 struct adiv5_private_config {
600 struct adiv5_dap *dap;
603 extern int adiv5_verify_config(struct adiv5_private_config *pc);
604 extern int adiv5_jim_configure(struct target *target, Jim_GetOptInfo *goi);
606 struct adiv5_mem_ap_spot {
607 struct adiv5_dap *dap;
612 extern int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p);
613 extern int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
614 Jim_GetOptInfo *goi);
616 #endif /* OPENOCD_TARGET_ARM_ADI_V5_H */