1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 * This defines formats and data structures used to talk to ADIv5 entities.
29 * Those include a DAP, different types of Debug Port (DP), and memory mapped
30 * resources accessed through a MEM-AP.
35 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
36 #define JTAG_DP_ABORT 0x8
37 #define JTAG_DP_DPACC 0xA
38 #define JTAG_DP_APACC 0xB
39 #define JTAG_DP_IDCODE 0xE
41 /* three-bit ACK values for DPACC and APACC reads */
42 #define JTAG_ACK_OK_FAULT 0x2
43 #define JTAG_ACK_WAIT 0x1
45 /* three-bit ACK values for SWD access (sent LSB first) */
46 #define SWD_ACK_OK 0x4
47 #define SWD_ACK_WAIT 0x2
48 #define SWD_ACK_FAULT 0x1
53 /* A[3:0] for DP registers; A[1:0] are always zero.
54 * - JTAG accesses all of these via JTAG_DP_DPACC, except for
55 * IDCODE (JTAG_DP_IDCODE) and ABORT (JTAG_DP_ABORT).
56 * - SWD accesses these directly, sometimes needing SELECT.CTRLSEL
58 #define DP_IDCODE 0 /* SWD: read */
59 #define DP_ABORT 0 /* SWD: write */
60 #define DP_CTRL_STAT 0x4 /* r/w */
61 #define DP_WCR 0x4 /* SWD: r/w (mux CTRLSEL) */
62 #define DP_RESEND 0x8 /* SWD: read */
63 #define DP_SELECT 0x8 /* JTAG: r/w; SWD: write */
64 #define DP_RDBUFF 0xC /* read-only */
66 /* Fields of the DP's AP ABORT register */
67 #define DAPABORT (1 << 0)
68 #define STKCMPCLR (1 << 1) /* SWD-only */
69 #define STKERRCLR (1 << 2) /* SWD-only */
70 #define WDERRCLR (1 << 3) /* SWD-only */
71 #define ORUNERRCLR (1 << 4) /* SWD-only */
73 /* Fields of the DP's CTRL/STAT register */
74 #define CORUNDETECT (1 << 0)
75 #define SSTICKYORUN (1 << 1)
76 /* 3:2 - transaction mode (e.g. pushed compare) */
77 #define SSTICKYCMP (1 << 4)
78 #define SSTICKYERR (1 << 5)
79 #define READOK (1 << 6) /* SWD-only */
80 #define WDATAERR (1 << 7) /* SWD-only */
81 /* 11:8 - mask lanes for pushed compare or verify ops */
82 /* 21:12 - transaction counter */
83 #define CDBGRSTREQ (1 << 26)
84 #define CDBGRSTACK (1 << 27)
85 #define CDBGPWRUPREQ (1 << 28)
86 #define CDBGPWRUPACK (1 << 29)
87 #define CSYSPWRUPREQ (1 << 30)
88 #define CSYSPWRUPACK (1 << 31)
90 /* MEM-AP register addresses */
91 /* TODO: rename as MEM_AP_REG_* */
92 #define AP_REG_CSW 0x00
93 #define AP_REG_TAR 0x04
94 #define AP_REG_DRW 0x0C
95 #define AP_REG_BD0 0x10
96 #define AP_REG_BD1 0x14
97 #define AP_REG_BD2 0x18
98 #define AP_REG_BD3 0x1C
99 #define AP_REG_CFG 0xF4 /* big endian? */
100 #define AP_REG_BASE 0xF8
102 /* Generic AP register address */
103 #define AP_REG_IDR 0xFC
105 /* Fields of the MEM-AP's CSW register */
109 #define CSW_ADDRINC_MASK (3 << 4)
110 #define CSW_ADDRINC_OFF 0
111 #define CSW_ADDRINC_SINGLE (1 << 4)
112 #define CSW_ADDRINC_PACKED (2 << 4)
113 #define CSW_DEVICE_EN (1 << 6)
114 #define CSW_TRIN_PROG (1 << 7)
115 #define CSW_SPIDEN (1 << 23)
116 /* 30:24 - implementation-defined! */
117 #define CSW_HPROT (1 << 25) /* ? */
118 #define CSW_MASTER_DEBUG (1 << 29) /* ? */
119 #define CSW_DBGSWENABLE (1 << 31)
122 * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
123 * A DAP has two types of component: one Debug Port (DP), which is a
124 * transport agent; and at least one Access Port (AP), controlling
125 * resource access. Most common is a MEM-AP, for memory access.
127 * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
128 * Accordingly, this interface is responsible for hiding the transport
129 * differences so upper layer code can largely ignore them.
131 * When the chip is implemented with JTAG-DP or SW-DP, the transport is
132 * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
133 * a choice made at board design time (by only using the SWD pins), or
134 * as part of setting up a debug session (if all the dual-role JTAG/SWD
135 * signals are available).
139 const struct dap_ops *ops;
141 struct arm_jtag *jtag_info;
143 uint32_t dp_ctrl_stat;
146 * Cache for DP_SELECT bits identifying the current AP. A DAP may
147 * connect to multiple APs, such as one MEM-AP for general access,
148 * another reserved for accessing debug modules, and a JTAG-DP.
149 * "-1" indicates no cached value.
154 * Cache for DP_SELECT bits identifying the current four-word AP
155 * register bank. This caches AP register addresss bits 7:4; JTAG
156 * and SWD access primitves pass address bits 3:2; bits 1:0 are zero.
157 * "-1" indicates no cached value.
159 uint32_t ap_bank_value;
162 * Cache for (MEM-AP) AP_REG_CSW register value. This is written to
163 * configure an access mode, such as autoincrementing AP_REG_TAR during
164 * word access. "-1" indicates no cached value.
166 uint32_t ap_csw_value;
169 * Cache for (MEM-AP) AP_REG_TAR register value This is written to
170 * configure the address being read or written
171 * "-1" indicates no cached value.
173 uint32_t ap_tar_value;
175 /* information about current pending SWjDP-AHBAP transaction */
179 * Configures how many extra tck clocks are added after starting a
180 * MEM-AP access before we try to read its status (and/or result).
182 uint32_t memaccess_tck;
183 /* Size of TAR autoincrement block, ARM ADI Specification requires at least 10 bits */
184 uint32_t tar_autoincr_block;
189 * Transport-neutral representation of queued DAP transactions, supporting
190 * both JTAG and SWD transports. All submitted transactions are logically
191 * queued, until the queue is executed by run(). Some implementations might
192 * execute transactions as soon as they're submitted, but no status is made
193 * availablue until run().
196 /** If the DAP transport isn't SWD, it must be JTAG. Upper level
197 * code may need to care about the difference in some cases.
201 /** Reads the DAP's IDCODe register. */
202 int (*queue_idcode_read)(struct adiv5_dap *dap,
203 uint8_t *ack, uint32_t *data);
205 /** DP register read. */
206 int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
208 /** DP register write. */
209 int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
212 /** AP register read. */
213 int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
215 /** AP register write. */
216 int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
218 /** AP operation abort. */
219 int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
221 /** Executes all queued DAP operations. */
222 int (*run)(struct adiv5_dap *dap);
226 * Queue an IDCODE register read. This is primarily useful for SWD
227 * transports, where it is required as part of link initialization.
228 * (For JTAG, this register is read as part of scan chain setup.)
230 * @param dap The DAP used for reading.
231 * @param ack Pointer to where transaction status will be stored.
232 * @param data Pointer saying where to store the IDCODE value.
234 * @return ERROR_OK for success, else a fault code.
236 static inline int dap_queue_idcode_read(struct adiv5_dap *dap,
237 uint8_t *ack, uint32_t *data)
239 return dap->ops->queue_idcode_read(dap, ack, data);
243 * Queue a DP register read.
244 * Note that not all DP registers are readable; also, that JTAG and SWD
245 * have slight differences in DP register support.
247 * @param dap The DAP used for reading.
248 * @param reg The two-bit number of the DP register being read.
249 * @param data Pointer saying where to store the register's value
250 * (in host endianness).
252 * @return ERROR_OK for success, else a fault code.
254 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
255 unsigned reg, uint32_t *data)
257 return dap->ops->queue_dp_read(dap, reg, data);
261 * Queue a DP register write.
262 * Note that not all DP registers are writable; also, that JTAG and SWD
263 * have slight differences in DP register support.
265 * @param dap The DAP used for writing.
266 * @param reg The two-bit number of the DP register being written.
267 * @param data Value being written (host endianness)
269 * @return ERROR_OK for success, else a fault code.
271 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
272 unsigned reg, uint32_t data)
274 return dap->ops->queue_dp_write(dap, reg, data);
278 * Queue an AP register read.
280 * @param dap The DAP used for reading.
281 * @param reg The number of the AP register being read.
282 * @param data Pointer saying where to store the register's value
283 * (in host endianness).
285 * @return ERROR_OK for success, else a fault code.
287 static inline int dap_queue_ap_read(struct adiv5_dap *dap,
288 unsigned reg, uint32_t *data)
290 return dap->ops->queue_ap_read(dap, reg, data);
294 * Queue an AP register write.
296 * @param dap The DAP used for writing.
297 * @param reg The number of the AP register being written.
298 * @param data Value being written (host endianness)
300 * @return ERROR_OK for success, else a fault code.
302 static inline int dap_queue_ap_write(struct adiv5_dap *dap,
303 unsigned reg, uint32_t data)
305 return dap->ops->queue_ap_write(dap, reg, data);
309 * Queue an AP abort operation. The current AP transaction is aborted,
310 * including any update of the transaction counter. The AP is left in
311 * an unknown state (so it must be re-initialized). For use only after
312 * the AP has reported WAIT status for an extended period.
314 * @param dap The DAP used for writing.
315 * @param ack Pointer to where transaction status will be stored.
317 * @return ERROR_OK for success, else a fault code.
319 static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
321 return dap->ops->queue_ap_abort(dap, ack);
325 * Perform all queued DAP operations, and clear any errors posted in the
326 * CTRL_STAT register when they are done. Note that if more than one AP
327 * operation will be queued, one of the first operations in the queue
328 * should probably enable CORUNDETECT in the CTRL/STAT register.
330 * @param dap The DAP used.
332 * @return ERROR_OK for success, else a fault code.
334 static inline int dap_run(struct adiv5_dap *dap)
336 return dap->ops->run(dap);
339 /** Accessor for currently selected DAP-AP number (0..255) */
340 static inline uint8_t dap_ap_get_select(struct adiv5_dap *swjdp)
342 return (uint8_t)(swjdp ->apsel >> 24);
345 /* AP selection applies to future AP transactions */
346 void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel);
348 /* Queued AP transactions */
349 int dap_setup_accessport(struct adiv5_dap *swjdp,
350 uint32_t csw, uint32_t tar);
352 /* Queued MEM-AP memory mapped single word transfers */
353 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t *value);
354 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address, uint32_t value);
356 /* Synchronous MEM-AP memory mapped single word transfers */
357 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp,
358 uint32_t address, uint32_t *value);
359 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp,
360 uint32_t address, uint32_t value);
362 /* MEM-AP memory mapped bus block transfers */
363 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp,
364 uint8_t *buffer, int count, uint32_t address);
365 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp,
366 uint8_t *buffer, int count, uint32_t address);
367 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp,
368 uint8_t *buffer, int count, uint32_t address);
370 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp,
371 uint8_t *buffer, int count, uint32_t address);
372 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp,
373 uint8_t *buffer, int count, uint32_t address);
374 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp,
375 uint8_t *buffer, int count, uint32_t address);
377 /* Initialisation of the debug system, power domains and registers */
378 int ahbap_debugport_init(struct adiv5_dap *swjdp);
383 /* Put debug link into SWD mode */
384 int dap_to_swd(struct target *target);
386 /* Put debug link into JTAG mode */
387 int dap_to_jtag(struct target *target);
389 extern const struct command_registration dap_command_handlers[];