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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116         }
 117 }
 118
 119 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
 120 {
 121         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 122                 ap->csw_default;
 123
 124         if (csw != ap->csw_value) {
 125                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 126                 int retval = dap_queue_ap_write(ap->dap, MEM_AP_REG_CSW, csw);
 127                 if (retval != ERROR_OK)
 128                         return retval;
 129                 ap->csw_value = csw;
 130         }
 131         return ERROR_OK;
 132 }
 133
 134 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
 135 {
 136         if (tar != ap->tar_value ||
 137                         (ap->csw_value & CSW_ADDRINC_MASK)) {
 138                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 139                 int retval = dap_queue_ap_write(ap->dap, MEM_AP_REG_TAR, tar);
 140                 if (retval != ERROR_OK)
 141                         return retval;
 142                 ap->tar_value = tar;
 143         }
 144         return ERROR_OK;
 145 }
 146
 147 /**
 148  * Queue transactions setting up transfer parameters for the
 149  * currently selected MEM-AP.
 150  *
 151  * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
 152  * initiate data reads or writes using memory or peripheral addresses.
 153  * If the CSW is configured for it, the TAR may be automatically
 154  * incremented after each transfer.
 155  *
 156  * @param ap The MEM-AP.
 157  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 158  *      matches the cached value, the register is not changed.
 159  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 160  *      matches the cached address, the register is not changed.
 161  *
 162  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 163  */
 164 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
 165 {
 166         int retval;
 167         retval = mem_ap_setup_csw(ap, csw);
 168         if (retval != ERROR_OK)
 169                 return retval;
 170         retval = mem_ap_setup_tar(ap, tar);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         return ERROR_OK;
 174 }
 175
 176 /**
 177  * Asynchronous (queued) read of a word from memory or a system register.
 178  *
 179  * @param ap The MEM-AP to access.
 180  * @param address Address of the 32-bit word to read; it must be
 181  *      readable by the currently selected MEM-AP.
 182  * @param value points to where the word will be stored when the
 183  *      transaction queue is flushed (assuming no errors).
 184  *
 185  * @return ERROR_OK for success.  Otherwise a fault code.
 186  */
 187 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
 188                 uint32_t *value)
 189 {
 190         int retval;
 191
 192         dap_ap_select(ap->dap, ap->ap_num);
 193
 194         /* Use banked addressing (REG_BDx) to avoid some link traffic
 195          * (updating TAR) when reading several consecutive addresses.
 196          */
 197         retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
 198                         address & 0xFFFFFFF0);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         return dap_queue_ap_read(ap->dap, MEM_AP_REG_BD0 | (address & 0xC), value);
 203 }
 204
 205 /**
 206  * Synchronous read of a word from memory or a system register.
 207  * As a side effect, this flushes any queued transactions.
 208  *
 209  * @param ap The MEM-AP to access.
 210  * @param address Address of the 32-bit word to read; it must be
 211  *      readable by the currently selected MEM-AP.
 212  * @param value points to where the result will be stored.
 213  *
 214  * @return ERROR_OK for success; *value holds the result.
 215  * Otherwise a fault code.
 216  */
 217 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 218                 uint32_t *value)
 219 {
 220         int retval;
 221
 222         retval = mem_ap_read_u32(ap, address, value);
 223         if (retval != ERROR_OK)
 224                 return retval;
 225
 226         return dap_run(ap->dap);
 227 }
 228
 229 /**
 230  * Asynchronous (queued) write of a word to memory or a system register.
 231  *
 232  * @param ap The MEM-AP to access.
 233  * @param address Address to be written; it must be writable by
 234  *      the currently selected MEM-AP.
 235  * @param value Word that will be written to the address when transaction
 236  *      queue is flushed (assuming no errors).
 237  *
 238  * @return ERROR_OK for success.  Otherwise a fault code.
 239  */
 240 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
 241                 uint32_t value)
 242 {
 243         int retval;
 244
 245         dap_ap_select(ap->dap, ap->ap_num);
 246
 247         /* Use banked addressing (REG_BDx) to avoid some link traffic
 248          * (updating TAR) when writing several consecutive addresses.
 249          */
 250         retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
 251                         address & 0xFFFFFFF0);
 252         if (retval != ERROR_OK)
 253                 return retval;
 254
 255         return dap_queue_ap_write(ap->dap, MEM_AP_REG_BD0 | (address & 0xC),
 256                         value);
 257 }
 258
 259 /**
 260  * Synchronous write of a word to memory or a system register.
 261  * As a side effect, this flushes any queued transactions.
 262  *
 263  * @param ap The MEM-AP to access.
 264  * @param address Address to be written; it must be writable by
 265  *      the currently selected MEM-AP.
 266  * @param value Word that will be written.
 267  *
 268  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 269  */
 270 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 271                 uint32_t value)
 272 {
 273         int retval = mem_ap_write_u32(ap, address, value);
 274
 275         if (retval != ERROR_OK)
 276                 return retval;
 277
 278         return dap_run(ap->dap);
 279 }
 280
 281 /**
 282  * Synchronous write of a block of memory, using a specific access size.
 283  *
 284  * @param ap The MEM-AP to access.
 285  * @param buffer The data buffer to write. No particular alignment is assumed.
 286  * @param size Which access size to use, in bytes. 1, 2 or 4.
 287  * @param count The number of writes to do (in size units, not bytes).
 288  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 289  * @param addrinc Whether the target address should be increased for each write or not. This
 290  *  should normally be true, except when writing to e.g. a FIFO.
 291  * @return ERROR_OK on success, otherwise an error code.
 292  */
 293 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
 294                 uint32_t address, bool addrinc)
 295 {
 296         struct adiv5_dap *dap = ap->dap;
 297         size_t nbytes = size * count;
 298         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 299         uint32_t csw_size;
 300         uint32_t addr_xor;
 301         int retval;
 302
 303         /* TI BE-32 Quirks mode:
 304          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 305          *   size   write address   bytes written in order
 306          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 307          *   2      TAR ^ 2         (val >> 8), (val)
 308          *   1      TAR ^ 3         (val)
 309          * For example, if you attempt to write a single byte to address 0, the processor
 310          * will actually write a byte to address 3.
 311          *
 312          * To make writes of size < 4 work as expected, we xor a value with the address before
 313          * setting the TAP, and we set the TAP after every transfer rather then relying on
 314          * address increment. */
 315
 316         if (size == 4) {
 317                 csw_size = CSW_32BIT;
 318                 addr_xor = 0;
 319         } else if (size == 2) {
 320                 csw_size = CSW_16BIT;
 321                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 322         } else if (size == 1) {
 323                 csw_size = CSW_8BIT;
 324                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 325         } else {
 326                 return ERROR_TARGET_UNALIGNED_ACCESS;
 327         }
 328
 329         if (ap->unaligned_access_bad && (address % size != 0))
 330                 return ERROR_TARGET_UNALIGNED_ACCESS;
 331
 332         dap_ap_select(ap->dap, ap->ap_num);
 333
 334         retval = mem_ap_setup_tar(ap, address ^ addr_xor);
 335         if (retval != ERROR_OK)
 336                 return retval;
 337
 338         while (nbytes > 0) {
 339                 uint32_t this_size = size;
 340
 341                 /* Select packed transfer if possible */
 342                 if (addrinc && ap->packed_transfers && nbytes >= 4
 343                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 344                         this_size = 4;
 345                         retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
 346                 } else {
 347                         retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
 348                 }
 349
 350                 if (retval != ERROR_OK)
 351                         break;
 352
 353                 /* How many source bytes each transfer will consume, and their location in the DRW,
 354                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 355                 uint32_t outvalue = 0;
 356                 if (dap->ti_be_32_quirks) {
 357                         switch (this_size) {
 358                         case 4:
 359                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 360                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 2:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 366                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 367                                 break;
 368                         case 1:
 369                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 370                                 break;
 371                         }
 372                 } else {
 373                         switch (this_size) {
 374                         case 4:
 375                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         case 2:
 378                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 379                         case 1:
 380                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 381                         }
 382                 }
 383
 384                 nbytes -= this_size;
 385
 386                 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
 387                 if (retval != ERROR_OK)
 388                         break;
 389
 390                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 391                 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
 392                         retval = mem_ap_setup_tar(ap, address ^ addr_xor);
 393                         if (retval != ERROR_OK)
 394                                 break;
 395                 }
 396         }
 397
 398         /* REVISIT: Might want to have a queued version of this function that does not run. */
 399         if (retval == ERROR_OK)
 400                 retval = dap_run(dap);
 401
 402         if (retval != ERROR_OK) {
 403                 uint32_t tar;
 404                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 405                                 && dap_run(dap) == ERROR_OK)
 406                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 407                 else
 408                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 409         }
 410
 411         return retval;
 412 }
 413
 414 /**
 415  * Synchronous read of a block of memory, using a specific access size.
 416  *
 417  * @param ap The MEM-AP to access.
 418  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 419  * @param size Which access size to use, in bytes. 1, 2 or 4.
 420  * @param count The number of reads to do (in size units, not bytes).
 421  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 422  * @param addrinc Whether the target address should be increased after each read or not. This
 423  *  should normally be true, except when reading from e.g. a FIFO.
 424  * @return ERROR_OK on success, otherwise an error code.
 425  */
 426 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
 427                 uint32_t adr, bool addrinc)
 428 {
 429         struct adiv5_dap *dap = ap->dap;
 430         size_t nbytes = size * count;
 431         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 432         uint32_t csw_size;
 433         uint32_t address = adr;
 434         int retval;
 435
 436         /* TI BE-32 Quirks mode:
 437          * Reads on big-endian TMS570 behave strangely differently than writes.
 438          * They read from the physical address requested, but with DRW byte-reversed.
 439          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 440          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 441          * so avoid them. */
 442
 443         if (size == 4)
 444                 csw_size = CSW_32BIT;
 445         else if (size == 2)
 446                 csw_size = CSW_16BIT;
 447         else if (size == 1)
 448                 csw_size = CSW_8BIT;
 449         else
 450                 return ERROR_TARGET_UNALIGNED_ACCESS;
 451
 452         if (ap->unaligned_access_bad && (adr % size != 0))
 453                 return ERROR_TARGET_UNALIGNED_ACCESS;
 454
 455         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 456          * over-allocation if packed transfers are going to be used, but determining the real need at
 457          * this point would be messy. */
 458         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 459         uint32_t *read_ptr = read_buf;
 460         if (read_buf == NULL) {
 461                 LOG_ERROR("Failed to allocate read buffer");
 462                 return ERROR_FAIL;
 463         }
 464
 465         dap_ap_select(ap->dap, ap->ap_num);
 466
 467         retval = mem_ap_setup_tar(ap, address);
 468         if (retval != ERROR_OK) {
 469                 free(read_buf);
 470                 return retval;
 471         }
 472
 473         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 474          * useful bytes it contains, and their location in the word, depends on the type of transfer
 475          * and alignment. */
 476         while (nbytes > 0) {
 477                 uint32_t this_size = size;
 478
 479                 /* Select packed transfer if possible */
 480                 if (addrinc && ap->packed_transfers && nbytes >= 4
 481                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 482                         this_size = 4;
 483                         retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
 484                 } else {
 485                         retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
 486                 }
 487                 if (retval != ERROR_OK)
 488                         break;
 489
 490                 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
 491                 if (retval != ERROR_OK)
 492                         break;
 493
 494                 nbytes -= this_size;
 495                 address += this_size;
 496
 497                 /* Rewrite TAR if it wrapped */
 498                 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
 499                         retval = mem_ap_setup_tar(ap, address);
 500                         if (retval != ERROR_OK)
 501                                 break;
 502                 }
 503         }
 504
 505         if (retval == ERROR_OK)
 506                 retval = dap_run(dap);
 507
 508         /* Restore state */
 509         address = adr;
 510         nbytes = size * count;
 511         read_ptr = read_buf;
 512
 513         /* If something failed, read TAR to find out how much data was successfully read, so we can
 514          * at least give the caller what we have. */
 515         if (retval != ERROR_OK) {
 516                 uint32_t tar;
 517                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 518                                 && dap_run(dap) == ERROR_OK) {
 519                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 520                         if (nbytes > tar - address)
 521                                 nbytes = tar - address;
 522                 } else {
 523                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 524                         nbytes = 0;
 525                 }
 526         }
 527
 528         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 529         while (nbytes > 0) {
 530                 uint32_t this_size = size;
 531
 532                 if (addrinc && ap->packed_transfers && nbytes >= 4
 533                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 534                         this_size = 4;
 535                 }
 536
 537                 if (dap->ti_be_32_quirks) {
 538                         switch (this_size) {
 539                         case 4:
 540                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 541                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 542                         case 2:
 543                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 544                         case 1:
 545                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 546                         }
 547                 } else {
 548                         switch (this_size) {
 549                         case 4:
 550                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 551                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 552                         case 2:
 553                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 554                         case 1:
 555                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 556                         }
 557                 }
 558
 559                 read_ptr++;
 560                 nbytes -= this_size;
 561         }
 562
 563         free(read_buf);
 564         return retval;
 565 }
 566
 567 int mem_ap_read_buf(struct adiv5_ap *ap,
 568                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 569 {
 570         return mem_ap_read(ap, buffer, size, count, address, true);
 571 }
 572
 573 int mem_ap_write_buf(struct adiv5_ap *ap,
 574                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 575 {
 576         return mem_ap_write(ap, buffer, size, count, address, true);
 577 }
 578
 579 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
 580                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 581 {
 582         return mem_ap_read(ap, buffer, size, count, address, false);
 583 }
 584
 585 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
 586                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 587 {
 588         return mem_ap_write(ap, buffer, size, count, address, false);
 589 }
 590
 591 /*--------------------------------------------------------------------------*/
 592
 593
 594 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 595
 596 /* FIXME don't import ... just initialize as
 597  * part of DAP transport setup
 598 */
 599 extern const struct dap_ops jtag_dp_ops;
 600
 601 /*--------------------------------------------------------------------------*/
 602
 603 /**
 604  * Create a new DAP
 605  */
 606 struct adiv5_dap *dap_init(void)
 607 {
 608         struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
 609         int i;
 610         /* Set up with safe defaults */
 611         for (i = 0; i <= 255; i++) {
 612                 dap->ap[i].dap = dap;
 613                 dap->ap[i].ap_num = i;
 614                 /* memaccess_tck max is 255 */
 615                 dap->ap[i].memaccess_tck = 255;
 616                 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
 617                 dap->ap[i].tar_autoincr_block = (1<<10);
 618         }
 619         dap->ap_current = -1;
 620         dap->ap_bank_value = -1;
 621         dap->dp_bank_value = -1;
 622         return dap;
 623 }
 624
 625 /**
 626  * Initialize a DAP.  This sets up the power domains, prepares the DP
 627  * for further use and activates overrun checking.
 628  *
 629  * @param dap The DAP being initialized.
 630  */
 631 int dap_dp_init(struct adiv5_dap *dap)
 632 {
 633         int retval;
 634
 635         LOG_DEBUG(" ");
 636         /* JTAG-DP or SWJ-DP, in JTAG mode
 637          * ... for SWD mode this is patched as part
 638          * of link switchover
 639          * FIXME: This should already be setup by the respective transport specific DAP creation.
 640          */
 641         if (!dap->ops)
 642                 dap->ops = &jtag_dp_ops;
 643
 644         dap->ap_current = -1;
 645         dap->ap_bank_value = -1;
 646         dap->last_read = NULL;
 647
 648         for (size_t i = 0; i < 10; i++) {
 649                 /* DP initialization */
 650
 651                 dap->dp_bank_value = 0;
 652
 653                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 654                 if (retval != ERROR_OK)
 655                         continue;
 656
 657                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 658                 if (retval != ERROR_OK)
 659                         continue;
 660
 661                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 662                 if (retval != ERROR_OK)
 663                         continue;
 664
 665                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 666                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 667                 if (retval != ERROR_OK)
 668                         continue;
 669
 670                 /* Check that we have debug power domains activated */
 671                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 672                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 673                                               CDBGPWRUPACK, CDBGPWRUPACK,
 674                                               DAP_POWER_DOMAIN_TIMEOUT);
 675                 if (retval != ERROR_OK)
 676                         continue;
 677
 678                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 679                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 680                                               CSYSPWRUPACK, CSYSPWRUPACK,
 681                                               DAP_POWER_DOMAIN_TIMEOUT);
 682                 if (retval != ERROR_OK)
 683                         continue;
 684
 685                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 686                 if (retval != ERROR_OK)
 687                         continue;
 688
 689                 /* With debug power on we can activate OVERRUN checking */
 690                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 691                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 692                 if (retval != ERROR_OK)
 693                         continue;
 694                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 695                 if (retval != ERROR_OK)
 696                         continue;
 697
 698                 retval = dap_run(dap);
 699                 if (retval != ERROR_OK)
 700                         continue;
 701
 702                 break;
 703         }
 704
 705         return retval;
 706 }
 707
 708 /**
 709  * Initialize a DAP.  This sets up the power domains, prepares the DP
 710  * for further use, and arranges to use AP #0 for all AP operations
 711  * until dap_ap-select() changes that policy.
 712  *
 713  * @param ap The MEM-AP being initialized.
 714  */
 715 int mem_ap_init(struct adiv5_ap *ap)
 716 {
 717         /* check that we support packed transfers */
 718         uint32_t csw, cfg;
 719         int retval;
 720         struct adiv5_dap *dap = ap->dap;
 721
 722         dap_ap_select(dap, ap->ap_num);
 723
 724         retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 725         if (retval != ERROR_OK)
 726                 return retval;
 727
 728         retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
 729         if (retval != ERROR_OK)
 730                 return retval;
 731
 732         retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
 733         if (retval != ERROR_OK)
 734                 return retval;
 735
 736         retval = dap_run(dap);
 737         if (retval != ERROR_OK)
 738                 return retval;
 739
 740         if (csw & CSW_ADDRINC_PACKED)
 741                 ap->packed_transfers = true;
 742         else
 743                 ap->packed_transfers = false;
 744
 745         /* Packed transfers on TI BE-32 processors do not work correctly in
 746          * many cases. */
 747         if (dap->ti_be_32_quirks)
 748                 ap->packed_transfers = false;
 749
 750         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 751                         ap->packed_transfers ? "enabled" : "disabled");
 752
 753         /* The ARM ADI spec leaves implementation-defined whether unaligned
 754          * memory accesses work, only work partially, or cause a sticky error.
 755          * On TI BE-32 processors, reads seem to return garbage in some bytes
 756          * and unaligned writes seem to cause a sticky error.
 757          * TODO: it would be nice to have a way to detect whether unaligned
 758          * operations are supported on other processors. */
 759         ap->unaligned_access_bad = dap->ti_be_32_quirks;
 760
 761         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 762                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 763
 764         return ERROR_OK;
 765 }
 766
 767 /* CID interpretation -- see ARM IHI 0029B section 3
 768  * and ARM IHI 0031A table 13-3.
 769  */
 770 static const char *class_description[16] = {
 771         "Reserved", "ROM table", "Reserved", "Reserved",
 772         "Reserved", "Reserved", "Reserved", "Reserved",
 773         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 774         "Reserved", "OptimoDE DESS",
 775         "Generic IP component", "PrimeCell or System component"
 776 };
 777
 778 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 779 {
 780         return cid3 == 0xb1 && cid2 == 0x05
 781                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 782 }
 783
 784 /*
 785  * This function checks the ID for each access port to find the requested Access Port type
 786  */
 787 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 788 {
 789         int ap_num;
 790
 791         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 792         for (ap_num = 0; ap_num <= 255; ap_num++) {
 793
 794                 /* read the IDR register of the Access Port */
 795                 uint32_t id_val = 0;
 796                 dap_ap_select(dap, ap_num);
 797
 798                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 799                 if (retval != ERROR_OK)
 800                         return retval;
 801
 802                 retval = dap_run(dap);
 803
 804                 /* IDR bits:
 805                  * 31-28 : Revision
 806                  * 27-24 : JEDEC bank (0x4 for ARM)
 807                  * 23-17 : JEDEC code (0x3B for ARM)
 808                  * 16-13 : Class (0b1000=Mem-AP)
 809                  * 12-8  : Reserved
 810                  *  7-4  : AP Variant (non-zero for JTAG-AP)
 811                  *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
 812                  */
 813
 814                 /* Reading register for a non-existant AP should not cause an error,
 815                  * but just to be sure, try to continue searching if an error does happen.
 816                  */
 817                 if ((retval == ERROR_OK) &&                  /* Register read success */
 818                         ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
 819                         ((id_val & IDR_TYPE) == type_to_find)) {      /* type matches*/
 820
 821                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 822                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 823                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 824                                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 825                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 826                                                 ap_num, id_val);
 827
 828                         *ap_out = &dap->ap[ap_num];
 829                         return ERROR_OK;
 830                 }
 831         }
 832
 833         LOG_DEBUG("No %s found",
 834                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 835                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 836                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 837                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 838         return ERROR_FAIL;
 839 }
 840
 841 int dap_get_debugbase(struct adiv5_ap *ap,
 842                         uint32_t *dbgbase, uint32_t *apid)
 843 {
 844         struct adiv5_dap *dap = ap->dap;
 845         int retval;
 846
 847         dap_ap_select(dap, ap->ap_num);
 848
 849         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
 850         if (retval != ERROR_OK)
 851                 return retval;
 852         retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
 853         if (retval != ERROR_OK)
 854                 return retval;
 855         retval = dap_run(dap);
 856         if (retval != ERROR_OK)
 857                 return retval;
 858
 859         return ERROR_OK;
 860 }
 861
 862 int dap_lookup_cs_component(struct adiv5_ap *ap,
 863                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
 864 {
 865         uint32_t romentry, entry_offset = 0, component_base, devtype;
 866         int retval;
 867
 868         *addr = 0;
 869
 870         do {
 871                 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
 872                                                 entry_offset, &romentry);
 873                 if (retval != ERROR_OK)
 874                         return retval;
 875
 876                 component_base = (dbgbase & 0xFFFFF000)
 877                         + (romentry & 0xFFFFF000);
 878
 879                 if (romentry & 0x1) {
 880                         uint32_t c_cid1;
 881                         retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
 882                         if (retval != ERROR_OK) {
 883                                 LOG_ERROR("Can't read component with base address 0x%" PRIx32
 884                                           ", the corresponding core might be turned off", component_base);
 885                                 return retval;
 886                         }
 887                         if (((c_cid1 >> 4) & 0x0f) == 1) {
 888                                 retval = dap_lookup_cs_component(ap, component_base,
 889                                                         type, addr, idx);
 890                                 if (retval == ERROR_OK)
 891                                         break;
 892                                 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 893                                         return retval;
 894                         }
 895
 896                         retval = mem_ap_read_atomic_u32(ap,
 897                                         (component_base & 0xfffff000) | 0xfcc,
 898                                         &devtype);
 899                         if (retval != ERROR_OK)
 900                                 return retval;
 901                         if ((devtype & 0xff) == type) {
 902                                 if (!*idx) {
 903                                         *addr = component_base;
 904                                         break;
 905                                 } else
 906                                         (*idx)--;
 907                         }
 908                 }
 909                 entry_offset += 4;
 910         } while (romentry > 0);
 911
 912         if (!*addr)
 913                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 914
 915         return ERROR_OK;
 916 }
 917
 918 static int dap_rom_display(struct command_context *cmd_ctx,
 919                                 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
 920 {
 921         struct adiv5_dap *dap = ap->dap;
 922         int retval;
 923         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 924         uint16_t entry_offset;
 925         char tabs[7] = "";
 926
 927         if (depth > 16) {
 928                 command_print(cmd_ctx, "\tTables too deep");
 929                 return ERROR_FAIL;
 930         }
 931
 932         if (depth)
 933                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 934
 935         /* bit 16 of apid indicates a memory access port */
 936         if (dbgbase & 0x02)
 937                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 938         else
 939                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 940
 941         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 942         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 943         if (retval != ERROR_OK)
 944                 return retval;
 945         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 946         if (retval != ERROR_OK)
 947                 return retval;
 948         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 949         if (retval != ERROR_OK)
 950                 return retval;
 951         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 952         if (retval != ERROR_OK)
 953                 return retval;
 954         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 955         if (retval != ERROR_OK)
 956                 return retval;
 957         retval = dap_run(dap);
 958         if (retval != ERROR_OK)
 959                 return retval;
 960
 961         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 962                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 963                                 ", CID2 0x%02x"
 964                                 ", CID1 0x%02x"
 965                                 ", CID0 0x%02x",
 966                                 tabs,
 967                                 (unsigned)cid3, (unsigned)cid2,
 968                                 (unsigned)cid1, (unsigned)cid0);
 969         if (memtype & 0x01)
 970                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
 971         else
 972                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
 973
 974         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
 975         for (entry_offset = 0; ; entry_offset += 4) {
 976                 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 977                 if (retval != ERROR_OK)
 978                         return retval;
 979                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 980                                 tabs, entry_offset, romentry);
 981                 if (romentry & 0x01) {
 982                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
 983                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
 984                         uint32_t component_base;
 985                         uint32_t part_num;
 986                         const char *type, *full;
 987
 988                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
 989
 990                         /* IDs are in last 4K section */
 991                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
 992                         if (retval != ERROR_OK) {
 993                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
 994                                               ", the corresponding core might be turned off", tabs, component_base);
 995                                 continue;
 996                         }
 997                         c_pid0 &= 0xff;
 998                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
 999                         if (retval != ERROR_OK)
1000                                 return retval;
1001                         c_pid1 &= 0xff;
1002                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
1003                         if (retval != ERROR_OK)
1004                                 return retval;
1005                         c_pid2 &= 0xff;
1006                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
1007                         if (retval != ERROR_OK)
1008                                 return retval;
1009                         c_pid3 &= 0xff;
1010                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
1011                         if (retval != ERROR_OK)
1012                                 return retval;
1013                         c_pid4 &= 0xff;
1014
1015                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1016                         if (retval != ERROR_OK)
1017                                 return retval;
1018                         c_cid0 &= 0xff;
1019                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1020                         if (retval != ERROR_OK)
1021                                 return retval;
1022                         c_cid1 &= 0xff;
1023                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1024                         if (retval != ERROR_OK)
1025                                 return retval;
1026                         c_cid2 &= 0xff;
1027                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1028                         if (retval != ERROR_OK)
1029                                 return retval;
1030                         c_cid3 &= 0xff;
1031
1032                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1033                                       "start address 0x%" PRIx32, component_base,
1034                                       /* component may take multiple 4K pages */
1035                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1036                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1037                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1038                                         /* See ARM IHI 0029B Table 3-3 */
1039                                         class_description[(c_cid1 >> 4) & 0xf]);
1040
1041                         /* CoreSight component? */
1042                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1043                                 uint32_t devtype;
1044                                 unsigned minor;
1045                                 const char *major = "Reserved", *subtype = "Reserved";
1046
1047                                 retval = mem_ap_read_atomic_u32(ap,
1048                                                 (component_base & 0xfffff000) | 0xfcc,
1049                                                 &devtype);
1050                                 if (retval != ERROR_OK)
1051                                         return retval;
1052                                 minor = (devtype >> 4) & 0x0f;
1053                                 switch (devtype & 0x0f) {
1054                                 case 0:
1055                                         major = "Miscellaneous";
1056                                         switch (minor) {
1057                                         case 0:
1058                                                 subtype = "other";
1059                                                 break;
1060                                         case 4:
1061                                                 subtype = "Validation component";
1062                                                 break;
1063                                         }
1064                                         break;
1065                                 case 1:
1066                                         major = "Trace Sink";
1067                                         switch (minor) {
1068                                         case 0:
1069                                                 subtype = "other";
1070                                                 break;
1071                                         case 1:
1072                                                 subtype = "Port";
1073                                                 break;
1074                                         case 2:
1075                                                 subtype = "Buffer";
1076                                                 break;
1077                                         case 3:
1078                                                 subtype = "Router";
1079                                                 break;
1080                                         }
1081                                         break;
1082                                 case 2:
1083                                         major = "Trace Link";
1084                                         switch (minor) {
1085                                         case 0:
1086                                                 subtype = "other";
1087                                                 break;
1088                                         case 1:
1089                                                 subtype = "Funnel, router";
1090                                                 break;
1091                                         case 2:
1092                                                 subtype = "Filter";
1093                                                 break;
1094                                         case 3:
1095                                                 subtype = "FIFO, buffer";
1096                                                 break;
1097                                         }
1098                                         break;
1099                                 case 3:
1100                                         major = "Trace Source";
1101                                         switch (minor) {
1102                                         case 0:
1103                                                 subtype = "other";
1104                                                 break;
1105                                         case 1:
1106                                                 subtype = "Processor";
1107                                                 break;
1108                                         case 2:
1109                                                 subtype = "DSP";
1110                                                 break;
1111                                         case 3:
1112                                                 subtype = "Engine/Coprocessor";
1113                                                 break;
1114                                         case 4:
1115                                                 subtype = "Bus";
1116                                                 break;
1117                                         case 6:
1118                                                 subtype = "Software";
1119                                                 break;
1120                                         }
1121                                         break;
1122                                 case 4:
1123                                         major = "Debug Control";
1124                                         switch (minor) {
1125                                         case 0:
1126                                                 subtype = "other";
1127                                                 break;
1128                                         case 1:
1129                                                 subtype = "Trigger Matrix";
1130                                                 break;
1131                                         case 2:
1132                                                 subtype = "Debug Auth";
1133                                                 break;
1134                                         case 3:
1135                                                 subtype = "Power Requestor";
1136                                                 break;
1137                                         }
1138                                         break;
1139                                 case 5:
1140                                         major = "Debug Logic";
1141                                         switch (minor) {
1142                                         case 0:
1143                                                 subtype = "other";
1144                                                 break;
1145                                         case 1:
1146                                                 subtype = "Processor";
1147                                                 break;
1148                                         case 2:
1149                                                 subtype = "DSP";
1150                                                 break;
1151                                         case 3:
1152                                                 subtype = "Engine/Coprocessor";
1153                                                 break;
1154                                         case 4:
1155                                                 subtype = "Bus";
1156                                                 break;
1157                                         case 5:
1158                                                 subtype = "Memory";
1159                                                 break;
1160                                         }
1161                                         break;
1162                                 case 6:
1163                                         major = "Perfomance Monitor";
1164                                         switch (minor) {
1165                                         case 0:
1166                                                 subtype = "other";
1167                                                 break;
1168                                         case 1:
1169                                                 subtype = "Processor";
1170                                                 break;
1171                                         case 2:
1172                                                 subtype = "DSP";
1173                                                 break;
1174                                         case 3:
1175                                                 subtype = "Engine/Coprocessor";
1176                                                 break;
1177                                         case 4:
1178                                                 subtype = "Bus";
1179                                                 break;
1180                                         case 5:
1181                                                 subtype = "Memory";
1182                                                 break;
1183                                         }
1184                                         break;
1185                                 }
1186                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1187                                                 (uint8_t)(devtype & 0xff),
1188                                                 major, subtype);
1189                                 /* REVISIT also show 0xfc8 DevId */
1190                         }
1191
1192                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1193                                 command_print(cmd_ctx,
1194                                                 "\t\tCID3 0%02x"
1195                                                 ", CID2 0%02x"
1196                                                 ", CID1 0%02x"
1197                                                 ", CID0 0%02x",
1198                                                 (int)c_cid3,
1199                                                 (int)c_cid2,
1200                                                 (int)c_cid1,
1201                                                 (int)c_cid0);
1202                         command_print(cmd_ctx,
1203                                 "\t\tPeripheral ID[4..0] = hex "
1204                                 "%02x %02x %02x %02x %02x",
1205                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1206                                 (int)c_pid1, (int)c_pid0);
1207
1208                         /* Part number interpretations are from Cortex
1209                          * core specs, the CoreSight components TRM
1210                          * (ARM DDI 0314H), CoreSight System Design
1211                          * Guide (ARM DGI 0012D) and ETM specs; also
1212                          * from chip observation (e.g. TI SDTI).
1213                          */
1214                         part_num = (c_pid0 & 0xff);
1215                         part_num |= (c_pid1 & 0x0f) << 8;
1216                         switch (part_num) {
1217                         case 0x000:
1218                                 type = "Cortex-M3 NVIC";
1219                                 full = "(Interrupt Controller)";
1220                                 break;
1221                         case 0x001:
1222                                 type = "Cortex-M3 ITM";
1223                                 full = "(Instrumentation Trace Module)";
1224                                 break;
1225                         case 0x002:
1226                                 type = "Cortex-M3 DWT";
1227                                 full = "(Data Watchpoint and Trace)";
1228                                 break;
1229                         case 0x003:
1230                                 type = "Cortex-M3 FBP";
1231                                 full = "(Flash Patch and Breakpoint)";
1232                                 break;
1233                         case 0x008:
1234                                 type = "Cortex-M0 SCS";
1235                                 full = "(System Control Space)";
1236                                 break;
1237                         case 0x00a:
1238                                 type = "Cortex-M0 DWT";
1239                                 full = "(Data Watchpoint and Trace)";
1240                                 break;
1241                         case 0x00b:
1242                                 type = "Cortex-M0 BPU";
1243                                 full = "(Breakpoint Unit)";
1244                                 break;
1245                         case 0x00c:
1246                                 type = "Cortex-M4 SCS";
1247                                 full = "(System Control Space)";
1248                                 break;
1249                         case 0x00d:
1250                                 type = "CoreSight ETM11";
1251                                 full = "(Embedded Trace)";
1252                                 break;
1253                         /* case 0x113: what? */
1254                         case 0x120:             /* from OMAP3 memmap */
1255                                 type = "TI SDTI";
1256                                 full = "(System Debug Trace Interface)";
1257                                 break;
1258                         case 0x343:             /* from OMAP3 memmap */
1259                                 type = "TI DAPCTL";
1260                                 full = "";
1261                                 break;
1262                         case 0x906:
1263                                 type = "Coresight CTI";
1264                                 full = "(Cross Trigger)";
1265                                 break;
1266                         case 0x907:
1267                                 type = "Coresight ETB";
1268                                 full = "(Trace Buffer)";
1269                                 break;
1270                         case 0x908:
1271                                 type = "Coresight CSTF";
1272                                 full = "(Trace Funnel)";
1273                                 break;
1274                         case 0x910:
1275                                 type = "CoreSight ETM9";
1276                                 full = "(Embedded Trace)";
1277                                 break;
1278                         case 0x912:
1279                                 type = "Coresight TPIU";
1280                                 full = "(Trace Port Interface Unit)";
1281                                 break;
1282                         case 0x913:
1283                                 type = "Coresight ITM";
1284                                 full = "(Instrumentation Trace Macrocell)";
1285                                 break;
1286                         case 0x914:
1287                                 type = "Coresight SWO";
1288                                 full = "(Single Wire Output)";
1289                                 break;
1290                         case 0x917:
1291                                 type = "Coresight HTM";
1292                                 full = "(AHB Trace Macrocell)";
1293                                 break;
1294                         case 0x920:
1295                                 type = "CoreSight ETM11";
1296                                 full = "(Embedded Trace)";
1297                                 break;
1298                         case 0x921:
1299                                 type = "Cortex-A8 ETM";
1300                                 full = "(Embedded Trace)";
1301                                 break;
1302                         case 0x922:
1303                                 type = "Cortex-A8 CTI";
1304                                 full = "(Cross Trigger)";
1305                                 break;
1306                         case 0x923:
1307                                 type = "Cortex-M3 TPIU";
1308                                 full = "(Trace Port Interface Unit)";
1309                                 break;
1310                         case 0x924:
1311                                 type = "Cortex-M3 ETM";
1312                                 full = "(Embedded Trace)";
1313                                 break;
1314                         case 0x925:
1315                                 type = "Cortex-M4 ETM";
1316                                 full = "(Embedded Trace)";
1317                                 break;
1318                         case 0x930:
1319                                 type = "Cortex-R4 ETM";
1320                                 full = "(Embedded Trace)";
1321                                 break;
1322                         case 0x950:
1323                                 type = "CoreSight Component";
1324                                 full = "(unidentified Cortex-A9 component)";
1325                                 break;
1326                         case 0x961:
1327                                 type = "CoreSight TMC";
1328                                 full = "(Trace Memory Controller)";
1329                                 break;
1330                         case 0x962:
1331                                 type = "CoreSight STM";
1332                                 full = "(System Trace Macrocell)";
1333                                 break;
1334                         case 0x9a0:
1335                                 type = "CoreSight PMU";
1336                                 full = "(Performance Monitoring Unit)";
1337                                 break;
1338                         case 0x9a1:
1339                                 type = "Cortex-M4 TPUI";
1340                                 full = "(Trace Port Interface Unit)";
1341                                 break;
1342                         case 0x9a5:
1343                                 type = "Cortex-A5 ETM";
1344                                 full = "(Embedded Trace)";
1345                                 break;
1346                         case 0xc05:
1347                                 type = "Cortex-A5 Debug";
1348                                 full = "(Debug Unit)";
1349                                 break;
1350                         case 0xc08:
1351                                 type = "Cortex-A8 Debug";
1352                                 full = "(Debug Unit)";
1353                                 break;
1354                         case 0xc09:
1355                                 type = "Cortex-A9 Debug";
1356                                 full = "(Debug Unit)";
1357                                 break;
1358                         case 0x4af:
1359                                 type = "Cortex-A15 Debug";
1360                                 full = "(Debug Unit)";
1361                                 break;
1362                         default:
1363                                 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1364                                 type = "-*- unrecognized -*-";
1365                                 full = "";
1366                                 break;
1367                         }
1368                         command_print(cmd_ctx, "\t\tPart is %s %s",
1369                                         type, full);
1370
1371                         /* ROM Table? */
1372                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1373                                 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1374                                 if (retval != ERROR_OK)
1375                                         return retval;
1376                         }
1377                 } else {
1378                         if (romentry)
1379                                 command_print(cmd_ctx, "\t\tComponent not present");
1380                         else
1381                                 break;
1382                 }
1383         }
1384         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1385         return ERROR_OK;
1386 }
1387
1388 static int dap_info_command(struct command_context *cmd_ctx,
1389                 struct adiv5_ap *ap)
1390 {
1391         int retval;
1392         uint32_t dbgbase, apid;
1393         int romtable_present = 0;
1394         uint8_t mem_ap;
1395
1396         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1397         retval = dap_get_debugbase(ap, &dbgbase, &apid);
1398         if (retval != ERROR_OK)
1399                 return retval;
1400
1401         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1402         if (apid == 0) {
1403                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1404                 return ERROR_FAIL;
1405         }
1406
1407         switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1408         case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1409                 command_print(cmd_ctx, "\tType is JTAG-AP");
1410                 break;
1411         case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1412                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1413                 break;
1414         case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1415                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1416                 break;
1417         case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1418                 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1419                 break;
1420         default:
1421                 command_print(cmd_ctx, "\tUnknown AP type");
1422                 break;
1423         }
1424
1425         /* NOTE: a MEM-AP may have a single CoreSight component that's
1426          * not a ROM table ... or have no such components at all.
1427          */
1428         mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1429         if (mem_ap) {
1430                 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1431
1432                 romtable_present = dbgbase != 0xFFFFFFFF;
1433                 if (romtable_present)
1434                         dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1435                 else
1436                         command_print(cmd_ctx, "\tNo ROM table present");
1437         }
1438
1439         return ERROR_OK;
1440 }
1441
1442 COMMAND_HANDLER(handle_dap_info_command)
1443 {
1444         struct target *target = get_current_target(CMD_CTX);
1445         struct arm *arm = target_to_arm(target);
1446         struct adiv5_dap *dap = arm->dap;
1447         uint32_t apsel;
1448
1449         switch (CMD_ARGC) {
1450         case 0:
1451                 apsel = dap->apsel;
1452                 break;
1453         case 1:
1454                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1455                 if (apsel >= 256)
1456                         return ERROR_COMMAND_SYNTAX_ERROR;
1457                 break;
1458         default:
1459                 return ERROR_COMMAND_SYNTAX_ERROR;
1460         }
1461
1462         return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1463 }
1464
1465 COMMAND_HANDLER(dap_baseaddr_command)
1466 {
1467         struct target *target = get_current_target(CMD_CTX);
1468         struct arm *arm = target_to_arm(target);
1469         struct adiv5_dap *dap = arm->dap;
1470
1471         uint32_t apsel, baseaddr;
1472         int retval;
1473
1474         switch (CMD_ARGC) {
1475         case 0:
1476                 apsel = dap->apsel;
1477                 break;
1478         case 1:
1479                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1480                 /* AP address is in bits 31:24 of DP_SELECT */
1481                 if (apsel >= 256)
1482                         return ERROR_COMMAND_SYNTAX_ERROR;
1483                 break;
1484         default:
1485                 return ERROR_COMMAND_SYNTAX_ERROR;
1486         }
1487
1488         dap_ap_select(dap, apsel);
1489
1490         /* NOTE:  assumes we're talking to a MEM-AP, which
1491          * has a base address.  There are other kinds of AP,
1492          * though they're not common for now.  This should
1493          * use the ID register to verify it's a MEM-AP.
1494          */
1495         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1496         if (retval != ERROR_OK)
1497                 return retval;
1498         retval = dap_run(dap);
1499         if (retval != ERROR_OK)
1500                 return retval;
1501
1502         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1503
1504         return retval;
1505 }
1506
1507 COMMAND_HANDLER(dap_memaccess_command)
1508 {
1509         struct target *target = get_current_target(CMD_CTX);
1510         struct arm *arm = target_to_arm(target);
1511         struct adiv5_dap *dap = arm->dap;
1512
1513         uint32_t memaccess_tck;
1514
1515         switch (CMD_ARGC) {
1516         case 0:
1517                 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1518                 break;
1519         case 1:
1520                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1521                 break;
1522         default:
1523                 return ERROR_COMMAND_SYNTAX_ERROR;
1524         }
1525         dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1526
1527         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1528                         dap->ap[dap->apsel].memaccess_tck);
1529
1530         return ERROR_OK;
1531 }
1532
1533 COMMAND_HANDLER(dap_apsel_command)
1534 {
1535         struct target *target = get_current_target(CMD_CTX);
1536         struct arm *arm = target_to_arm(target);
1537         struct adiv5_dap *dap = arm->dap;
1538
1539         uint32_t apsel, apid;
1540         int retval;
1541
1542         switch (CMD_ARGC) {
1543         case 0:
1544                 apsel = dap->apsel;
1545                 break;
1546         case 1:
1547                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1548                 /* AP address is in bits 31:24 of DP_SELECT */
1549                 if (apsel >= 256)
1550                         return ERROR_COMMAND_SYNTAX_ERROR;
1551                 break;
1552         default:
1553                 return ERROR_COMMAND_SYNTAX_ERROR;
1554         }
1555
1556         dap->apsel = apsel;
1557         dap_ap_select(dap, apsel);
1558
1559         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1560         if (retval != ERROR_OK)
1561                 return retval;
1562         retval = dap_run(dap);
1563         if (retval != ERROR_OK)
1564                 return retval;
1565
1566         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1567                         apsel, apid);
1568
1569         return retval;
1570 }
1571
1572 COMMAND_HANDLER(dap_apcsw_command)
1573 {
1574         struct target *target = get_current_target(CMD_CTX);
1575         struct arm *arm = target_to_arm(target);
1576         struct adiv5_dap *dap = arm->dap;
1577
1578         uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1579
1580         switch (CMD_ARGC) {
1581         case 0:
1582                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1583                         (dap->apsel), apcsw);
1584                 break;
1585         case 1:
1586                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1587                 /* AP address is in bits 31:24 of DP_SELECT */
1588                 if (sprot > 1)
1589                         return ERROR_COMMAND_SYNTAX_ERROR;
1590                 if (sprot)
1591                         apcsw |= CSW_SPROT;
1592                 else
1593                         apcsw &= ~CSW_SPROT;
1594                 break;
1595         default:
1596                 return ERROR_COMMAND_SYNTAX_ERROR;
1597         }
1598         dap->ap[dap->apsel].csw_default = apcsw;
1599
1600         return 0;
1601 }
1602
1603
1604
1605 COMMAND_HANDLER(dap_apid_command)
1606 {
1607         struct target *target = get_current_target(CMD_CTX);
1608         struct arm *arm = target_to_arm(target);
1609         struct adiv5_dap *dap = arm->dap;
1610
1611         uint32_t apsel, apid;
1612         int retval;
1613
1614         switch (CMD_ARGC) {
1615         case 0:
1616                 apsel = dap->apsel;
1617                 break;
1618         case 1:
1619                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1620                 /* AP address is in bits 31:24 of DP_SELECT */
1621                 if (apsel >= 256)
1622                         return ERROR_COMMAND_SYNTAX_ERROR;
1623                 break;
1624         default:
1625                 return ERROR_COMMAND_SYNTAX_ERROR;
1626         }
1627
1628         dap_ap_select(dap, apsel);
1629
1630         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1631         if (retval != ERROR_OK)
1632                 return retval;
1633         retval = dap_run(dap);
1634         if (retval != ERROR_OK)
1635                 return retval;
1636
1637         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1638
1639         return retval;
1640 }
1641
1642 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1643 {
1644         struct target *target = get_current_target(CMD_CTX);
1645         struct arm *arm = target_to_arm(target);
1646         struct adiv5_dap *dap = arm->dap;
1647
1648         uint32_t enable = dap->ti_be_32_quirks;
1649
1650         switch (CMD_ARGC) {
1651         case 0:
1652                 break;
1653         case 1:
1654                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1655                 if (enable > 1)
1656                         return ERROR_COMMAND_SYNTAX_ERROR;
1657                 break;
1658         default:
1659                 return ERROR_COMMAND_SYNTAX_ERROR;
1660         }
1661         dap->ti_be_32_quirks = enable;
1662         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1663                 enable ? "enabled" : "disabled");
1664
1665         return 0;
1666 }
1667
1668 static const struct command_registration dap_commands[] = {
1669         {
1670                 .name = "info",
1671                 .handler = handle_dap_info_command,
1672                 .mode = COMMAND_EXEC,
1673                 .help = "display ROM table for MEM-AP "
1674                         "(default currently selected AP)",
1675                 .usage = "[ap_num]",
1676         },
1677         {
1678                 .name = "apsel",
1679                 .handler = dap_apsel_command,
1680                 .mode = COMMAND_EXEC,
1681                 .help = "Set the currently selected AP (default 0) "
1682                         "and display the result",
1683                 .usage = "[ap_num]",
1684         },
1685         {
1686                 .name = "apcsw",
1687                 .handler = dap_apcsw_command,
1688                 .mode = COMMAND_EXEC,
1689                 .help = "Set csw access bit ",
1690                 .usage = "[sprot]",
1691         },
1692
1693         {
1694                 .name = "apid",
1695                 .handler = dap_apid_command,
1696                 .mode = COMMAND_EXEC,
1697                 .help = "return ID register from AP "
1698                         "(default currently selected AP)",
1699                 .usage = "[ap_num]",
1700         },
1701         {
1702                 .name = "baseaddr",
1703                 .handler = dap_baseaddr_command,
1704                 .mode = COMMAND_EXEC,
1705                 .help = "return debug base address from MEM-AP "
1706                         "(default currently selected AP)",
1707                 .usage = "[ap_num]",
1708         },
1709         {
1710                 .name = "memaccess",
1711                 .handler = dap_memaccess_command,
1712                 .mode = COMMAND_EXEC,
1713                 .help = "set/get number of extra tck for MEM-AP memory "
1714                         "bus access [0-255]",
1715                 .usage = "[cycles]",
1716         },
1717         {
1718                 .name = "ti_be_32_quirks",
1719                 .handler = dap_ti_be_32_quirks_command,
1720                 .mode = COMMAND_CONFIG,
1721                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1722                 .usage = "[enable]",
1723         },
1724         COMMAND_REGISTRATION_DONE
1725 };
1726
1727 const struct command_registration dap_command_handlers[] = {
1728         {
1729                 .name = "dap",
1730                 .mode = COMMAND_EXEC,
1731                 .help = "DAP command group",
1732                 .usage = "",
1733                 .chain = dap_commands,
1734         },
1735         COMMAND_REGISTRATION_DONE
1736 };