1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap->ap_bank_value = -1;
119 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
121 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
122 dap->ap[dap_ap_get_select(dap)].csw_default;
124 if (csw != dap->ap[dap_ap_get_select(dap)].csw_value) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
127 if (retval != ERROR_OK)
129 dap->ap[dap_ap_get_select(dap)].csw_value = csw;
134 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
136 if (tar != dap->ap[dap_ap_get_select(dap)].tar_value ||
137 (dap->ap[dap_ap_get_select(dap)].csw_value & CSW_ADDRINC_MASK)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
140 if (retval != ERROR_OK)
142 dap->ap[dap_ap_get_select(dap)].tar_value = tar;
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
156 * @todo Rename to reflect it being specifically a MEM-AP function.
158 * @param dap The DAP connected to the MEM-AP.
159 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
160 * matches the cached value, the register is not changed.
161 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
162 * matches the cached address, the register is not changed.
164 * @return ERROR_OK if the transaction was properly queued, else a fault code.
166 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
169 retval = dap_setup_accessport_csw(dap, csw);
170 if (retval != ERROR_OK)
172 retval = dap_setup_accessport_tar(dap, tar);
173 if (retval != ERROR_OK)
179 * Asynchronous (queued) read of a word from memory or a system register.
181 * @param dap The DAP connected to the MEM-AP performing the read.
182 * @param address Address of the 32-bit word to read; it must be
183 * readable by the currently selected MEM-AP.
184 * @param value points to where the word will be stored when the
185 * transaction queue is flushed (assuming no errors).
187 * @return ERROR_OK for success. Otherwise a fault code.
189 static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
194 /* Use banked addressing (REG_BDx) to avoid some link traffic
195 * (updating TAR) when reading several consecutive addresses.
197 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
198 address & 0xFFFFFFF0);
199 if (retval != ERROR_OK)
202 return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value);
206 * Synchronous read of a word from memory or a system register.
207 * As a side effect, this flushes any queued transactions.
209 * @param dap The DAP connected to the MEM-AP performing the read.
210 * @param address Address of the 32-bit word to read; it must be
211 * readable by the currently selected MEM-AP.
212 * @param value points to where the result will be stored.
214 * @return ERROR_OK for success; *value holds the result.
215 * Otherwise a fault code.
217 static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
222 retval = mem_ap_read_u32(dap, address, value);
223 if (retval != ERROR_OK)
230 * Asynchronous (queued) write of a word to memory or a system register.
232 * @param dap The DAP connected to the MEM-AP.
233 * @param address Address to be written; it must be writable by
234 * the currently selected MEM-AP.
235 * @param value Word that will be written to the address when transaction
236 * queue is flushed (assuming no errors).
238 * @return ERROR_OK for success. Otherwise a fault code.
240 static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
245 /* Use banked addressing (REG_BDx) to avoid some link traffic
246 * (updating TAR) when writing several consecutive addresses.
248 retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
249 address & 0xFFFFFFF0);
250 if (retval != ERROR_OK)
253 return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC),
258 * Synchronous write of a word to memory or a system register.
259 * As a side effect, this flushes any queued transactions.
261 * @param dap The DAP connected to the MEM-AP.
262 * @param address Address to be written; it must be writable by
263 * the currently selected MEM-AP.
264 * @param value Word that will be written.
266 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
268 static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
271 int retval = mem_ap_write_u32(dap, address, value);
273 if (retval != ERROR_OK)
280 * Synchronous write of a block of memory, using a specific access size.
282 * @param dap The DAP connected to the MEM-AP.
283 * @param buffer The data buffer to write. No particular alignment is assumed.
284 * @param size Which access size to use, in bytes. 1, 2 or 4.
285 * @param count The number of writes to do (in size units, not bytes).
286 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
287 * @param addrinc Whether the target address should be increased for each write or not. This
288 * should normally be true, except when writing to e.g. a FIFO.
289 * @return ERROR_OK on success, otherwise an error code.
291 static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
292 uint32_t address, bool addrinc)
294 struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
295 size_t nbytes = size * count;
296 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
301 /* TI BE-32 Quirks mode:
302 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
303 * size write address bytes written in order
304 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
305 * 2 TAR ^ 2 (val >> 8), (val)
307 * For example, if you attempt to write a single byte to address 0, the processor
308 * will actually write a byte to address 3.
310 * To make writes of size < 4 work as expected, we xor a value with the address before
311 * setting the TAP, and we set the TAP after every transfer rather then relying on
312 * address increment. */
315 csw_size = CSW_32BIT;
317 } else if (size == 2) {
318 csw_size = CSW_16BIT;
319 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
320 } else if (size == 1) {
322 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
324 return ERROR_TARGET_UNALIGNED_ACCESS;
327 if (ap->unaligned_access_bad && (address % size != 0))
328 return ERROR_TARGET_UNALIGNED_ACCESS;
330 retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
331 if (retval != ERROR_OK)
335 uint32_t this_size = size;
337 /* Select packed transfer if possible */
338 if (addrinc && ap->packed_transfers && nbytes >= 4
339 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
341 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
343 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
346 if (retval != ERROR_OK)
349 /* How many source bytes each transfer will consume, and their location in the DRW,
350 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
351 uint32_t outvalue = 0;
352 if (dap->ti_be_32_quirks) {
355 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
356 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
357 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
358 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
361 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
362 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
365 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
371 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
372 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
374 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
376 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
382 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
383 if (retval != ERROR_OK)
386 /* Rewrite TAR if it wrapped or we're xoring addresses */
387 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
388 retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
389 if (retval != ERROR_OK)
394 /* REVISIT: Might want to have a queued version of this function that does not run. */
395 if (retval == ERROR_OK)
396 retval = dap_run(dap);
398 if (retval != ERROR_OK) {
400 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
401 && dap_run(dap) == ERROR_OK)
402 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
404 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
411 * Synchronous read of a block of memory, using a specific access size.
413 * @param dap The DAP connected to the MEM-AP.
414 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
415 * @param size Which access size to use, in bytes. 1, 2 or 4.
416 * @param count The number of reads to do (in size units, not bytes).
417 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
418 * @param addrinc Whether the target address should be increased after each read or not. This
419 * should normally be true, except when reading from e.g. a FIFO.
420 * @return ERROR_OK on success, otherwise an error code.
422 static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
423 uint32_t adr, bool addrinc)
425 struct adiv5_ap *ap = &dap->ap[dap_ap_get_select(dap)];
426 size_t nbytes = size * count;
427 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
429 uint32_t address = adr;
432 /* TI BE-32 Quirks mode:
433 * Reads on big-endian TMS570 behave strangely differently than writes.
434 * They read from the physical address requested, but with DRW byte-reversed.
435 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
436 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
440 csw_size = CSW_32BIT;
442 csw_size = CSW_16BIT;
446 return ERROR_TARGET_UNALIGNED_ACCESS;
448 if (ap->unaligned_access_bad && (adr % size != 0))
449 return ERROR_TARGET_UNALIGNED_ACCESS;
451 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
452 * over-allocation if packed transfers are going to be used, but determining the real need at
453 * this point would be messy. */
454 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
455 uint32_t *read_ptr = read_buf;
456 if (read_buf == NULL) {
457 LOG_ERROR("Failed to allocate read buffer");
461 retval = dap_setup_accessport_tar(dap, address);
462 if (retval != ERROR_OK) {
467 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
468 * useful bytes it contains, and their location in the word, depends on the type of transfer
471 uint32_t this_size = size;
473 /* Select packed transfer if possible */
474 if (addrinc && ap->packed_transfers && nbytes >= 4
475 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
477 retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
479 retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
481 if (retval != ERROR_OK)
484 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
485 if (retval != ERROR_OK)
489 address += this_size;
491 /* Rewrite TAR if it wrapped */
492 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
493 retval = dap_setup_accessport_tar(dap, address);
494 if (retval != ERROR_OK)
499 if (retval == ERROR_OK)
500 retval = dap_run(dap);
504 nbytes = size * count;
507 /* If something failed, read TAR to find out how much data was successfully read, so we can
508 * at least give the caller what we have. */
509 if (retval != ERROR_OK) {
511 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
512 && dap_run(dap) == ERROR_OK) {
513 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
514 if (nbytes > tar - address)
515 nbytes = tar - address;
517 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
522 /* Replay loop to populate caller's buffer from the correct word and byte lane */
524 uint32_t this_size = size;
526 if (addrinc && ap->packed_transfers && nbytes >= 4
527 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
531 if (dap->ti_be_32_quirks) {
534 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
535 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
537 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
539 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
544 *buffer++ = *read_ptr >> 8 * (address++ & 3);
545 *buffer++ = *read_ptr >> 8 * (address++ & 3);
547 *buffer++ = *read_ptr >> 8 * (address++ & 3);
549 *buffer++ = *read_ptr >> 8 * (address++ & 3);
561 /*--------------------------------------------------------------------*/
562 /* Wrapping function with selection of AP */
563 /*--------------------------------------------------------------------*/
564 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
565 uint32_t address, uint32_t *value)
567 dap_ap_select(swjdp, ap);
568 return mem_ap_read_u32(swjdp, address, value);
571 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
572 uint32_t address, uint32_t value)
574 dap_ap_select(swjdp, ap);
575 return mem_ap_write_u32(swjdp, address, value);
578 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
579 uint32_t address, uint32_t *value)
581 dap_ap_select(swjdp, ap);
582 return mem_ap_read_atomic_u32(swjdp, address, value);
585 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
586 uint32_t address, uint32_t value)
588 dap_ap_select(swjdp, ap);
589 return mem_ap_write_atomic_u32(swjdp, address, value);
592 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
593 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
595 dap_ap_select(swjdp, ap);
596 return mem_ap_read(swjdp, buffer, size, count, address, true);
599 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
600 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
602 dap_ap_select(swjdp, ap);
603 return mem_ap_write(swjdp, buffer, size, count, address, true);
606 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
607 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
609 dap_ap_select(swjdp, ap);
610 return mem_ap_read(swjdp, buffer, size, count, address, false);
613 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
614 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
616 dap_ap_select(swjdp, ap);
617 return mem_ap_write(swjdp, buffer, size, count, address, false);
620 /*--------------------------------------------------------------------------*/
623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
625 /* FIXME don't import ... just initialize as
626 * part of DAP transport setup
628 extern const struct dap_ops jtag_dp_ops;
630 /*--------------------------------------------------------------------------*/
635 struct adiv5_dap *dap_init(void)
637 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
639 /* Set up with safe defaults */
640 for (i = 0; i <= 255; i++) {
641 /* memaccess_tck max is 255 */
642 dap->ap[i].memaccess_tck = 255;
643 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
644 dap->ap[i].tar_autoincr_block = (1<<10);
650 * Initialize a DAP. This sets up the power domains, prepares the DP
651 * for further use, and arranges to use AP #0 for all AP operations
652 * until dap_ap-select() changes that policy.
654 * @param dap The DAP being initialized.
656 * @todo Rename this. We also need an initialization scheme which account
657 * for SWD transports not just JTAG; that will need to address differences
658 * in layering. (JTAG is useful without any debug target; but not SWD.)
659 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
661 int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
663 /* check that we support packed transfers */
666 struct adiv5_ap *ap = &dap->ap[apsel];
670 /* JTAG-DP or SWJ-DP, in JTAG mode
671 * ... for SWD mode this is patched as part
675 dap->ops = &jtag_dp_ops;
677 /* Default MEM-AP setup.
679 * REVISIT AP #0 may be an inappropriate default for this.
680 * Should we probe, or take a hint from the caller?
681 * Presumably we can ignore the possibility of multiple APs.
683 dap->ap_current = -1;
684 dap_ap_select(dap, apsel);
685 dap->last_read = NULL;
687 for (size_t i = 0; i < 10; i++) {
688 /* DP initialization */
690 dap->dp_bank_value = 0;
692 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
693 if (retval != ERROR_OK)
696 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
697 if (retval != ERROR_OK)
700 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
701 if (retval != ERROR_OK)
704 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
705 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
706 if (retval != ERROR_OK)
709 /* Check that we have debug power domains activated */
710 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
711 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
712 CDBGPWRUPACK, CDBGPWRUPACK,
713 DAP_POWER_DOMAIN_TIMEOUT);
714 if (retval != ERROR_OK)
717 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
718 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
719 CSYSPWRUPACK, CSYSPWRUPACK,
720 DAP_POWER_DOMAIN_TIMEOUT);
721 if (retval != ERROR_OK)
724 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
725 if (retval != ERROR_OK)
727 /* With debug power on we can activate OVERRUN checking */
728 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
729 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
730 if (retval != ERROR_OK)
732 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
733 if (retval != ERROR_OK)
736 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
737 if (retval != ERROR_OK)
740 retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
741 if (retval != ERROR_OK)
744 retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
745 if (retval != ERROR_OK)
748 retval = dap_run(dap);
749 if (retval != ERROR_OK)
755 if (retval != ERROR_OK)
758 if (csw & CSW_ADDRINC_PACKED)
759 ap->packed_transfers = true;
761 ap->packed_transfers = false;
763 /* Packed transfers on TI BE-32 processors do not work correctly in
765 if (dap->ti_be_32_quirks)
766 ap->packed_transfers = false;
768 LOG_DEBUG("MEM_AP Packed Transfers: %s",
769 ap->packed_transfers ? "enabled" : "disabled");
771 /* The ARM ADI spec leaves implementation-defined whether unaligned
772 * memory accesses work, only work partially, or cause a sticky error.
773 * On TI BE-32 processors, reads seem to return garbage in some bytes
774 * and unaligned writes seem to cause a sticky error.
775 * TODO: it would be nice to have a way to detect whether unaligned
776 * operations are supported on other processors. */
777 ap->unaligned_access_bad = dap->ti_be_32_quirks;
779 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
780 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
785 /* CID interpretation -- see ARM IHI 0029B section 3
786 * and ARM IHI 0031A table 13-3.
788 static const char *class_description[16] = {
789 "Reserved", "ROM table", "Reserved", "Reserved",
790 "Reserved", "Reserved", "Reserved", "Reserved",
791 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
792 "Reserved", "OptimoDE DESS",
793 "Generic IP component", "PrimeCell or System component"
796 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
798 return cid3 == 0xb1 && cid2 == 0x05
799 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
803 * This function checks the ID for each access port to find the requested Access Port type
805 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
809 /* Maximum AP number is 255 since the SELECT register is 8 bits */
810 for (ap = 0; ap <= 255; ap++) {
812 /* read the IDR register of the Access Port */
814 dap_ap_select(dap, ap);
816 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
817 if (retval != ERROR_OK)
820 retval = dap_run(dap);
824 * 27-24 : JEDEC bank (0x4 for ARM)
825 * 23-17 : JEDEC code (0x3B for ARM)
828 * 7-0 : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
831 /* Reading register for a non-existant AP should not cause an error,
832 * but just to be sure, try to continue searching if an error does happen.
834 if ((retval == ERROR_OK) && /* Register read success */
835 ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
836 ((id_val & 0xFF) == type_to_find)) { /* type matches*/
838 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
839 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
840 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
841 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
849 LOG_DEBUG("No %s found",
850 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
851 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
852 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
856 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
857 uint32_t *dbgbase, uint32_t *apid)
862 /* AP address is in bits 31:24 of DP_SELECT */
864 return ERROR_COMMAND_SYNTAX_ERROR;
866 ap_old = dap_ap_get_select(dap);
867 dap_ap_select(dap, ap);
869 retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
870 if (retval != ERROR_OK)
872 retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
873 if (retval != ERROR_OK)
875 retval = dap_run(dap);
876 if (retval != ERROR_OK)
879 dap_ap_select(dap, ap_old);
884 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
885 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
888 uint32_t romentry, entry_offset = 0, component_base, devtype;
892 return ERROR_COMMAND_SYNTAX_ERROR;
895 ap_old = dap_ap_get_select(dap);
896 dap_ap_select(dap, ap);
899 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
900 entry_offset, &romentry);
901 if (retval != ERROR_OK)
904 component_base = (dbgbase & 0xFFFFF000)
905 + (romentry & 0xFFFFF000);
907 if (romentry & 0x1) {
909 retval = mem_ap_read_atomic_u32(dap, component_base | 0xff4, &c_cid1);
910 if (retval != ERROR_OK) {
911 LOG_ERROR("Can't read component with base address 0x%" PRIx32
912 ", the corresponding core might be turned off", component_base);
915 if (((c_cid1 >> 4) & 0x0f) == 1) {
916 retval = dap_lookup_cs_component(dap, ap, component_base,
918 if (retval == ERROR_OK)
920 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
924 retval = mem_ap_read_atomic_u32(dap,
925 (component_base & 0xfffff000) | 0xfcc,
927 if (retval != ERROR_OK)
929 if ((devtype & 0xff) == type) {
931 *addr = component_base;
938 } while (romentry > 0);
940 dap_ap_select(dap, ap_old);
943 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
948 static int dap_rom_display(struct command_context *cmd_ctx,
949 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
952 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
953 uint16_t entry_offset;
957 command_print(cmd_ctx, "\tTables too deep");
962 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
964 /* bit 16 of apid indicates a memory access port */
966 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
968 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
970 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
971 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
972 if (retval != ERROR_OK)
974 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
975 if (retval != ERROR_OK)
977 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
978 if (retval != ERROR_OK)
980 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
981 if (retval != ERROR_OK)
983 retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
984 if (retval != ERROR_OK)
986 retval = dap_run(dap);
987 if (retval != ERROR_OK)
990 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
991 command_print(cmd_ctx, "\t%sCID3 0x%02x"
996 (unsigned)cid3, (unsigned)cid2,
997 (unsigned)cid1, (unsigned)cid0);
999 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1001 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1003 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1004 for (entry_offset = 0; ; entry_offset += 4) {
1005 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1006 if (retval != ERROR_OK)
1008 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1009 tabs, entry_offset, romentry);
1010 if (romentry & 0x01) {
1011 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1012 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1013 uint32_t component_base;
1015 const char *type, *full;
1017 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1019 /* IDs are in last 4K section */
1020 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1021 if (retval != ERROR_OK) {
1022 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1023 ", the corresponding core might be turned off", tabs, component_base);
1027 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1028 if (retval != ERROR_OK)
1031 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1032 if (retval != ERROR_OK)
1035 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1036 if (retval != ERROR_OK)
1039 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1040 if (retval != ERROR_OK)
1044 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1045 if (retval != ERROR_OK)
1048 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1049 if (retval != ERROR_OK)
1052 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1053 if (retval != ERROR_OK)
1056 retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1057 if (retval != ERROR_OK)
1061 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1062 "start address 0x%" PRIx32, component_base,
1063 /* component may take multiple 4K pages */
1064 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1065 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1066 (uint8_t)((c_cid1 >> 4) & 0xf),
1067 /* See ARM IHI 0029B Table 3-3 */
1068 class_description[(c_cid1 >> 4) & 0xf]);
1070 /* CoreSight component? */
1071 if (((c_cid1 >> 4) & 0x0f) == 9) {
1074 const char *major = "Reserved", *subtype = "Reserved";
1076 retval = mem_ap_read_atomic_u32(dap,
1077 (component_base & 0xfffff000) | 0xfcc,
1079 if (retval != ERROR_OK)
1081 minor = (devtype >> 4) & 0x0f;
1082 switch (devtype & 0x0f) {
1084 major = "Miscellaneous";
1090 subtype = "Validation component";
1095 major = "Trace Sink";
1112 major = "Trace Link";
1118 subtype = "Funnel, router";
1124 subtype = "FIFO, buffer";
1129 major = "Trace Source";
1135 subtype = "Processor";
1141 subtype = "Engine/Coprocessor";
1147 subtype = "Software";
1152 major = "Debug Control";
1158 subtype = "Trigger Matrix";
1161 subtype = "Debug Auth";
1164 subtype = "Power Requestor";
1169 major = "Debug Logic";
1175 subtype = "Processor";
1181 subtype = "Engine/Coprocessor";
1192 major = "Perfomance Monitor";
1198 subtype = "Processor";
1204 subtype = "Engine/Coprocessor";
1215 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1216 (uint8_t)(devtype & 0xff),
1218 /* REVISIT also show 0xfc8 DevId */
1221 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1222 command_print(cmd_ctx,
1231 command_print(cmd_ctx,
1232 "\t\tPeripheral ID[4..0] = hex "
1233 "%02x %02x %02x %02x %02x",
1234 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1235 (int)c_pid1, (int)c_pid0);
1237 /* Part number interpretations are from Cortex
1238 * core specs, the CoreSight components TRM
1239 * (ARM DDI 0314H), CoreSight System Design
1240 * Guide (ARM DGI 0012D) and ETM specs; also
1241 * from chip observation (e.g. TI SDTI).
1243 part_num = (c_pid0 & 0xff);
1244 part_num |= (c_pid1 & 0x0f) << 8;
1247 type = "Cortex-M3 NVIC";
1248 full = "(Interrupt Controller)";
1251 type = "Cortex-M3 ITM";
1252 full = "(Instrumentation Trace Module)";
1255 type = "Cortex-M3 DWT";
1256 full = "(Data Watchpoint and Trace)";
1259 type = "Cortex-M3 FBP";
1260 full = "(Flash Patch and Breakpoint)";
1263 type = "Cortex-M0 SCS";
1264 full = "(System Control Space)";
1267 type = "Cortex-M0 DWT";
1268 full = "(Data Watchpoint and Trace)";
1271 type = "Cortex-M0 BPU";
1272 full = "(Breakpoint Unit)";
1275 type = "Cortex-M4 SCS";
1276 full = "(System Control Space)";
1279 type = "CoreSight ETM11";
1280 full = "(Embedded Trace)";
1282 /* case 0x113: what? */
1283 case 0x120: /* from OMAP3 memmap */
1285 full = "(System Debug Trace Interface)";
1287 case 0x343: /* from OMAP3 memmap */
1292 type = "Coresight CTI";
1293 full = "(Cross Trigger)";
1296 type = "Coresight ETB";
1297 full = "(Trace Buffer)";
1300 type = "Coresight CSTF";
1301 full = "(Trace Funnel)";
1304 type = "CoreSight ETM9";
1305 full = "(Embedded Trace)";
1308 type = "Coresight TPIU";
1309 full = "(Trace Port Interface Unit)";
1312 type = "Coresight ITM";
1313 full = "(Instrumentation Trace Macrocell)";
1316 type = "Coresight SWO";
1317 full = "(Single Wire Output)";
1320 type = "Coresight HTM";
1321 full = "(AHB Trace Macrocell)";
1324 type = "CoreSight ETM11";
1325 full = "(Embedded Trace)";
1328 type = "Cortex-A8 ETM";
1329 full = "(Embedded Trace)";
1332 type = "Cortex-A8 CTI";
1333 full = "(Cross Trigger)";
1336 type = "Cortex-M3 TPIU";
1337 full = "(Trace Port Interface Unit)";
1340 type = "Cortex-M3 ETM";
1341 full = "(Embedded Trace)";
1344 type = "Cortex-M4 ETM";
1345 full = "(Embedded Trace)";
1348 type = "Cortex-R4 ETM";
1349 full = "(Embedded Trace)";
1352 type = "CoreSight Component";
1353 full = "(unidentified Cortex-A9 component)";
1356 type = "CoreSight TMC";
1357 full = "(Trace Memory Controller)";
1360 type = "CoreSight STM";
1361 full = "(System Trace Macrocell)";
1364 type = "CoreSight PMU";
1365 full = "(Performance Monitoring Unit)";
1368 type = "Cortex-M4 TPUI";
1369 full = "(Trace Port Interface Unit)";
1372 type = "Cortex-A5 ETM";
1373 full = "(Embedded Trace)";
1376 type = "Cortex-A5 Debug";
1377 full = "(Debug Unit)";
1380 type = "Cortex-A8 Debug";
1381 full = "(Debug Unit)";
1384 type = "Cortex-A9 Debug";
1385 full = "(Debug Unit)";
1388 type = "Cortex-A15 Debug";
1389 full = "(Debug Unit)";
1392 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1393 type = "-*- unrecognized -*-";
1397 command_print(cmd_ctx, "\t\tPart is %s %s",
1401 if (((c_cid1 >> 4) & 0x0f) == 1) {
1402 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1403 if (retval != ERROR_OK)
1408 command_print(cmd_ctx, "\t\tComponent not present");
1413 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1417 static int dap_info_command(struct command_context *cmd_ctx,
1418 struct adiv5_dap *dap, int ap)
1421 uint32_t dbgbase, apid;
1422 int romtable_present = 0;
1426 retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1427 if (retval != ERROR_OK)
1430 ap_old = dap_ap_get_select(dap);
1431 dap_ap_select(dap, ap);
1433 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1434 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1435 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1437 switch (apid&0x0F) {
1439 command_print(cmd_ctx, "\tType is JTAG-AP");
1442 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1445 command_print(cmd_ctx, "\tType is MEM-AP APB");
1448 command_print(cmd_ctx, "\tUnknown AP type");
1452 /* NOTE: a MEM-AP may have a single CoreSight component that's
1453 * not a ROM table ... or have no such components at all.
1456 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1458 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1460 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1461 if (romtable_present)
1462 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1464 command_print(cmd_ctx, "\tNo ROM table present");
1465 dap_ap_select(dap, ap_old);
1470 COMMAND_HANDLER(handle_dap_info_command)
1472 struct target *target = get_current_target(CMD_CTX);
1473 struct arm *arm = target_to_arm(target);
1474 struct adiv5_dap *dap = arm->dap;
1482 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1485 return ERROR_COMMAND_SYNTAX_ERROR;
1488 return dap_info_command(CMD_CTX, dap, apsel);
1491 COMMAND_HANDLER(dap_baseaddr_command)
1493 struct target *target = get_current_target(CMD_CTX);
1494 struct arm *arm = target_to_arm(target);
1495 struct adiv5_dap *dap = arm->dap;
1497 uint32_t apsel, baseaddr;
1505 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1506 /* AP address is in bits 31:24 of DP_SELECT */
1508 return ERROR_COMMAND_SYNTAX_ERROR;
1511 return ERROR_COMMAND_SYNTAX_ERROR;
1514 dap_ap_select(dap, apsel);
1516 /* NOTE: assumes we're talking to a MEM-AP, which
1517 * has a base address. There are other kinds of AP,
1518 * though they're not common for now. This should
1519 * use the ID register to verify it's a MEM-AP.
1521 retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1522 if (retval != ERROR_OK)
1524 retval = dap_run(dap);
1525 if (retval != ERROR_OK)
1528 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1533 COMMAND_HANDLER(dap_memaccess_command)
1535 struct target *target = get_current_target(CMD_CTX);
1536 struct arm *arm = target_to_arm(target);
1537 struct adiv5_dap *dap = arm->dap;
1539 uint32_t memaccess_tck;
1543 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1546 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1549 return ERROR_COMMAND_SYNTAX_ERROR;
1551 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1553 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1554 dap->ap[dap->apsel].memaccess_tck);
1559 COMMAND_HANDLER(dap_apsel_command)
1561 struct target *target = get_current_target(CMD_CTX);
1562 struct arm *arm = target_to_arm(target);
1563 struct adiv5_dap *dap = arm->dap;
1565 uint32_t apsel, apid;
1573 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1574 /* AP address is in bits 31:24 of DP_SELECT */
1576 return ERROR_COMMAND_SYNTAX_ERROR;
1579 return ERROR_COMMAND_SYNTAX_ERROR;
1583 dap_ap_select(dap, apsel);
1585 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1586 if (retval != ERROR_OK)
1588 retval = dap_run(dap);
1589 if (retval != ERROR_OK)
1592 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1598 COMMAND_HANDLER(dap_apcsw_command)
1600 struct target *target = get_current_target(CMD_CTX);
1601 struct arm *arm = target_to_arm(target);
1602 struct adiv5_dap *dap = arm->dap;
1604 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1608 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1609 (dap->apsel), apcsw);
1612 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1613 /* AP address is in bits 31:24 of DP_SELECT */
1615 return ERROR_COMMAND_SYNTAX_ERROR;
1619 apcsw &= ~CSW_SPROT;
1622 return ERROR_COMMAND_SYNTAX_ERROR;
1624 dap->ap[dap->apsel].csw_default = apcsw;
1631 COMMAND_HANDLER(dap_apid_command)
1633 struct target *target = get_current_target(CMD_CTX);
1634 struct arm *arm = target_to_arm(target);
1635 struct adiv5_dap *dap = arm->dap;
1637 uint32_t apsel, apid;
1645 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1646 /* AP address is in bits 31:24 of DP_SELECT */
1648 return ERROR_COMMAND_SYNTAX_ERROR;
1651 return ERROR_COMMAND_SYNTAX_ERROR;
1654 dap_ap_select(dap, apsel);
1656 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1657 if (retval != ERROR_OK)
1659 retval = dap_run(dap);
1660 if (retval != ERROR_OK)
1663 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1668 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1670 struct target *target = get_current_target(CMD_CTX);
1671 struct arm *arm = target_to_arm(target);
1672 struct adiv5_dap *dap = arm->dap;
1674 uint32_t enable = dap->ti_be_32_quirks;
1680 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1682 return ERROR_COMMAND_SYNTAX_ERROR;
1685 return ERROR_COMMAND_SYNTAX_ERROR;
1687 dap->ti_be_32_quirks = enable;
1688 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1689 enable ? "enabled" : "disabled");
1694 static const struct command_registration dap_commands[] = {
1697 .handler = handle_dap_info_command,
1698 .mode = COMMAND_EXEC,
1699 .help = "display ROM table for MEM-AP "
1700 "(default currently selected AP)",
1701 .usage = "[ap_num]",
1705 .handler = dap_apsel_command,
1706 .mode = COMMAND_EXEC,
1707 .help = "Set the currently selected AP (default 0) "
1708 "and display the result",
1709 .usage = "[ap_num]",
1713 .handler = dap_apcsw_command,
1714 .mode = COMMAND_EXEC,
1715 .help = "Set csw access bit ",
1721 .handler = dap_apid_command,
1722 .mode = COMMAND_EXEC,
1723 .help = "return ID register from AP "
1724 "(default currently selected AP)",
1725 .usage = "[ap_num]",
1729 .handler = dap_baseaddr_command,
1730 .mode = COMMAND_EXEC,
1731 .help = "return debug base address from MEM-AP "
1732 "(default currently selected AP)",
1733 .usage = "[ap_num]",
1736 .name = "memaccess",
1737 .handler = dap_memaccess_command,
1738 .mode = COMMAND_EXEC,
1739 .help = "set/get number of extra tck for MEM-AP memory "
1740 "bus access [0-255]",
1741 .usage = "[cycles]",
1744 .name = "ti_be_32_quirks",
1745 .handler = dap_ti_be_32_quirks_command,
1746 .mode = COMMAND_CONFIG,
1747 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1748 .usage = "[enable]",
1750 COMMAND_REGISTRATION_DONE
1753 const struct command_registration dap_command_handlers[] = {
1756 .mode = COMMAND_EXEC,
1757 .help = "DAP command group",
1759 .chain = dap_commands,
1761 COMMAND_REGISTRATION_DONE