1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program; if not, write to the *
28 * Free Software Foundation, Inc., *
29 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
30 ***************************************************************************/
34 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
35 * debugging architecture. Compared with previous versions, this includes
36 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
37 * transport, and focusses on memory mapped resources as defined by the
38 * CoreSight architecture.
40 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
41 * basic components: a Debug Port (DP) transporting messages to and from a
42 * debugger, and an Access Port (AP) accessing resources. Three types of DP
43 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
44 * One uses only SWD for communication, and is called SW-DP. The third can
45 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
46 * is used to access memory mapped resources and is called a MEM-AP. Also a
47 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
49 * This programming interface allows DAP pipelined operations through a
50 * transaction queue. This primarily affects AP operations (such as using
51 * a MEM-AP to access memory or registers). If the current transaction has
52 * not finished by the time the next one must begin, and the ORUNDETECT bit
53 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
54 * further AP operations will fail. There are two basic methods to avoid
55 * such overrun errors. One involves polling for status instead of using
56 * transaction piplining. The other involves adding delays to ensure the
57 * AP has enough time to complete one operation before starting the next
58 * one. (For JTAG these delays are controlled by memaccess_tck.)
62 * Relevant specifications from ARM include:
64 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
65 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
67 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
68 * Cortex-M3(tm) TRM, ARM DDI 0337G
75 #include "jtag/interface.h"
77 #include "arm_adi_v5.h"
78 #include <helper/time_support.h>
80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
83 uint32_t tar_block_size(uint32_t address)
84 Return the largest block starting at address that does not cross a tar block size alignment boundary
86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
88 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
91 /***************************************************************************
93 * DP and MEM-AP register access through APACC and DPACC *
95 ***************************************************************************/
98 * Select one of the APs connected to the specified DAP. The
99 * selection is implicitly used with future AP transactions.
100 * This is a NOP if the specified AP is already selected.
103 * @param apsel Number of the AP to (implicitly) use with further
104 * transactions. This normally identifies a MEM-AP.
106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
108 uint32_t new_ap = (ap << 24) & 0xFF000000;
110 if (new_ap != dap->ap_current) {
111 dap->ap_current = new_ap;
112 /* Switching AP invalidates cached values.
113 * Values MUST BE UPDATED BEFORE AP ACCESS.
115 dap->ap_bank_value = -1;
119 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
121 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
124 if (csw != ap->csw_value) {
125 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
126 int retval = dap_queue_ap_write(ap->dap, MEM_AP_REG_CSW, csw);
127 if (retval != ERROR_OK)
134 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
136 if (tar != ap->tar_value ||
137 (ap->csw_value & CSW_ADDRINC_MASK)) {
138 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
139 int retval = dap_queue_ap_write(ap->dap, MEM_AP_REG_TAR, tar);
140 if (retval != ERROR_OK)
148 * Queue transactions setting up transfer parameters for the
149 * currently selected MEM-AP.
151 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
152 * initiate data reads or writes using memory or peripheral addresses.
153 * If the CSW is configured for it, the TAR may be automatically
154 * incremented after each transfer.
156 * @param ap The MEM-AP.
157 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
158 * matches the cached value, the register is not changed.
159 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
160 * matches the cached address, the register is not changed.
162 * @return ERROR_OK if the transaction was properly queued, else a fault code.
164 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
167 retval = mem_ap_setup_csw(ap, csw);
168 if (retval != ERROR_OK)
170 retval = mem_ap_setup_tar(ap, tar);
171 if (retval != ERROR_OK)
177 * Asynchronous (queued) read of a word from memory or a system register.
179 * @param dap The DAP connected to the MEM-AP performing the read.
180 * @param address Address of the 32-bit word to read; it must be
181 * readable by the currently selected MEM-AP.
182 * @param value points to where the word will be stored when the
183 * transaction queue is flushed (assuming no errors).
185 * @return ERROR_OK for success. Otherwise a fault code.
187 static int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
192 /* Use banked addressing (REG_BDx) to avoid some link traffic
193 * (updating TAR) when reading several consecutive addresses.
195 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
196 address & 0xFFFFFFF0);
197 if (retval != ERROR_OK)
200 return dap_queue_ap_read(ap->dap, MEM_AP_REG_BD0 | (address & 0xC), value);
204 * Synchronous read of a word from memory or a system register.
205 * As a side effect, this flushes any queued transactions.
207 * @param dap The DAP connected to the MEM-AP performing the read.
208 * @param address Address of the 32-bit word to read; it must be
209 * readable by the currently selected MEM-AP.
210 * @param value points to where the result will be stored.
212 * @return ERROR_OK for success; *value holds the result.
213 * Otherwise a fault code.
215 static int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
220 retval = mem_ap_read_u32(ap, address, value);
221 if (retval != ERROR_OK)
224 return dap_run(ap->dap);
228 * Asynchronous (queued) write of a word to memory or a system register.
230 * @param dap The DAP connected to the MEM-AP.
231 * @param address Address to be written; it must be writable by
232 * the currently selected MEM-AP.
233 * @param value Word that will be written to the address when transaction
234 * queue is flushed (assuming no errors).
236 * @return ERROR_OK for success. Otherwise a fault code.
238 static int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
243 /* Use banked addressing (REG_BDx) to avoid some link traffic
244 * (updating TAR) when writing several consecutive addresses.
246 retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
247 address & 0xFFFFFFF0);
248 if (retval != ERROR_OK)
251 return dap_queue_ap_write(ap->dap, MEM_AP_REG_BD0 | (address & 0xC),
256 * Synchronous write of a word to memory or a system register.
257 * As a side effect, this flushes any queued transactions.
259 * @param dap The DAP connected to the MEM-AP.
260 * @param address Address to be written; it must be writable by
261 * the currently selected MEM-AP.
262 * @param value Word that will be written.
264 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
266 static int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
269 int retval = mem_ap_write_u32(ap, address, value);
271 if (retval != ERROR_OK)
274 return dap_run(ap->dap);
278 * Synchronous write of a block of memory, using a specific access size.
280 * @param dap The DAP connected to the MEM-AP.
281 * @param buffer The data buffer to write. No particular alignment is assumed.
282 * @param size Which access size to use, in bytes. 1, 2 or 4.
283 * @param count The number of writes to do (in size units, not bytes).
284 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
285 * @param addrinc Whether the target address should be increased for each write or not. This
286 * should normally be true, except when writing to e.g. a FIFO.
287 * @return ERROR_OK on success, otherwise an error code.
289 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
290 uint32_t address, bool addrinc)
292 struct adiv5_dap *dap = ap->dap;
293 size_t nbytes = size * count;
294 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
299 /* TI BE-32 Quirks mode:
300 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
301 * size write address bytes written in order
302 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
303 * 2 TAR ^ 2 (val >> 8), (val)
305 * For example, if you attempt to write a single byte to address 0, the processor
306 * will actually write a byte to address 3.
308 * To make writes of size < 4 work as expected, we xor a value with the address before
309 * setting the TAP, and we set the TAP after every transfer rather then relying on
310 * address increment. */
313 csw_size = CSW_32BIT;
315 } else if (size == 2) {
316 csw_size = CSW_16BIT;
317 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
318 } else if (size == 1) {
320 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
322 return ERROR_TARGET_UNALIGNED_ACCESS;
325 if (ap->unaligned_access_bad && (address % size != 0))
326 return ERROR_TARGET_UNALIGNED_ACCESS;
328 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
329 if (retval != ERROR_OK)
333 uint32_t this_size = size;
335 /* Select packed transfer if possible */
336 if (addrinc && ap->packed_transfers && nbytes >= 4
337 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
339 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
341 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
344 if (retval != ERROR_OK)
347 /* How many source bytes each transfer will consume, and their location in the DRW,
348 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
349 uint32_t outvalue = 0;
350 if (dap->ti_be_32_quirks) {
353 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
354 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
355 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
356 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
359 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
360 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
363 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
369 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
370 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
372 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
374 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
380 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
381 if (retval != ERROR_OK)
384 /* Rewrite TAR if it wrapped or we're xoring addresses */
385 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
386 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
387 if (retval != ERROR_OK)
392 /* REVISIT: Might want to have a queued version of this function that does not run. */
393 if (retval == ERROR_OK)
394 retval = dap_run(dap);
396 if (retval != ERROR_OK) {
398 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
399 && dap_run(dap) == ERROR_OK)
400 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
402 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
409 * Synchronous read of a block of memory, using a specific access size.
411 * @param dap The DAP connected to the MEM-AP.
412 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
413 * @param size Which access size to use, in bytes. 1, 2 or 4.
414 * @param count The number of reads to do (in size units, not bytes).
415 * @param address Address to be read; it must be readable by the currently selected MEM-AP.
416 * @param addrinc Whether the target address should be increased after each read or not. This
417 * should normally be true, except when reading from e.g. a FIFO.
418 * @return ERROR_OK on success, otherwise an error code.
420 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
421 uint32_t adr, bool addrinc)
423 struct adiv5_dap *dap = ap->dap;
424 size_t nbytes = size * count;
425 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
427 uint32_t address = adr;
430 /* TI BE-32 Quirks mode:
431 * Reads on big-endian TMS570 behave strangely differently than writes.
432 * They read from the physical address requested, but with DRW byte-reversed.
433 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
434 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
438 csw_size = CSW_32BIT;
440 csw_size = CSW_16BIT;
444 return ERROR_TARGET_UNALIGNED_ACCESS;
446 if (ap->unaligned_access_bad && (adr % size != 0))
447 return ERROR_TARGET_UNALIGNED_ACCESS;
449 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
450 * over-allocation if packed transfers are going to be used, but determining the real need at
451 * this point would be messy. */
452 uint32_t *read_buf = malloc(count * sizeof(uint32_t));
453 uint32_t *read_ptr = read_buf;
454 if (read_buf == NULL) {
455 LOG_ERROR("Failed to allocate read buffer");
459 retval = mem_ap_setup_tar(ap, address);
460 if (retval != ERROR_OK) {
465 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
466 * useful bytes it contains, and their location in the word, depends on the type of transfer
469 uint32_t this_size = size;
471 /* Select packed transfer if possible */
472 if (addrinc && ap->packed_transfers && nbytes >= 4
473 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
475 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
477 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
479 if (retval != ERROR_OK)
482 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
483 if (retval != ERROR_OK)
487 address += this_size;
489 /* Rewrite TAR if it wrapped */
490 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
491 retval = mem_ap_setup_tar(ap, address);
492 if (retval != ERROR_OK)
497 if (retval == ERROR_OK)
498 retval = dap_run(dap);
502 nbytes = size * count;
505 /* If something failed, read TAR to find out how much data was successfully read, so we can
506 * at least give the caller what we have. */
507 if (retval != ERROR_OK) {
509 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
510 && dap_run(dap) == ERROR_OK) {
511 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
512 if (nbytes > tar - address)
513 nbytes = tar - address;
515 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
520 /* Replay loop to populate caller's buffer from the correct word and byte lane */
522 uint32_t this_size = size;
524 if (addrinc && ap->packed_transfers && nbytes >= 4
525 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
529 if (dap->ti_be_32_quirks) {
532 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
533 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
535 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
537 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
542 *buffer++ = *read_ptr >> 8 * (address++ & 3);
543 *buffer++ = *read_ptr >> 8 * (address++ & 3);
545 *buffer++ = *read_ptr >> 8 * (address++ & 3);
547 *buffer++ = *read_ptr >> 8 * (address++ & 3);
559 /*--------------------------------------------------------------------*/
560 /* Wrapping function with selection of AP */
561 /*--------------------------------------------------------------------*/
562 int mem_ap_sel_read_u32(struct adiv5_ap *ap,
563 uint32_t address, uint32_t *value)
565 dap_ap_select(ap->dap, ap->ap_num);
566 return mem_ap_read_u32(ap, address, value);
569 int mem_ap_sel_write_u32(struct adiv5_ap *ap,
570 uint32_t address, uint32_t value)
572 dap_ap_select(ap->dap, ap->ap_num);
573 return mem_ap_write_u32(ap, address, value);
576 int mem_ap_sel_read_atomic_u32(struct adiv5_ap *ap,
577 uint32_t address, uint32_t *value)
579 dap_ap_select(ap->dap, ap->ap_num);
580 return mem_ap_read_atomic_u32(ap, address, value);
583 int mem_ap_sel_write_atomic_u32(struct adiv5_ap *ap,
584 uint32_t address, uint32_t value)
586 dap_ap_select(ap->dap, ap->ap_num);
587 return mem_ap_write_atomic_u32(ap, address, value);
590 int mem_ap_sel_read_buf(struct adiv5_ap *ap,
591 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
593 dap_ap_select(ap->dap, ap->ap_num);
594 return mem_ap_read(ap, buffer, size, count, address, true);
597 int mem_ap_sel_write_buf(struct adiv5_ap *ap,
598 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
600 dap_ap_select(ap->dap, ap->ap_num);
601 return mem_ap_write(ap, buffer, size, count, address, true);
604 int mem_ap_sel_read_buf_noincr(struct adiv5_ap *ap,
605 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
607 dap_ap_select(ap->dap, ap->ap_num);
608 return mem_ap_read(ap, buffer, size, count, address, false);
611 int mem_ap_sel_write_buf_noincr(struct adiv5_ap *ap,
612 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
614 dap_ap_select(ap->dap, ap->ap_num);
615 return mem_ap_write(ap, buffer, size, count, address, false);
618 /*--------------------------------------------------------------------------*/
621 #define DAP_POWER_DOMAIN_TIMEOUT (10)
623 /* FIXME don't import ... just initialize as
624 * part of DAP transport setup
626 extern const struct dap_ops jtag_dp_ops;
628 /*--------------------------------------------------------------------------*/
633 struct adiv5_dap *dap_init(void)
635 struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
637 /* Set up with safe defaults */
638 for (i = 0; i <= 255; i++) {
639 dap->ap[i].dap = dap;
640 dap->ap[i].ap_num = i;
641 /* memaccess_tck max is 255 */
642 dap->ap[i].memaccess_tck = 255;
643 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
644 dap->ap[i].tar_autoincr_block = (1<<10);
646 dap->ap_current = -1;
647 dap->ap_bank_value = -1;
648 dap->dp_bank_value = -1;
653 * Initialize a DAP. This sets up the power domains, prepares the DP
654 * for further use and activates overrun checking.
656 * @param dap The DAP being initialized.
658 int dap_dp_init(struct adiv5_dap *dap)
663 /* JTAG-DP or SWJ-DP, in JTAG mode
664 * ... for SWD mode this is patched as part
666 * FIXME: This should already be setup by the respective transport specific DAP creation.
669 dap->ops = &jtag_dp_ops;
671 dap->ap_current = -1;
672 dap->ap_bank_value = -1;
673 dap->last_read = NULL;
675 for (size_t i = 0; i < 10; i++) {
676 /* DP initialization */
678 dap->dp_bank_value = 0;
680 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
681 if (retval != ERROR_OK)
684 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
685 if (retval != ERROR_OK)
688 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
689 if (retval != ERROR_OK)
692 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
693 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
694 if (retval != ERROR_OK)
697 /* Check that we have debug power domains activated */
698 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
699 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
700 CDBGPWRUPACK, CDBGPWRUPACK,
701 DAP_POWER_DOMAIN_TIMEOUT);
702 if (retval != ERROR_OK)
705 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
706 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
707 CSYSPWRUPACK, CSYSPWRUPACK,
708 DAP_POWER_DOMAIN_TIMEOUT);
709 if (retval != ERROR_OK)
712 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
713 if (retval != ERROR_OK)
716 /* With debug power on we can activate OVERRUN checking */
717 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
718 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
719 if (retval != ERROR_OK)
721 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
722 if (retval != ERROR_OK)
725 retval = dap_run(dap);
726 if (retval != ERROR_OK)
736 * Initialize a DAP. This sets up the power domains, prepares the DP
737 * for further use, and arranges to use AP #0 for all AP operations
738 * until dap_ap-select() changes that policy.
740 * @param ap The MEM-AP being initialized.
742 int mem_ap_init(struct adiv5_ap *ap)
744 /* check that we support packed transfers */
747 struct adiv5_dap *dap = ap->dap;
749 dap_ap_select(dap, ap->ap_num);
751 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
752 if (retval != ERROR_OK)
755 retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
756 if (retval != ERROR_OK)
759 retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
760 if (retval != ERROR_OK)
763 retval = dap_run(dap);
764 if (retval != ERROR_OK)
767 if (csw & CSW_ADDRINC_PACKED)
768 ap->packed_transfers = true;
770 ap->packed_transfers = false;
772 /* Packed transfers on TI BE-32 processors do not work correctly in
774 if (dap->ti_be_32_quirks)
775 ap->packed_transfers = false;
777 LOG_DEBUG("MEM_AP Packed Transfers: %s",
778 ap->packed_transfers ? "enabled" : "disabled");
780 /* The ARM ADI spec leaves implementation-defined whether unaligned
781 * memory accesses work, only work partially, or cause a sticky error.
782 * On TI BE-32 processors, reads seem to return garbage in some bytes
783 * and unaligned writes seem to cause a sticky error.
784 * TODO: it would be nice to have a way to detect whether unaligned
785 * operations are supported on other processors. */
786 ap->unaligned_access_bad = dap->ti_be_32_quirks;
788 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
789 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
794 /* CID interpretation -- see ARM IHI 0029B section 3
795 * and ARM IHI 0031A table 13-3.
797 static const char *class_description[16] = {
798 "Reserved", "ROM table", "Reserved", "Reserved",
799 "Reserved", "Reserved", "Reserved", "Reserved",
800 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
801 "Reserved", "OptimoDE DESS",
802 "Generic IP component", "PrimeCell or System component"
805 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
807 return cid3 == 0xb1 && cid2 == 0x05
808 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
812 * This function checks the ID for each access port to find the requested Access Port type
814 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
818 /* Maximum AP number is 255 since the SELECT register is 8 bits */
819 for (ap_num = 0; ap_num <= 255; ap_num++) {
821 /* read the IDR register of the Access Port */
823 dap_ap_select(dap, ap_num);
825 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
826 if (retval != ERROR_OK)
829 retval = dap_run(dap);
833 * 27-24 : JEDEC bank (0x4 for ARM)
834 * 23-17 : JEDEC code (0x3B for ARM)
835 * 16-13 : Class (0b1000=Mem-AP)
837 * 7-4 : AP Variant (non-zero for JTAG-AP)
838 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
841 /* Reading register for a non-existant AP should not cause an error,
842 * but just to be sure, try to continue searching if an error does happen.
844 if ((retval == ERROR_OK) && /* Register read success */
845 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
846 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
848 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
849 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
850 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
851 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
852 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
855 *ap_out = &dap->ap[ap_num];
860 LOG_DEBUG("No %s found",
861 (type_to_find == AP_TYPE_AHB_AP) ? "AHB-AP" :
862 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
863 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
864 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
868 int dap_get_debugbase(struct adiv5_ap *ap,
869 uint32_t *dbgbase, uint32_t *apid)
871 struct adiv5_dap *dap = ap->dap;
875 ap_old = dap_ap_get_select(dap);
876 dap_ap_select(dap, ap->ap_num);
878 retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
879 if (retval != ERROR_OK)
881 retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
882 if (retval != ERROR_OK)
884 retval = dap_run(dap);
885 if (retval != ERROR_OK)
888 dap_ap_select(dap, ap_old);
893 int dap_lookup_cs_component(struct adiv5_ap *ap,
894 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
896 struct adiv5_dap *dap = ap->dap;
898 uint32_t romentry, entry_offset = 0, component_base, devtype;
902 ap_old = dap_ap_get_select(dap);
905 retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
906 entry_offset, &romentry);
907 if (retval != ERROR_OK)
910 component_base = (dbgbase & 0xFFFFF000)
911 + (romentry & 0xFFFFF000);
913 if (romentry & 0x1) {
915 retval = mem_ap_sel_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
916 if (retval != ERROR_OK) {
917 LOG_ERROR("Can't read component with base address 0x%" PRIx32
918 ", the corresponding core might be turned off", component_base);
921 if (((c_cid1 >> 4) & 0x0f) == 1) {
922 retval = dap_lookup_cs_component(ap, component_base,
924 if (retval == ERROR_OK)
926 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
930 retval = mem_ap_sel_read_atomic_u32(ap,
931 (component_base & 0xfffff000) | 0xfcc,
933 if (retval != ERROR_OK)
935 if ((devtype & 0xff) == type) {
937 *addr = component_base;
944 } while (romentry > 0);
946 dap_ap_select(dap, ap_old);
949 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
954 static int dap_rom_display(struct command_context *cmd_ctx,
955 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
957 struct adiv5_dap *dap = ap->dap;
959 uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
960 uint16_t entry_offset;
964 command_print(cmd_ctx, "\tTables too deep");
969 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
971 /* bit 16 of apid indicates a memory access port */
973 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
975 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
977 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
978 retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
979 if (retval != ERROR_OK)
981 retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
982 if (retval != ERROR_OK)
984 retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
985 if (retval != ERROR_OK)
987 retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
988 if (retval != ERROR_OK)
990 retval = mem_ap_sel_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
991 if (retval != ERROR_OK)
993 retval = dap_run(dap);
994 if (retval != ERROR_OK)
997 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
998 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1003 (unsigned)cid3, (unsigned)cid2,
1004 (unsigned)cid1, (unsigned)cid0);
1006 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1008 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1010 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1011 for (entry_offset = 0; ; entry_offset += 4) {
1012 retval = mem_ap_sel_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1013 if (retval != ERROR_OK)
1015 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1016 tabs, entry_offset, romentry);
1017 if (romentry & 0x01) {
1018 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1019 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1020 uint32_t component_base;
1022 const char *type, *full;
1024 component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1026 /* IDs are in last 4K section */
1027 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
1028 if (retval != ERROR_OK) {
1029 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1030 ", the corresponding core might be turned off", tabs, component_base);
1034 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
1035 if (retval != ERROR_OK)
1038 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
1039 if (retval != ERROR_OK)
1042 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
1043 if (retval != ERROR_OK)
1046 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
1047 if (retval != ERROR_OK)
1051 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1052 if (retval != ERROR_OK)
1055 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1056 if (retval != ERROR_OK)
1059 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1060 if (retval != ERROR_OK)
1063 retval = mem_ap_sel_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1064 if (retval != ERROR_OK)
1068 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1069 "start address 0x%" PRIx32, component_base,
1070 /* component may take multiple 4K pages */
1071 (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1072 command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1073 (uint8_t)((c_cid1 >> 4) & 0xf),
1074 /* See ARM IHI 0029B Table 3-3 */
1075 class_description[(c_cid1 >> 4) & 0xf]);
1077 /* CoreSight component? */
1078 if (((c_cid1 >> 4) & 0x0f) == 9) {
1081 const char *major = "Reserved", *subtype = "Reserved";
1083 retval = mem_ap_sel_read_atomic_u32(ap,
1084 (component_base & 0xfffff000) | 0xfcc,
1086 if (retval != ERROR_OK)
1088 minor = (devtype >> 4) & 0x0f;
1089 switch (devtype & 0x0f) {
1091 major = "Miscellaneous";
1097 subtype = "Validation component";
1102 major = "Trace Sink";
1119 major = "Trace Link";
1125 subtype = "Funnel, router";
1131 subtype = "FIFO, buffer";
1136 major = "Trace Source";
1142 subtype = "Processor";
1148 subtype = "Engine/Coprocessor";
1154 subtype = "Software";
1159 major = "Debug Control";
1165 subtype = "Trigger Matrix";
1168 subtype = "Debug Auth";
1171 subtype = "Power Requestor";
1176 major = "Debug Logic";
1182 subtype = "Processor";
1188 subtype = "Engine/Coprocessor";
1199 major = "Perfomance Monitor";
1205 subtype = "Processor";
1211 subtype = "Engine/Coprocessor";
1222 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1223 (uint8_t)(devtype & 0xff),
1225 /* REVISIT also show 0xfc8 DevId */
1228 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1229 command_print(cmd_ctx,
1238 command_print(cmd_ctx,
1239 "\t\tPeripheral ID[4..0] = hex "
1240 "%02x %02x %02x %02x %02x",
1241 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1242 (int)c_pid1, (int)c_pid0);
1244 /* Part number interpretations are from Cortex
1245 * core specs, the CoreSight components TRM
1246 * (ARM DDI 0314H), CoreSight System Design
1247 * Guide (ARM DGI 0012D) and ETM specs; also
1248 * from chip observation (e.g. TI SDTI).
1250 part_num = (c_pid0 & 0xff);
1251 part_num |= (c_pid1 & 0x0f) << 8;
1254 type = "Cortex-M3 NVIC";
1255 full = "(Interrupt Controller)";
1258 type = "Cortex-M3 ITM";
1259 full = "(Instrumentation Trace Module)";
1262 type = "Cortex-M3 DWT";
1263 full = "(Data Watchpoint and Trace)";
1266 type = "Cortex-M3 FBP";
1267 full = "(Flash Patch and Breakpoint)";
1270 type = "Cortex-M0 SCS";
1271 full = "(System Control Space)";
1274 type = "Cortex-M0 DWT";
1275 full = "(Data Watchpoint and Trace)";
1278 type = "Cortex-M0 BPU";
1279 full = "(Breakpoint Unit)";
1282 type = "Cortex-M4 SCS";
1283 full = "(System Control Space)";
1286 type = "CoreSight ETM11";
1287 full = "(Embedded Trace)";
1289 /* case 0x113: what? */
1290 case 0x120: /* from OMAP3 memmap */
1292 full = "(System Debug Trace Interface)";
1294 case 0x343: /* from OMAP3 memmap */
1299 type = "Coresight CTI";
1300 full = "(Cross Trigger)";
1303 type = "Coresight ETB";
1304 full = "(Trace Buffer)";
1307 type = "Coresight CSTF";
1308 full = "(Trace Funnel)";
1311 type = "CoreSight ETM9";
1312 full = "(Embedded Trace)";
1315 type = "Coresight TPIU";
1316 full = "(Trace Port Interface Unit)";
1319 type = "Coresight ITM";
1320 full = "(Instrumentation Trace Macrocell)";
1323 type = "Coresight SWO";
1324 full = "(Single Wire Output)";
1327 type = "Coresight HTM";
1328 full = "(AHB Trace Macrocell)";
1331 type = "CoreSight ETM11";
1332 full = "(Embedded Trace)";
1335 type = "Cortex-A8 ETM";
1336 full = "(Embedded Trace)";
1339 type = "Cortex-A8 CTI";
1340 full = "(Cross Trigger)";
1343 type = "Cortex-M3 TPIU";
1344 full = "(Trace Port Interface Unit)";
1347 type = "Cortex-M3 ETM";
1348 full = "(Embedded Trace)";
1351 type = "Cortex-M4 ETM";
1352 full = "(Embedded Trace)";
1355 type = "Cortex-R4 ETM";
1356 full = "(Embedded Trace)";
1359 type = "CoreSight Component";
1360 full = "(unidentified Cortex-A9 component)";
1363 type = "CoreSight TMC";
1364 full = "(Trace Memory Controller)";
1367 type = "CoreSight STM";
1368 full = "(System Trace Macrocell)";
1371 type = "CoreSight PMU";
1372 full = "(Performance Monitoring Unit)";
1375 type = "Cortex-M4 TPUI";
1376 full = "(Trace Port Interface Unit)";
1379 type = "Cortex-A5 ETM";
1380 full = "(Embedded Trace)";
1383 type = "Cortex-A5 Debug";
1384 full = "(Debug Unit)";
1387 type = "Cortex-A8 Debug";
1388 full = "(Debug Unit)";
1391 type = "Cortex-A9 Debug";
1392 full = "(Debug Unit)";
1395 type = "Cortex-A15 Debug";
1396 full = "(Debug Unit)";
1399 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1400 type = "-*- unrecognized -*-";
1404 command_print(cmd_ctx, "\t\tPart is %s %s",
1408 if (((c_cid1 >> 4) & 0x0f) == 1) {
1409 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1410 if (retval != ERROR_OK)
1415 command_print(cmd_ctx, "\t\tComponent not present");
1420 command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1424 static int dap_info_command(struct command_context *cmd_ctx,
1425 struct adiv5_ap *ap)
1428 uint32_t dbgbase, apid;
1429 int romtable_present = 0;
1432 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1433 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1434 if (retval != ERROR_OK)
1437 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1439 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1443 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1444 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1445 command_print(cmd_ctx, "\tType is JTAG-AP");
1447 case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1448 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1450 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1451 command_print(cmd_ctx, "\tType is MEM-AP APB");
1453 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1454 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1457 command_print(cmd_ctx, "\tUnknown AP type");
1461 /* NOTE: a MEM-AP may have a single CoreSight component that's
1462 * not a ROM table ... or have no such components at all.
1464 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1466 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1468 romtable_present = dbgbase != 0xFFFFFFFF;
1469 if (romtable_present)
1470 dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1472 command_print(cmd_ctx, "\tNo ROM table present");
1478 COMMAND_HANDLER(handle_dap_info_command)
1480 struct target *target = get_current_target(CMD_CTX);
1481 struct arm *arm = target_to_arm(target);
1482 struct adiv5_dap *dap = arm->dap;
1490 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1492 return ERROR_COMMAND_SYNTAX_ERROR;
1495 return ERROR_COMMAND_SYNTAX_ERROR;
1498 return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1501 COMMAND_HANDLER(dap_baseaddr_command)
1503 struct target *target = get_current_target(CMD_CTX);
1504 struct arm *arm = target_to_arm(target);
1505 struct adiv5_dap *dap = arm->dap;
1507 uint32_t apsel, baseaddr;
1515 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1516 /* AP address is in bits 31:24 of DP_SELECT */
1518 return ERROR_COMMAND_SYNTAX_ERROR;
1521 return ERROR_COMMAND_SYNTAX_ERROR;
1524 dap_ap_select(dap, apsel);
1526 /* NOTE: assumes we're talking to a MEM-AP, which
1527 * has a base address. There are other kinds of AP,
1528 * though they're not common for now. This should
1529 * use the ID register to verify it's a MEM-AP.
1531 retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1532 if (retval != ERROR_OK)
1534 retval = dap_run(dap);
1535 if (retval != ERROR_OK)
1538 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1543 COMMAND_HANDLER(dap_memaccess_command)
1545 struct target *target = get_current_target(CMD_CTX);
1546 struct arm *arm = target_to_arm(target);
1547 struct adiv5_dap *dap = arm->dap;
1549 uint32_t memaccess_tck;
1553 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1556 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1559 return ERROR_COMMAND_SYNTAX_ERROR;
1561 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1563 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1564 dap->ap[dap->apsel].memaccess_tck);
1569 COMMAND_HANDLER(dap_apsel_command)
1571 struct target *target = get_current_target(CMD_CTX);
1572 struct arm *arm = target_to_arm(target);
1573 struct adiv5_dap *dap = arm->dap;
1575 uint32_t apsel, apid;
1583 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1584 /* AP address is in bits 31:24 of DP_SELECT */
1586 return ERROR_COMMAND_SYNTAX_ERROR;
1589 return ERROR_COMMAND_SYNTAX_ERROR;
1593 dap_ap_select(dap, apsel);
1595 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1596 if (retval != ERROR_OK)
1598 retval = dap_run(dap);
1599 if (retval != ERROR_OK)
1602 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1608 COMMAND_HANDLER(dap_apcsw_command)
1610 struct target *target = get_current_target(CMD_CTX);
1611 struct arm *arm = target_to_arm(target);
1612 struct adiv5_dap *dap = arm->dap;
1614 uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1618 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1619 (dap->apsel), apcsw);
1622 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1623 /* AP address is in bits 31:24 of DP_SELECT */
1625 return ERROR_COMMAND_SYNTAX_ERROR;
1629 apcsw &= ~CSW_SPROT;
1632 return ERROR_COMMAND_SYNTAX_ERROR;
1634 dap->ap[dap->apsel].csw_default = apcsw;
1641 COMMAND_HANDLER(dap_apid_command)
1643 struct target *target = get_current_target(CMD_CTX);
1644 struct arm *arm = target_to_arm(target);
1645 struct adiv5_dap *dap = arm->dap;
1647 uint32_t apsel, apid;
1655 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1656 /* AP address is in bits 31:24 of DP_SELECT */
1658 return ERROR_COMMAND_SYNTAX_ERROR;
1661 return ERROR_COMMAND_SYNTAX_ERROR;
1664 dap_ap_select(dap, apsel);
1666 retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1667 if (retval != ERROR_OK)
1669 retval = dap_run(dap);
1670 if (retval != ERROR_OK)
1673 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1678 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1680 struct target *target = get_current_target(CMD_CTX);
1681 struct arm *arm = target_to_arm(target);
1682 struct adiv5_dap *dap = arm->dap;
1684 uint32_t enable = dap->ti_be_32_quirks;
1690 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1692 return ERROR_COMMAND_SYNTAX_ERROR;
1695 return ERROR_COMMAND_SYNTAX_ERROR;
1697 dap->ti_be_32_quirks = enable;
1698 command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1699 enable ? "enabled" : "disabled");
1704 static const struct command_registration dap_commands[] = {
1707 .handler = handle_dap_info_command,
1708 .mode = COMMAND_EXEC,
1709 .help = "display ROM table for MEM-AP "
1710 "(default currently selected AP)",
1711 .usage = "[ap_num]",
1715 .handler = dap_apsel_command,
1716 .mode = COMMAND_EXEC,
1717 .help = "Set the currently selected AP (default 0) "
1718 "and display the result",
1719 .usage = "[ap_num]",
1723 .handler = dap_apcsw_command,
1724 .mode = COMMAND_EXEC,
1725 .help = "Set csw access bit ",
1731 .handler = dap_apid_command,
1732 .mode = COMMAND_EXEC,
1733 .help = "return ID register from AP "
1734 "(default currently selected AP)",
1735 .usage = "[ap_num]",
1739 .handler = dap_baseaddr_command,
1740 .mode = COMMAND_EXEC,
1741 .help = "return debug base address from MEM-AP "
1742 "(default currently selected AP)",
1743 .usage = "[ap_num]",
1746 .name = "memaccess",
1747 .handler = dap_memaccess_command,
1748 .mode = COMMAND_EXEC,
1749 .help = "set/get number of extra tck for MEM-AP memory "
1750 "bus access [0-255]",
1751 .usage = "[cycles]",
1754 .name = "ti_be_32_quirks",
1755 .handler = dap_ti_be_32_quirks_command,
1756 .mode = COMMAND_CONFIG,
1757 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1758 .usage = "[enable]",
1760 COMMAND_REGISTRATION_DONE
1763 const struct command_registration dap_command_handlers[] = {
1766 .mode = COMMAND_EXEC,
1767 .help = "DAP command group",
1769 .chain = dap_commands,
1771 COMMAND_REGISTRATION_DONE