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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
  98 {
  99         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 100                 ap->csw_default;
 101
 102         if (csw != ap->csw_value) {
 103                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 104                 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
 105                 if (retval != ERROR_OK)
 106                         return retval;
 107                 ap->csw_value = csw;
 108         }
 109         return ERROR_OK;
 110 }
 111
 112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
 113 {
 114         if (tar != ap->tar_value ||
 115                         (ap->csw_value & CSW_ADDRINC_MASK)) {
 116                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 117                 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
 118                 if (retval != ERROR_OK)
 119                         return retval;
 120                 ap->tar_value = tar;
 121         }
 122         return ERROR_OK;
 123 }
 124
 125 /**
 126  * Queue transactions setting up transfer parameters for the
 127  * currently selected MEM-AP.
 128  *
 129  * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
 130  * initiate data reads or writes using memory or peripheral addresses.
 131  * If the CSW is configured for it, the TAR may be automatically
 132  * incremented after each transfer.
 133  *
 134  * @param ap The MEM-AP.
 135  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 136  *      matches the cached value, the register is not changed.
 137  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 138  *      matches the cached address, the register is not changed.
 139  *
 140  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 141  */
 142 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
 143 {
 144         int retval;
 145         retval = mem_ap_setup_csw(ap, csw);
 146         if (retval != ERROR_OK)
 147                 return retval;
 148         retval = mem_ap_setup_tar(ap, tar);
 149         if (retval != ERROR_OK)
 150                 return retval;
 151         return ERROR_OK;
 152 }
 153
 154 /**
 155  * Asynchronous (queued) read of a word from memory or a system register.
 156  *
 157  * @param ap The MEM-AP to access.
 158  * @param address Address of the 32-bit word to read; it must be
 159  *      readable by the currently selected MEM-AP.
 160  * @param value points to where the word will be stored when the
 161  *      transaction queue is flushed (assuming no errors).
 162  *
 163  * @return ERROR_OK for success.  Otherwise a fault code.
 164  */
 165 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
 166                 uint32_t *value)
 167 {
 168         int retval;
 169
 170         /* Use banked addressing (REG_BDx) to avoid some link traffic
 171          * (updating TAR) when reading several consecutive addresses.
 172          */
 173         retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
 174                         address & 0xFFFFFFF0);
 175         if (retval != ERROR_OK)
 176                 return retval;
 177
 178         return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
 179 }
 180
 181 /**
 182  * Synchronous read of a word from memory or a system register.
 183  * As a side effect, this flushes any queued transactions.
 184  *
 185  * @param ap The MEM-AP to access.
 186  * @param address Address of the 32-bit word to read; it must be
 187  *      readable by the currently selected MEM-AP.
 188  * @param value points to where the result will be stored.
 189  *
 190  * @return ERROR_OK for success; *value holds the result.
 191  * Otherwise a fault code.
 192  */
 193 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 194                 uint32_t *value)
 195 {
 196         int retval;
 197
 198         retval = mem_ap_read_u32(ap, address, value);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         return dap_run(ap->dap);
 203 }
 204
 205 /**
 206  * Asynchronous (queued) write of a word to memory or a system register.
 207  *
 208  * @param ap The MEM-AP to access.
 209  * @param address Address to be written; it must be writable by
 210  *      the currently selected MEM-AP.
 211  * @param value Word that will be written to the address when transaction
 212  *      queue is flushed (assuming no errors).
 213  *
 214  * @return ERROR_OK for success.  Otherwise a fault code.
 215  */
 216 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
 217                 uint32_t value)
 218 {
 219         int retval;
 220
 221         /* Use banked addressing (REG_BDx) to avoid some link traffic
 222          * (updating TAR) when writing several consecutive addresses.
 223          */
 224         retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
 225                         address & 0xFFFFFFF0);
 226         if (retval != ERROR_OK)
 227                 return retval;
 228
 229         return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
 230                         value);
 231 }
 232
 233 /**
 234  * Synchronous write of a word to memory or a system register.
 235  * As a side effect, this flushes any queued transactions.
 236  *
 237  * @param ap The MEM-AP to access.
 238  * @param address Address to be written; it must be writable by
 239  *      the currently selected MEM-AP.
 240  * @param value Word that will be written.
 241  *
 242  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 243  */
 244 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 245                 uint32_t value)
 246 {
 247         int retval = mem_ap_write_u32(ap, address, value);
 248
 249         if (retval != ERROR_OK)
 250                 return retval;
 251
 252         return dap_run(ap->dap);
 253 }
 254
 255 /**
 256  * Synchronous write of a block of memory, using a specific access size.
 257  *
 258  * @param ap The MEM-AP to access.
 259  * @param buffer The data buffer to write. No particular alignment is assumed.
 260  * @param size Which access size to use, in bytes. 1, 2 or 4.
 261  * @param count The number of writes to do (in size units, not bytes).
 262  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 263  * @param addrinc Whether the target address should be increased for each write or not. This
 264  *  should normally be true, except when writing to e.g. a FIFO.
 265  * @return ERROR_OK on success, otherwise an error code.
 266  */
 267 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
 268                 uint32_t address, bool addrinc)
 269 {
 270         struct adiv5_dap *dap = ap->dap;
 271         size_t nbytes = size * count;
 272         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 273         uint32_t csw_size;
 274         uint32_t addr_xor;
 275         int retval;
 276
 277         /* TI BE-32 Quirks mode:
 278          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 279          *   size   write address   bytes written in order
 280          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 281          *   2      TAR ^ 2         (val >> 8), (val)
 282          *   1      TAR ^ 3         (val)
 283          * For example, if you attempt to write a single byte to address 0, the processor
 284          * will actually write a byte to address 3.
 285          *
 286          * To make writes of size < 4 work as expected, we xor a value with the address before
 287          * setting the TAP, and we set the TAP after every transfer rather then relying on
 288          * address increment. */
 289
 290         if (size == 4) {
 291                 csw_size = CSW_32BIT;
 292                 addr_xor = 0;
 293         } else if (size == 2) {
 294                 csw_size = CSW_16BIT;
 295                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 296         } else if (size == 1) {
 297                 csw_size = CSW_8BIT;
 298                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 299         } else {
 300                 return ERROR_TARGET_UNALIGNED_ACCESS;
 301         }
 302
 303         if (ap->unaligned_access_bad && (address % size != 0))
 304                 return ERROR_TARGET_UNALIGNED_ACCESS;
 305
 306         retval = mem_ap_setup_tar(ap, address ^ addr_xor);
 307         if (retval != ERROR_OK)
 308                 return retval;
 309
 310         while (nbytes > 0) {
 311                 uint32_t this_size = size;
 312
 313                 /* Select packed transfer if possible */
 314                 if (addrinc && ap->packed_transfers && nbytes >= 4
 315                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 316                         this_size = 4;
 317                         retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
 318                 } else {
 319                         retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
 320                 }
 321
 322                 if (retval != ERROR_OK)
 323                         break;
 324
 325                 /* How many source bytes each transfer will consume, and their location in the DRW,
 326                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 327                 uint32_t outvalue = 0;
 328                 if (dap->ti_be_32_quirks) {
 329                         switch (this_size) {
 330                         case 4:
 331                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 332                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 333                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 334                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 335                                 break;
 336                         case 2:
 337                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 338                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 339                                 break;
 340                         case 1:
 341                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 342                                 break;
 343                         }
 344                 } else {
 345                         switch (this_size) {
 346                         case 4:
 347                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 348                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 349                         case 2:
 350                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 351                         case 1:
 352                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 353                         }
 354                 }
 355
 356                 nbytes -= this_size;
 357
 358                 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
 359                 if (retval != ERROR_OK)
 360                         break;
 361
 362                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 363                 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
 364                         retval = mem_ap_setup_tar(ap, address ^ addr_xor);
 365                         if (retval != ERROR_OK)
 366                                 break;
 367                 }
 368         }
 369
 370         /* REVISIT: Might want to have a queued version of this function that does not run. */
 371         if (retval == ERROR_OK)
 372                 retval = dap_run(dap);
 373
 374         if (retval != ERROR_OK) {
 375                 uint32_t tar;
 376                 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 377                                 && dap_run(dap) == ERROR_OK)
 378                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 379                 else
 380                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 381         }
 382
 383         return retval;
 384 }
 385
 386 /**
 387  * Synchronous read of a block of memory, using a specific access size.
 388  *
 389  * @param ap The MEM-AP to access.
 390  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 391  * @param size Which access size to use, in bytes. 1, 2 or 4.
 392  * @param count The number of reads to do (in size units, not bytes).
 393  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 394  * @param addrinc Whether the target address should be increased after each read or not. This
 395  *  should normally be true, except when reading from e.g. a FIFO.
 396  * @return ERROR_OK on success, otherwise an error code.
 397  */
 398 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
 399                 uint32_t adr, bool addrinc)
 400 {
 401         struct adiv5_dap *dap = ap->dap;
 402         size_t nbytes = size * count;
 403         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 404         uint32_t csw_size;
 405         uint32_t address = adr;
 406         int retval;
 407
 408         /* TI BE-32 Quirks mode:
 409          * Reads on big-endian TMS570 behave strangely differently than writes.
 410          * They read from the physical address requested, but with DRW byte-reversed.
 411          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 412          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 413          * so avoid them. */
 414
 415         if (size == 4)
 416                 csw_size = CSW_32BIT;
 417         else if (size == 2)
 418                 csw_size = CSW_16BIT;
 419         else if (size == 1)
 420                 csw_size = CSW_8BIT;
 421         else
 422                 return ERROR_TARGET_UNALIGNED_ACCESS;
 423
 424         if (ap->unaligned_access_bad && (adr % size != 0))
 425                 return ERROR_TARGET_UNALIGNED_ACCESS;
 426
 427         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 428          * over-allocation if packed transfers are going to be used, but determining the real need at
 429          * this point would be messy. */
 430         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 431         uint32_t *read_ptr = read_buf;
 432         if (read_buf == NULL) {
 433                 LOG_ERROR("Failed to allocate read buffer");
 434                 return ERROR_FAIL;
 435         }
 436
 437         retval = mem_ap_setup_tar(ap, address);
 438         if (retval != ERROR_OK) {
 439                 free(read_buf);
 440                 return retval;
 441         }
 442
 443         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 444          * useful bytes it contains, and their location in the word, depends on the type of transfer
 445          * and alignment. */
 446         while (nbytes > 0) {
 447                 uint32_t this_size = size;
 448
 449                 /* Select packed transfer if possible */
 450                 if (addrinc && ap->packed_transfers && nbytes >= 4
 451                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 452                         this_size = 4;
 453                         retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
 454                 } else {
 455                         retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
 456                 }
 457                 if (retval != ERROR_OK)
 458                         break;
 459
 460                 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
 461                 if (retval != ERROR_OK)
 462                         break;
 463
 464                 nbytes -= this_size;
 465                 address += this_size;
 466
 467                 /* Rewrite TAR if it wrapped */
 468                 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
 469                         retval = mem_ap_setup_tar(ap, address);
 470                         if (retval != ERROR_OK)
 471                                 break;
 472                 }
 473         }
 474
 475         if (retval == ERROR_OK)
 476                 retval = dap_run(dap);
 477
 478         /* Restore state */
 479         address = adr;
 480         nbytes = size * count;
 481         read_ptr = read_buf;
 482
 483         /* If something failed, read TAR to find out how much data was successfully read, so we can
 484          * at least give the caller what we have. */
 485         if (retval != ERROR_OK) {
 486                 uint32_t tar;
 487                 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 488                                 && dap_run(dap) == ERROR_OK) {
 489                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 490                         if (nbytes > tar - address)
 491                                 nbytes = tar - address;
 492                 } else {
 493                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 494                         nbytes = 0;
 495                 }
 496         }
 497
 498         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 499         while (nbytes > 0) {
 500                 uint32_t this_size = size;
 501
 502                 if (addrinc && ap->packed_transfers && nbytes >= 4
 503                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 504                         this_size = 4;
 505                 }
 506
 507                 if (dap->ti_be_32_quirks) {
 508                         switch (this_size) {
 509                         case 4:
 510                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 511                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 512                         case 2:
 513                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 514                         case 1:
 515                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 516                         }
 517                 } else {
 518                         switch (this_size) {
 519                         case 4:
 520                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 521                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 522                         case 2:
 523                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 524                         case 1:
 525                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 526                         }
 527                 }
 528
 529                 read_ptr++;
 530                 nbytes -= this_size;
 531         }
 532
 533         free(read_buf);
 534         return retval;
 535 }
 536
 537 int mem_ap_read_buf(struct adiv5_ap *ap,
 538                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 539 {
 540         return mem_ap_read(ap, buffer, size, count, address, true);
 541 }
 542
 543 int mem_ap_write_buf(struct adiv5_ap *ap,
 544                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 545 {
 546         return mem_ap_write(ap, buffer, size, count, address, true);
 547 }
 548
 549 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
 550                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 551 {
 552         return mem_ap_read(ap, buffer, size, count, address, false);
 553 }
 554
 555 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
 556                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 557 {
 558         return mem_ap_write(ap, buffer, size, count, address, false);
 559 }
 560
 561 /*--------------------------------------------------------------------------*/
 562
 563
 564 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 565
 566 /* FIXME don't import ... just initialize as
 567  * part of DAP transport setup
 568 */
 569 extern const struct dap_ops jtag_dp_ops;
 570
 571 /*--------------------------------------------------------------------------*/
 572
 573 /**
 574  * Create a new DAP
 575  */
 576 struct adiv5_dap *dap_init(void)
 577 {
 578         struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
 579         int i;
 580         /* Set up with safe defaults */
 581         for (i = 0; i <= 255; i++) {
 582                 dap->ap[i].dap = dap;
 583                 dap->ap[i].ap_num = i;
 584                 /* memaccess_tck max is 255 */
 585                 dap->ap[i].memaccess_tck = 255;
 586                 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
 587                 dap->ap[i].tar_autoincr_block = (1<<10);
 588         }
 589         return dap;
 590 }
 591
 592 /**
 593  * Initialize a DAP.  This sets up the power domains, prepares the DP
 594  * for further use and activates overrun checking.
 595  *
 596  * @param dap The DAP being initialized.
 597  */
 598 int dap_dp_init(struct adiv5_dap *dap)
 599 {
 600         int retval;
 601
 602         LOG_DEBUG(" ");
 603         /* JTAG-DP or SWJ-DP, in JTAG mode
 604          * ... for SWD mode this is patched as part
 605          * of link switchover
 606          * FIXME: This should already be setup by the respective transport specific DAP creation.
 607          */
 608         if (!dap->ops)
 609                 dap->ops = &jtag_dp_ops;
 610
 611         dap->select = DP_SELECT_INVALID;
 612         dap->last_read = NULL;
 613
 614         for (size_t i = 0; i < 10; i++) {
 615                 /* DP initialization */
 616
 617                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 618                 if (retval != ERROR_OK)
 619                         continue;
 620
 621                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 622                 if (retval != ERROR_OK)
 623                         continue;
 624
 625                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 626                 if (retval != ERROR_OK)
 627                         continue;
 628
 629                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 630                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 631                 if (retval != ERROR_OK)
 632                         continue;
 633
 634                 /* Check that we have debug power domains activated */
 635                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 636                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 637                                               CDBGPWRUPACK, CDBGPWRUPACK,
 638                                               DAP_POWER_DOMAIN_TIMEOUT);
 639                 if (retval != ERROR_OK)
 640                         continue;
 641
 642                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 643                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 644                                               CSYSPWRUPACK, CSYSPWRUPACK,
 645                                               DAP_POWER_DOMAIN_TIMEOUT);
 646                 if (retval != ERROR_OK)
 647                         continue;
 648
 649                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 650                 if (retval != ERROR_OK)
 651                         continue;
 652
 653                 /* With debug power on we can activate OVERRUN checking */
 654                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 655                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 656                 if (retval != ERROR_OK)
 657                         continue;
 658                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 659                 if (retval != ERROR_OK)
 660                         continue;
 661
 662                 retval = dap_run(dap);
 663                 if (retval != ERROR_OK)
 664                         continue;
 665
 666                 break;
 667         }
 668
 669         return retval;
 670 }
 671
 672 /**
 673  * Initialize a DAP.  This sets up the power domains, prepares the DP
 674  * for further use, and arranges to use AP #0 for all AP operations
 675  * until dap_ap-select() changes that policy.
 676  *
 677  * @param ap The MEM-AP being initialized.
 678  */
 679 int mem_ap_init(struct adiv5_ap *ap)
 680 {
 681         /* check that we support packed transfers */
 682         uint32_t csw, cfg;
 683         int retval;
 684         struct adiv5_dap *dap = ap->dap;
 685
 686         retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 687         if (retval != ERROR_OK)
 688                 return retval;
 689
 690         retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
 691         if (retval != ERROR_OK)
 692                 return retval;
 693
 694         retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
 695         if (retval != ERROR_OK)
 696                 return retval;
 697
 698         retval = dap_run(dap);
 699         if (retval != ERROR_OK)
 700                 return retval;
 701
 702         if (csw & CSW_ADDRINC_PACKED)
 703                 ap->packed_transfers = true;
 704         else
 705                 ap->packed_transfers = false;
 706
 707         /* Packed transfers on TI BE-32 processors do not work correctly in
 708          * many cases. */
 709         if (dap->ti_be_32_quirks)
 710                 ap->packed_transfers = false;
 711
 712         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 713                         ap->packed_transfers ? "enabled" : "disabled");
 714
 715         /* The ARM ADI spec leaves implementation-defined whether unaligned
 716          * memory accesses work, only work partially, or cause a sticky error.
 717          * On TI BE-32 processors, reads seem to return garbage in some bytes
 718          * and unaligned writes seem to cause a sticky error.
 719          * TODO: it would be nice to have a way to detect whether unaligned
 720          * operations are supported on other processors. */
 721         ap->unaligned_access_bad = dap->ti_be_32_quirks;
 722
 723         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 724                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 725
 726         return ERROR_OK;
 727 }
 728
 729 /* CID interpretation -- see ARM IHI 0029B section 3
 730  * and ARM IHI 0031A table 13-3.
 731  */
 732 static const char *class_description[16] = {
 733         "Reserved", "ROM table", "Reserved", "Reserved",
 734         "Reserved", "Reserved", "Reserved", "Reserved",
 735         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 736         "Reserved", "OptimoDE DESS",
 737         "Generic IP component", "PrimeCell or System component"
 738 };
 739
 740 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 741 {
 742         return cid3 == 0xb1 && cid2 == 0x05
 743                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 744 }
 745
 746 /*
 747  * This function checks the ID for each access port to find the requested Access Port type
 748  */
 749 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 750 {
 751         int ap_num;
 752
 753         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 754         for (ap_num = 0; ap_num <= 255; ap_num++) {
 755
 756                 /* read the IDR register of the Access Port */
 757                 uint32_t id_val = 0;
 758
 759                 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
 760                 if (retval != ERROR_OK)
 761                         return retval;
 762
 763                 retval = dap_run(dap);
 764
 765                 /* IDR bits:
 766                  * 31-28 : Revision
 767                  * 27-24 : JEDEC bank (0x4 for ARM)
 768                  * 23-17 : JEDEC code (0x3B for ARM)
 769                  * 16-13 : Class (0b1000=Mem-AP)
 770                  * 12-8  : Reserved
 771                  *  7-4  : AP Variant (non-zero for JTAG-AP)
 772                  *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
 773                  */
 774
 775                 /* Reading register for a non-existant AP should not cause an error,
 776                  * but just to be sure, try to continue searching if an error does happen.
 777                  */
 778                 if ((retval == ERROR_OK) &&                  /* Register read success */
 779                         ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
 780                         ((id_val & IDR_TYPE) == type_to_find)) {      /* type matches*/
 781
 782                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 783                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 784                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 785                                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 786                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 787                                                 ap_num, id_val);
 788
 789                         *ap_out = &dap->ap[ap_num];
 790                         return ERROR_OK;
 791                 }
 792         }
 793
 794         LOG_DEBUG("No %s found",
 795                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 796                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 797                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 798                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 799         return ERROR_FAIL;
 800 }
 801
 802 int dap_get_debugbase(struct adiv5_ap *ap,
 803                         uint32_t *dbgbase, uint32_t *apid)
 804 {
 805         struct adiv5_dap *dap = ap->dap;
 806         int retval;
 807
 808         retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
 809         if (retval != ERROR_OK)
 810                 return retval;
 811         retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
 812         if (retval != ERROR_OK)
 813                 return retval;
 814         retval = dap_run(dap);
 815         if (retval != ERROR_OK)
 816                 return retval;
 817
 818         return ERROR_OK;
 819 }
 820
 821 int dap_lookup_cs_component(struct adiv5_ap *ap,
 822                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
 823 {
 824         uint32_t romentry, entry_offset = 0, component_base, devtype;
 825         int retval;
 826
 827         *addr = 0;
 828
 829         do {
 830                 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
 831                                                 entry_offset, &romentry);
 832                 if (retval != ERROR_OK)
 833                         return retval;
 834
 835                 component_base = (dbgbase & 0xFFFFF000)
 836                         + (romentry & 0xFFFFF000);
 837
 838                 if (romentry & 0x1) {
 839                         uint32_t c_cid1;
 840                         retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
 841                         if (retval != ERROR_OK) {
 842                                 LOG_ERROR("Can't read component with base address 0x%" PRIx32
 843                                           ", the corresponding core might be turned off", component_base);
 844                                 return retval;
 845                         }
 846                         if (((c_cid1 >> 4) & 0x0f) == 1) {
 847                                 retval = dap_lookup_cs_component(ap, component_base,
 848                                                         type, addr, idx);
 849                                 if (retval == ERROR_OK)
 850                                         break;
 851                                 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 852                                         return retval;
 853                         }
 854
 855                         retval = mem_ap_read_atomic_u32(ap,
 856                                         (component_base & 0xfffff000) | 0xfcc,
 857                                         &devtype);
 858                         if (retval != ERROR_OK)
 859                                 return retval;
 860                         if ((devtype & 0xff) == type) {
 861                                 if (!*idx) {
 862                                         *addr = component_base;
 863                                         break;
 864                                 } else
 865                                         (*idx)--;
 866                         }
 867                 }
 868                 entry_offset += 4;
 869         } while (romentry > 0);
 870
 871         if (!*addr)
 872                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 873
 874         return ERROR_OK;
 875 }
 876
 877 /* The designer identity code is encoded as:
 878  * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
 879  * bit 7     : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
 880  *             a legacy ASCII Identity Code.
 881  * bits 6:0  : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
 882  * JEP106 is a standard available from jedec.org
 883  */
 884
 885 /* Part number interpretations are from Cortex
 886  * core specs, the CoreSight components TRM
 887  * (ARM DDI 0314H), CoreSight System Design
 888  * Guide (ARM DGI 0012D) and ETM specs; also
 889  * from chip observation (e.g. TI SDTI).
 890  */
 891
 892 /* The legacy code only used the part number field to identify CoreSight peripherals.
 893  * This meant that the same part number from two different manufacturers looked the same.
 894  * It is desirable for all future additions to identify with both part number and JEP106.
 895  * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
 896  */
 897
 898 #define ANY_ID 0x1000
 899
 900 #define ARM_ID 0x4BB
 901
 902 static const struct {
 903         uint16_t designer_id;
 904         uint16_t part_num;
 905         const char *type;
 906         const char *full;
 907 } dap_partnums[] = {
 908         { ARM_ID, 0x000, "Cortex-M3 SCS",    "(System Control Space)", },
 909         { ARM_ID, 0x001, "Cortex-M3 ITM",    "(Instrumentation Trace Module)", },
 910         { ARM_ID, 0x002, "Cortex-M3 DWT",    "(Data Watchpoint and Trace)", },
 911         { ARM_ID, 0x003, "Cortex-M3 FBP",    "(Flash Patch and Breakpoint)", },
 912         { ARM_ID, 0x008, "Cortex-M0 SCS",    "(System Control Space)", },
 913         { ARM_ID, 0x00a, "Cortex-M0 DWT",    "(Data Watchpoint and Trace)", },
 914         { ARM_ID, 0x00b, "Cortex-M0 BPU",    "(Breakpoint Unit)", },
 915         { ARM_ID, 0x00c, "Cortex-M4 SCS",    "(System Control Space)", },
 916         { ARM_ID, 0x00d, "CoreSight ETM11",  "(Embedded Trace)", },
 917         { ARM_ID, 0x490, "Cortex-A15 GIC",   "(Generic Interrupt Controller)", },
 918         { ARM_ID, 0x4c7, "Cortex-M7 PPB",    "(Private Peripheral Bus ROM Table)", },
 919         { ARM_ID, 0x906, "CoreSight CTI",    "(Cross Trigger)", },
 920         { ARM_ID, 0x907, "CoreSight ETB",    "(Trace Buffer)", },
 921         { ARM_ID, 0x908, "CoreSight CSTF",   "(Trace Funnel)", },
 922         { ARM_ID, 0x910, "CoreSight ETM9",   "(Embedded Trace)", },
 923         { ARM_ID, 0x912, "CoreSight TPIU",   "(Trace Port Interface Unit)", },
 924         { ARM_ID, 0x913, "CoreSight ITM",    "(Instrumentation Trace Macrocell)", },
 925         { ARM_ID, 0x914, "CoreSight SWO",    "(Single Wire Output)", },
 926         { ARM_ID, 0x917, "CoreSight HTM",    "(AHB Trace Macrocell)", },
 927         { ARM_ID, 0x920, "CoreSight ETM11",  "(Embedded Trace)", },
 928         { ARM_ID, 0x921, "Cortex-A8 ETM",    "(Embedded Trace)", },
 929         { ARM_ID, 0x922, "Cortex-A8 CTI",    "(Cross Trigger)", },
 930         { ARM_ID, 0x923, "Cortex-M3 TPIU",   "(Trace Port Interface Unit)", },
 931         { ARM_ID, 0x924, "Cortex-M3 ETM",    "(Embedded Trace)", },
 932         { ARM_ID, 0x925, "Cortex-M4 ETM",    "(Embedded Trace)", },
 933         { ARM_ID, 0x930, "Cortex-R4 ETM",    "(Embedded Trace)", },
 934         { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
 935         { ARM_ID, 0x950, "CoreSight Component", "(unidentified Cortex-A9 component)", },
 936         { ARM_ID, 0x955, "CoreSight Component", "(unidentified Cortex-A5 component)", },
 937         { ARM_ID, 0x95f, "Cortex-A15 PTM",   "(Program Trace Macrocell)", },
 938         { ARM_ID, 0x961, "CoreSight TMC",    "(Trace Memory Controller)", },
 939         { ARM_ID, 0x962, "CoreSight STM",    "(System Trace Macrocell)", },
 940         { ARM_ID, 0x9a0, "CoreSight PMU",    "(Performance Monitoring Unit)", },
 941         { ARM_ID, 0x9a1, "Cortex-M4 TPIU",   "(Trace Port Interface Unit)", },
 942         { ARM_ID, 0x9a5, "Cortex-A5 ETM",    "(Embedded Trace)", },
 943         { ARM_ID, 0x9a7, "Cortex-A7 PMU",    "(Performance Monitor Unit)", },
 944         { ARM_ID, 0x9af, "Cortex-A15 PMU",   "(Performance Monitor Unit)", },
 945         { ARM_ID, 0xc05, "Cortex-A5 Debug",  "(Debug Unit)", },
 946         { ARM_ID, 0xc07, "Cortex-A7 Debug",  "(Debug Unit)", },
 947         { ARM_ID, 0xc08, "Cortex-A8 Debug",  "(Debug Unit)", },
 948         { ARM_ID, 0xc09, "Cortex-A9 Debug",  "(Debug Unit)", },
 949         { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
 950         { ARM_ID, 0xc14, "Cortex-R4 Debug",  "(Debug Unit)", },
 951         { 0x0E5,  0x000, "SHARC+/Blackfin+", "", },
 952         /* legacy comment: 0x113: what? */
 953         { ANY_ID,  0x120, "TI SDTI",         "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
 954         { ANY_ID,  0x343, "TI DAPCTL",       "", }, /* from OMAP3 memmap */
 955 };
 956
 957 static int dap_rom_display(struct command_context *cmd_ctx,
 958                                 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
 959 {
 960         struct adiv5_dap *dap = ap->dap;
 961         int retval;
 962         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 963         uint16_t entry_offset;
 964         char tabs[7] = "";
 965
 966         if (depth > 16) {
 967                 command_print(cmd_ctx, "\tTables too deep");
 968                 return ERROR_FAIL;
 969         }
 970
 971         if (depth)
 972                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 973
 974         /* bit 16 of apid indicates a memory access port */
 975         if (dbgbase & 0x02)
 976                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 977         else
 978                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 979
 980         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 981         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 982         if (retval != ERROR_OK)
 983                 return retval;
 984         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 985         if (retval != ERROR_OK)
 986                 return retval;
 987         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 988         if (retval != ERROR_OK)
 989                 return retval;
 990         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 991         if (retval != ERROR_OK)
 992                 return retval;
 993         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 994         if (retval != ERROR_OK)
 995                 return retval;
 996         retval = dap_run(dap);
 997         if (retval != ERROR_OK)
 998                 return retval;
 999
1000         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1001                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
1002                                 ", CID2 0x%02x"
1003                                 ", CID1 0x%02x"
1004                                 ", CID0 0x%02x",
1005                                 tabs,
1006                                 (unsigned)cid3, (unsigned)cid2,
1007                                 (unsigned)cid1, (unsigned)cid0);
1008         if (memtype & 0x01)
1009                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
1010         else
1011                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
1012
1013         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1014         for (entry_offset = 0; ; entry_offset += 4) {
1015                 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1016                 if (retval != ERROR_OK)
1017                         return retval;
1018                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1019                                 tabs, entry_offset, romentry);
1020                 if (romentry & 0x01) {
1021                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1022                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1023                         uint32_t component_base;
1024                         uint16_t part_num, designer_id;
1025                         const char *type, *full;
1026
1027                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
1028
1029                         /* IDs are in last 4K section */
1030                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
1031                         if (retval != ERROR_OK) {
1032                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1033                                               ", the corresponding core might be turned off", tabs, component_base);
1034                                 continue;
1035                         }
1036                         c_pid0 &= 0xff;
1037                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
1038                         if (retval != ERROR_OK)
1039                                 return retval;
1040                         c_pid1 &= 0xff;
1041                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
1042                         if (retval != ERROR_OK)
1043                                 return retval;
1044                         c_pid2 &= 0xff;
1045                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
1046                         if (retval != ERROR_OK)
1047                                 return retval;
1048                         c_pid3 &= 0xff;
1049                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
1050                         if (retval != ERROR_OK)
1051                                 return retval;
1052                         c_pid4 &= 0xff;
1053
1054                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
1055                         if (retval != ERROR_OK)
1056                                 return retval;
1057                         c_cid0 &= 0xff;
1058                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
1059                         if (retval != ERROR_OK)
1060                                 return retval;
1061                         c_cid1 &= 0xff;
1062                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
1063                         if (retval != ERROR_OK)
1064                                 return retval;
1065                         c_cid2 &= 0xff;
1066                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
1067                         if (retval != ERROR_OK)
1068                                 return retval;
1069                         c_cid3 &= 0xff;
1070
1071                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1072                                       "start address 0x%" PRIx32, component_base,
1073                                       /* component may take multiple 4K pages */
1074                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1075                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1076                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1077                                         /* See ARM IHI 0029B Table 3-3 */
1078                                         class_description[(c_cid1 >> 4) & 0xf]);
1079
1080                         /* CoreSight component? */
1081                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1082                                 uint32_t devtype;
1083                                 unsigned minor;
1084                                 const char *major = "Reserved", *subtype = "Reserved";
1085
1086                                 retval = mem_ap_read_atomic_u32(ap,
1087                                                 (component_base & 0xfffff000) | 0xfcc,
1088                                                 &devtype);
1089                                 if (retval != ERROR_OK)
1090                                         return retval;
1091                                 minor = (devtype >> 4) & 0x0f;
1092                                 switch (devtype & 0x0f) {
1093                                 case 0:
1094                                         major = "Miscellaneous";
1095                                         switch (minor) {
1096                                         case 0:
1097                                                 subtype = "other";
1098                                                 break;
1099                                         case 4:
1100                                                 subtype = "Validation component";
1101                                                 break;
1102                                         }
1103                                         break;
1104                                 case 1:
1105                                         major = "Trace Sink";
1106                                         switch (minor) {
1107                                         case 0:
1108                                                 subtype = "other";
1109                                                 break;
1110                                         case 1:
1111                                                 subtype = "Port";
1112                                                 break;
1113                                         case 2:
1114                                                 subtype = "Buffer";
1115                                                 break;
1116                                         case 3:
1117                                                 subtype = "Router";
1118                                                 break;
1119                                         }
1120                                         break;
1121                                 case 2:
1122                                         major = "Trace Link";
1123                                         switch (minor) {
1124                                         case 0:
1125                                                 subtype = "other";
1126                                                 break;
1127                                         case 1:
1128                                                 subtype = "Funnel, router";
1129                                                 break;
1130                                         case 2:
1131                                                 subtype = "Filter";
1132                                                 break;
1133                                         case 3:
1134                                                 subtype = "FIFO, buffer";
1135                                                 break;
1136                                         }
1137                                         break;
1138                                 case 3:
1139                                         major = "Trace Source";
1140                                         switch (minor) {
1141                                         case 0:
1142                                                 subtype = "other";
1143                                                 break;
1144                                         case 1:
1145                                                 subtype = "Processor";
1146                                                 break;
1147                                         case 2:
1148                                                 subtype = "DSP";
1149                                                 break;
1150                                         case 3:
1151                                                 subtype = "Engine/Coprocessor";
1152                                                 break;
1153                                         case 4:
1154                                                 subtype = "Bus";
1155                                                 break;
1156                                         case 6:
1157                                                 subtype = "Software";
1158                                                 break;
1159                                         }
1160                                         break;
1161                                 case 4:
1162                                         major = "Debug Control";
1163                                         switch (minor) {
1164                                         case 0:
1165                                                 subtype = "other";
1166                                                 break;
1167                                         case 1:
1168                                                 subtype = "Trigger Matrix";
1169                                                 break;
1170                                         case 2:
1171                                                 subtype = "Debug Auth";
1172                                                 break;
1173                                         case 3:
1174                                                 subtype = "Power Requestor";
1175                                                 break;
1176                                         }
1177                                         break;
1178                                 case 5:
1179                                         major = "Debug Logic";
1180                                         switch (minor) {
1181                                         case 0:
1182                                                 subtype = "other";
1183                                                 break;
1184                                         case 1:
1185                                                 subtype = "Processor";
1186                                                 break;
1187                                         case 2:
1188                                                 subtype = "DSP";
1189                                                 break;
1190                                         case 3:
1191                                                 subtype = "Engine/Coprocessor";
1192                                                 break;
1193                                         case 4:
1194                                                 subtype = "Bus";
1195                                                 break;
1196                                         case 5:
1197                                                 subtype = "Memory";
1198                                                 break;
1199                                         }
1200                                         break;
1201                                 case 6:
1202                                         major = "Perfomance Monitor";
1203                                         switch (minor) {
1204                                         case 0:
1205                                                 subtype = "other";
1206                                                 break;
1207                                         case 1:
1208                                                 subtype = "Processor";
1209                                                 break;
1210                                         case 2:
1211                                                 subtype = "DSP";
1212                                                 break;
1213                                         case 3:
1214                                                 subtype = "Engine/Coprocessor";
1215                                                 break;
1216                                         case 4:
1217                                                 subtype = "Bus";
1218                                                 break;
1219                                         case 5:
1220                                                 subtype = "Memory";
1221                                                 break;
1222                                         }
1223                                         break;
1224                                 }
1225                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1226                                                 (uint8_t)(devtype & 0xff),
1227                                                 major, subtype);
1228                                 /* REVISIT also show 0xfc8 DevId */
1229                         }
1230
1231                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1232                                 command_print(cmd_ctx,
1233                                                 "\t\tCID3 0%02x"
1234                                                 ", CID2 0%02x"
1235                                                 ", CID1 0%02x"
1236                                                 ", CID0 0%02x",
1237                                                 (int)c_cid3,
1238                                                 (int)c_cid2,
1239                                                 (int)c_cid1,
1240                                                 (int)c_cid0);
1241                         command_print(cmd_ctx,
1242                                 "\t\tPeripheral ID[4..0] = hex "
1243                                 "%02x %02x %02x %02x %02x",
1244                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1245                                 (int)c_pid1, (int)c_pid0);
1246
1247                         part_num = (c_pid0 & 0xff);
1248                         part_num |= (c_pid1 & 0x0f) << 8;
1249                         designer_id = (c_pid1 & 0xf0) >> 4;
1250                         designer_id |= (c_pid2 & 0x0f) << 4;
1251                         designer_id |= (c_pid4 & 0x0f) << 8;
1252                         if ((designer_id & 0x80) == 0) {
1253                                 /* Legacy ASCII ID, clear invalid bits */
1254                                 designer_id &= 0x7f;
1255                         }
1256
1257                         /* default values to be overwritten upon finding a match */
1258                         type = NULL;
1259                         full = "";
1260
1261                         /* search dap_partnums[] array for a match */
1262                         unsigned entry;
1263                         for (entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1264
1265                                 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1266                                         continue;
1267
1268                                 if (dap_partnums[entry].part_num != part_num)
1269                                         continue;
1270
1271                                 type = dap_partnums[entry].type;
1272                                 full = dap_partnums[entry].full;
1273                                 break;
1274                         }
1275
1276                         if (type) {
1277                                 command_print(cmd_ctx, "\t\tPart is %s %s",
1278                                                 type, full);
1279                         } else {
1280                                 command_print(cmd_ctx, "\t\tUnrecognized (Part 0x%" PRIx16 ", designer 0x%" PRIx16 ")",
1281                                                 part_num, designer_id);
1282                         }
1283
1284                         /* ROM Table? */
1285                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1286                                 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1287                                 if (retval != ERROR_OK)
1288                                         return retval;
1289                         }
1290                 } else {
1291                         if (romentry)
1292                                 command_print(cmd_ctx, "\t\tComponent not present");
1293                         else
1294                                 break;
1295                 }
1296         }
1297         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1298         return ERROR_OK;
1299 }
1300
1301 static int dap_info_command(struct command_context *cmd_ctx,
1302                 struct adiv5_ap *ap)
1303 {
1304         int retval;
1305         uint32_t dbgbase, apid;
1306         int romtable_present = 0;
1307         uint8_t mem_ap;
1308
1309         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1310         retval = dap_get_debugbase(ap, &dbgbase, &apid);
1311         if (retval != ERROR_OK)
1312                 return retval;
1313
1314         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1315         if (apid == 0) {
1316                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1317                 return ERROR_FAIL;
1318         }
1319
1320         switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1321         case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1322                 command_print(cmd_ctx, "\tType is JTAG-AP");
1323                 break;
1324         case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1325                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1326                 break;
1327         case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1328                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1329                 break;
1330         case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1331                 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1332                 break;
1333         default:
1334                 command_print(cmd_ctx, "\tUnknown AP type");
1335                 break;
1336         }
1337
1338         /* NOTE: a MEM-AP may have a single CoreSight component that's
1339          * not a ROM table ... or have no such components at all.
1340          */
1341         mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1342         if (mem_ap) {
1343                 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1344
1345                 romtable_present = dbgbase != 0xFFFFFFFF;
1346                 if (romtable_present)
1347                         dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1348                 else
1349                         command_print(cmd_ctx, "\tNo ROM table present");
1350         }
1351
1352         return ERROR_OK;
1353 }
1354
1355 COMMAND_HANDLER(handle_dap_info_command)
1356 {
1357         struct target *target = get_current_target(CMD_CTX);
1358         struct arm *arm = target_to_arm(target);
1359         struct adiv5_dap *dap = arm->dap;
1360         uint32_t apsel;
1361
1362         switch (CMD_ARGC) {
1363         case 0:
1364                 apsel = dap->apsel;
1365                 break;
1366         case 1:
1367                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1368                 if (apsel >= 256)
1369                         return ERROR_COMMAND_SYNTAX_ERROR;
1370                 break;
1371         default:
1372                 return ERROR_COMMAND_SYNTAX_ERROR;
1373         }
1374
1375         return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1376 }
1377
1378 COMMAND_HANDLER(dap_baseaddr_command)
1379 {
1380         struct target *target = get_current_target(CMD_CTX);
1381         struct arm *arm = target_to_arm(target);
1382         struct adiv5_dap *dap = arm->dap;
1383
1384         uint32_t apsel, baseaddr;
1385         int retval;
1386
1387         switch (CMD_ARGC) {
1388         case 0:
1389                 apsel = dap->apsel;
1390                 break;
1391         case 1:
1392                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1393                 /* AP address is in bits 31:24 of DP_SELECT */
1394                 if (apsel >= 256)
1395                         return ERROR_COMMAND_SYNTAX_ERROR;
1396                 break;
1397         default:
1398                 return ERROR_COMMAND_SYNTAX_ERROR;
1399         }
1400
1401         /* NOTE:  assumes we're talking to a MEM-AP, which
1402          * has a base address.  There are other kinds of AP,
1403          * though they're not common for now.  This should
1404          * use the ID register to verify it's a MEM-AP.
1405          */
1406         retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1407         if (retval != ERROR_OK)
1408                 return retval;
1409         retval = dap_run(dap);
1410         if (retval != ERROR_OK)
1411                 return retval;
1412
1413         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1414
1415         return retval;
1416 }
1417
1418 COMMAND_HANDLER(dap_memaccess_command)
1419 {
1420         struct target *target = get_current_target(CMD_CTX);
1421         struct arm *arm = target_to_arm(target);
1422         struct adiv5_dap *dap = arm->dap;
1423
1424         uint32_t memaccess_tck;
1425
1426         switch (CMD_ARGC) {
1427         case 0:
1428                 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1429                 break;
1430         case 1:
1431                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1432                 break;
1433         default:
1434                 return ERROR_COMMAND_SYNTAX_ERROR;
1435         }
1436         dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1437
1438         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1439                         dap->ap[dap->apsel].memaccess_tck);
1440
1441         return ERROR_OK;
1442 }
1443
1444 COMMAND_HANDLER(dap_apsel_command)
1445 {
1446         struct target *target = get_current_target(CMD_CTX);
1447         struct arm *arm = target_to_arm(target);
1448         struct adiv5_dap *dap = arm->dap;
1449
1450         uint32_t apsel, apid;
1451         int retval;
1452
1453         switch (CMD_ARGC) {
1454         case 0:
1455                 apsel = dap->apsel;
1456                 break;
1457         case 1:
1458                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1459                 /* AP address is in bits 31:24 of DP_SELECT */
1460                 if (apsel >= 256)
1461                         return ERROR_COMMAND_SYNTAX_ERROR;
1462                 break;
1463         default:
1464                 return ERROR_COMMAND_SYNTAX_ERROR;
1465         }
1466
1467         dap->apsel = apsel;
1468
1469         retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1470         if (retval != ERROR_OK)
1471                 return retval;
1472         retval = dap_run(dap);
1473         if (retval != ERROR_OK)
1474                 return retval;
1475
1476         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1477                         apsel, apid);
1478
1479         return retval;
1480 }
1481
1482 COMMAND_HANDLER(dap_apcsw_command)
1483 {
1484         struct target *target = get_current_target(CMD_CTX);
1485         struct arm *arm = target_to_arm(target);
1486         struct adiv5_dap *dap = arm->dap;
1487
1488         uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1489
1490         switch (CMD_ARGC) {
1491         case 0:
1492                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1493                         (dap->apsel), apcsw);
1494                 break;
1495         case 1:
1496                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1497                 /* AP address is in bits 31:24 of DP_SELECT */
1498                 if (sprot > 1)
1499                         return ERROR_COMMAND_SYNTAX_ERROR;
1500                 if (sprot)
1501                         apcsw |= CSW_SPROT;
1502                 else
1503                         apcsw &= ~CSW_SPROT;
1504                 break;
1505         default:
1506                 return ERROR_COMMAND_SYNTAX_ERROR;
1507         }
1508         dap->ap[dap->apsel].csw_default = apcsw;
1509
1510         return 0;
1511 }
1512
1513
1514
1515 COMMAND_HANDLER(dap_apid_command)
1516 {
1517         struct target *target = get_current_target(CMD_CTX);
1518         struct arm *arm = target_to_arm(target);
1519         struct adiv5_dap *dap = arm->dap;
1520
1521         uint32_t apsel, apid;
1522         int retval;
1523
1524         switch (CMD_ARGC) {
1525         case 0:
1526                 apsel = dap->apsel;
1527                 break;
1528         case 1:
1529                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1530                 /* AP address is in bits 31:24 of DP_SELECT */
1531                 if (apsel >= 256)
1532                         return ERROR_COMMAND_SYNTAX_ERROR;
1533                 break;
1534         default:
1535                 return ERROR_COMMAND_SYNTAX_ERROR;
1536         }
1537
1538         retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1539         if (retval != ERROR_OK)
1540                 return retval;
1541         retval = dap_run(dap);
1542         if (retval != ERROR_OK)
1543                 return retval;
1544
1545         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1546
1547         return retval;
1548 }
1549
1550 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1551 {
1552         struct target *target = get_current_target(CMD_CTX);
1553         struct arm *arm = target_to_arm(target);
1554         struct adiv5_dap *dap = arm->dap;
1555
1556         uint32_t enable = dap->ti_be_32_quirks;
1557
1558         switch (CMD_ARGC) {
1559         case 0:
1560                 break;
1561         case 1:
1562                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1563                 if (enable > 1)
1564                         return ERROR_COMMAND_SYNTAX_ERROR;
1565                 break;
1566         default:
1567                 return ERROR_COMMAND_SYNTAX_ERROR;
1568         }
1569         dap->ti_be_32_quirks = enable;
1570         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1571                 enable ? "enabled" : "disabled");
1572
1573         return 0;
1574 }
1575
1576 static const struct command_registration dap_commands[] = {
1577         {
1578                 .name = "info",
1579                 .handler = handle_dap_info_command,
1580                 .mode = COMMAND_EXEC,
1581                 .help = "display ROM table for MEM-AP "
1582                         "(default currently selected AP)",
1583                 .usage = "[ap_num]",
1584         },
1585         {
1586                 .name = "apsel",
1587                 .handler = dap_apsel_command,
1588                 .mode = COMMAND_EXEC,
1589                 .help = "Set the currently selected AP (default 0) "
1590                         "and display the result",
1591                 .usage = "[ap_num]",
1592         },
1593         {
1594                 .name = "apcsw",
1595                 .handler = dap_apcsw_command,
1596                 .mode = COMMAND_EXEC,
1597                 .help = "Set csw access bit ",
1598                 .usage = "[sprot]",
1599         },
1600
1601         {
1602                 .name = "apid",
1603                 .handler = dap_apid_command,
1604                 .mode = COMMAND_EXEC,
1605                 .help = "return ID register from AP "
1606                         "(default currently selected AP)",
1607                 .usage = "[ap_num]",
1608         },
1609         {
1610                 .name = "baseaddr",
1611                 .handler = dap_baseaddr_command,
1612                 .mode = COMMAND_EXEC,
1613                 .help = "return debug base address from MEM-AP "
1614                         "(default currently selected AP)",
1615                 .usage = "[ap_num]",
1616         },
1617         {
1618                 .name = "memaccess",
1619                 .handler = dap_memaccess_command,
1620                 .mode = COMMAND_EXEC,
1621                 .help = "set/get number of extra tck for MEM-AP memory "
1622                         "bus access [0-255]",
1623                 .usage = "[cycles]",
1624         },
1625         {
1626                 .name = "ti_be_32_quirks",
1627                 .handler = dap_ti_be_32_quirks_command,
1628                 .mode = COMMAND_CONFIG,
1629                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1630                 .usage = "[enable]",
1631         },
1632         COMMAND_REGISTRATION_DONE
1633 };
1634
1635 const struct command_registration dap_command_handlers[] = {
1636         {
1637                 .name = "dap",
1638                 .mode = COMMAND_EXEC,
1639                 .help = "DAP command group",
1640                 .usage = "",
1641                 .chain = dap_commands,
1642         },
1643         COMMAND_REGISTRATION_DONE
1644 };