1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
31 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
32 * debugging architecture. Compared with previous versions, this includes
33 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
34 * transport, and focusses on memory mapped resources as defined by the
35 * CoreSight architecture.
37 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
38 * basic components: a Debug Port (DP) transporting messages to and from a
39 * debugger, and an Access Port (AP) accessing resources. Three types of DP
40 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
41 * One uses only SWD for communication, and is called SW-DP. The third can
42 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
43 * is used to access memory mapped resources and is called a MEM-AP. Also a
44 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
46 * This programming interface allows DAP pipelined operations through a
47 * transaction queue. This primarily affects AP operations (such as using
48 * a MEM-AP to access memory or registers). If the current transaction has
49 * not finished by the time the next one must begin, and the ORUNDETECT bit
50 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
51 * further AP operations will fail. There are two basic methods to avoid
52 * such overrun errors. One involves polling for status instead of using
53 * transaction piplining. The other involves adding delays to ensure the
54 * AP has enough time to complete one operation before starting the next
55 * one. (For JTAG these delays are controlled by memaccess_tck.)
59 * Relevant specifications from ARM include:
61 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
62 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
64 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
65 * Cortex-M3(tm) TRM, ARM DDI 0337G
72 #include "arm_adi_v5.h"
73 #include <helper/time_support.h>
76 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
79 uint32_t tar_block_size(uint32_t address)
80 Return the largest block starting at address that does not cross a tar block size alignment boundary
82 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
84 return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
87 /***************************************************************************
89 * DPACC and APACC scanchain access through JTAG-DP *
91 ***************************************************************************/
94 * Scan DPACC or APACC using target ordered uint8_t buffers. No endianness
95 * conversions are performed. See section 4.4.3 of the ADIv5 spec, which
96 * discusses operations which access these registers.
98 * Note that only one scan is performed. If RnW is set, a separate scan
99 * will be needed to collect the data which was read; the "invalue" collects
100 * the posted result of a preceding operation, not the current one.
102 * @param swjdp the DAP
103 * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
104 * @param reg_addr two significant bits; A[3:2]; for APACC access, the
105 * SELECT register has more addressing bits.
106 * @param RnW false iff outvalue will be written to the DP or AP
107 * @param outvalue points to a 32-bit (little-endian) integer
108 * @param invalue NULL, or points to a 32-bit (little-endian) integer
109 * @param ack points to where the three bit JTAG_ACK_* code will be stored
111 static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
112 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
113 uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
115 struct arm_jtag *jtag_info = swjdp->jtag_info;
116 struct scan_field fields[2];
117 uint8_t out_addr_buf;
119 jtag_set_end_state(TAP_IDLE);
120 arm_jtag_set_instr(jtag_info, instr, NULL);
122 /* Scan out a read or write operation using some DP or AP register.
123 * For APACC access with any sticky error flag set, this is discarded.
125 fields[0].tap = jtag_info->tap;
126 fields[0].num_bits = 3;
127 buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
128 fields[0].out_value = &out_addr_buf;
129 fields[0].in_value = ack;
131 /* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
132 * complete; data we write is discarded, data we read is unpredictable.
133 * When overrun detect is active, STICKYORUN is set.
136 fields[1].tap = jtag_info->tap;
137 fields[1].num_bits = 32;
138 fields[1].out_value = outvalue;
139 fields[1].in_value = invalue;
141 jtag_add_dr_scan(2, fields, jtag_get_end_state());
143 /* Add specified number of tck clocks after starting memory bus
144 * access, giving the hardware time to complete the access.
145 * They provide more time for the (MEM) AP to complete the read ...
146 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
148 if ((instr == JTAG_DP_APACC)
149 && ((reg_addr == AP_REG_DRW)
150 || ((reg_addr & 0xF0) == AP_REG_BD0))
151 && (swjdp->memaccess_tck != 0))
152 jtag_add_runtest(swjdp->memaccess_tck,
153 jtag_set_end_state(TAP_IDLE));
155 return jtag_get_error();
159 * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
160 * This is exactly like adi_jtag_dp_scan(), except that endianness
161 * conversions are performed (so the types of invalue and outvalue
162 * must be different).
164 static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
165 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
166 uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
168 uint8_t out_value_buf[4];
171 buf_set_u32(out_value_buf, 0, 32, outvalue);
173 retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
174 out_value_buf, (uint8_t *)invalue, ack);
175 if (retval != ERROR_OK)
179 jtag_add_callback(arm_le_to_h_u32,
180 (jtag_callback_data_t) invalue);
186 * Utility to write AP registers.
188 static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
189 uint8_t reg_addr, uint8_t *outvalue)
191 return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
192 outvalue, NULL, NULL);
195 static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
196 uint8_t instr, uint8_t reg_addr, uint8_t RnW,
197 uint32_t outvalue, uint32_t *invalue)
201 /* Issue the read or write */
202 retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
203 RnW, outvalue, NULL, NULL);
204 if (retval != ERROR_OK)
207 /* For reads, collect posted value; RDBUFF has no other effect.
208 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
210 if ((RnW == DPAP_READ) && (invalue != NULL))
211 retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
212 DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
216 static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
221 /* too expensive to call keep_alive() here */
224 /* Danger!!!! BROKEN!!!! */
225 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
226 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
227 /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
228 R956 introduced the check on return value here and now Michael Schwingen reports
229 that this code no longer works....
231 https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
233 if ((retval = jtag_execute_queue()) != ERROR_OK)
235 LOG_ERROR("BUG: Why does this fail the first time????");
237 /* Why??? second time it works??? */
240 /* Post CTRL/STAT read; discard any previous posted read value
241 * but collect its ACK status.
243 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
244 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
245 if ((retval = jtag_execute_queue()) != ERROR_OK)
248 swjdp->ack = swjdp->ack & 0x7;
250 /* common code path avoids calling timeval_ms() */
251 if (swjdp->ack != JTAG_ACK_OK_FAULT)
253 long long then = timeval_ms();
255 while (swjdp->ack != JTAG_ACK_OK_FAULT)
257 if (swjdp->ack == JTAG_ACK_WAIT)
259 if ((timeval_ms()-then) > 1000)
261 /* NOTE: this would be a good spot
262 * to use JTAG_DP_ABORT.
264 LOG_WARNING("Timeout (1000ms) waiting "
266 "in JTAG-DP transaction");
267 return ERROR_JTAG_DEVICE_ERROR;
272 LOG_WARNING("Invalid ACK %#x "
273 "in JTAG-DP transaction",
275 return ERROR_JTAG_DEVICE_ERROR;
278 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
279 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
280 if ((retval = dap_run(swjdp)) != ERROR_OK)
282 swjdp->ack = swjdp->ack & 0x7;
286 /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
288 /* Check for STICKYERR and STICKYORUN */
289 if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
291 LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
292 /* Check power to debug regions */
293 if ((ctrlstat & 0xf0000000) != 0xf0000000)
294 ahbap_debugport_init(swjdp);
297 uint32_t mem_ap_csw, mem_ap_tar;
299 /* Maybe print information about last intended
300 * MEM-AP access; but not if autoincrementing.
301 * *Real* CSW and TAR values are always shown.
303 if (swjdp->ap_tar_value != (uint32_t) -1)
304 LOG_DEBUG("MEM-AP Cached values: "
306 ", ap_csw 0x%" PRIx32
307 ", ap_tar 0x%" PRIx32,
308 swjdp->ap_bank_value,
310 swjdp->ap_tar_value);
312 if (ctrlstat & SSTICKYORUN)
313 LOG_ERROR("JTAG-DP OVERRUN - check clock, "
314 "memaccess, or reduce jtag speed");
316 if (ctrlstat & SSTICKYERR)
317 LOG_ERROR("JTAG-DP STICKY ERROR");
319 /* Clear Sticky Error Bits */
320 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
321 DP_CTRL_STAT, DPAP_WRITE,
322 swjdp->dp_ctrl_stat | SSTICKYORUN
324 adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
325 DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
326 if ((retval = dap_run(swjdp)) != ERROR_OK)
329 LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
331 retval = dap_queue_ap_read(swjdp,
332 AP_REG_CSW, &mem_ap_csw);
333 if (retval != ERROR_OK)
336 retval = dap_queue_ap_read(swjdp,
337 AP_REG_TAR, &mem_ap_tar);
338 if (retval != ERROR_OK)
341 if ((retval = dap_run(swjdp)) != ERROR_OK)
343 LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
344 PRIx32, mem_ap_csw, mem_ap_tar);
347 if ((retval = dap_run(swjdp)) != ERROR_OK)
349 return ERROR_JTAG_DEVICE_ERROR;
355 /***************************************************************************
357 * DP and MEM-AP register access through APACC and DPACC *
359 ***************************************************************************/
362 * Select one of the APs connected to the specified DAP. The
363 * selection is implicitly used with future AP transactions.
364 * This is a NOP if the specified AP is already selected.
366 * @param swjdp The DAP
367 * @param apsel Number of the AP to (implicitly) use with further
368 * transactions. This normally identifies a MEM-AP.
370 void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
372 uint32_t select = (apsel << 24) & 0xFF000000;
374 if (select != swjdp->apsel)
376 swjdp->apsel = select;
377 /* Switching AP invalidates cached values.
378 * Values MUST BE UPDATED BEFORE AP ACCESS.
380 swjdp->ap_bank_value = -1;
381 swjdp->ap_csw_value = -1;
382 swjdp->ap_tar_value = -1;
387 * Queue transactions setting up transfer parameters for the
388 * currently selected MEM-AP.
390 * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
391 * initiate data reads or writes using memory or peripheral addresses.
392 * If the CSW is configured for it, the TAR may be automatically
393 * incremented after each transfer.
395 * @todo Rename to reflect it being specifically a MEM-AP function.
397 * @param swjdp The DAP connected to the MEM-AP.
398 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
399 * matches the cached value, the register is not changed.
400 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
401 * matches the cached address, the register is not changed.
403 * @return ERROR_OK if the transaction was properly queued, else a fault code.
405 int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
409 csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
410 if (csw != swjdp->ap_csw_value)
412 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
413 retval = dap_queue_ap_write(swjdp, AP_REG_CSW, csw);
414 if (retval != ERROR_OK)
416 swjdp->ap_csw_value = csw;
418 if (tar != swjdp->ap_tar_value)
420 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
421 retval = dap_queue_ap_write(swjdp, AP_REG_TAR, tar);
422 if (retval != ERROR_OK)
424 swjdp->ap_tar_value = tar;
426 /* Disable TAR cache when autoincrementing */
427 if (csw & CSW_ADDRINC_MASK)
428 swjdp->ap_tar_value = -1;
433 * Asynchronous (queued) read of a word from memory or a system register.
435 * @param swjdp The DAP connected to the MEM-AP performing the read.
436 * @param address Address of the 32-bit word to read; it must be
437 * readable by the currently selected MEM-AP.
438 * @param value points to where the word will be stored when the
439 * transaction queue is flushed (assuming no errors).
441 * @return ERROR_OK for success. Otherwise a fault code.
443 int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
448 /* Use banked addressing (REG_BDx) to avoid some link traffic
449 * (updating TAR) when reading several consecutive addresses.
451 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
452 address & 0xFFFFFFF0);
453 if (retval != ERROR_OK)
456 return dap_queue_ap_read(swjdp, AP_REG_BD0 | (address & 0xC), value);
460 * Synchronous read of a word from memory or a system register.
461 * As a side effect, this flushes any queued transactions.
463 * @param swjdp The DAP connected to the MEM-AP performing the read.
464 * @param address Address of the 32-bit word to read; it must be
465 * readable by the currently selected MEM-AP.
466 * @param value points to where the result will be stored.
468 * @return ERROR_OK for success; *value holds the result.
469 * Otherwise a fault code.
471 int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
476 retval = mem_ap_read_u32(swjdp, address, value);
477 if (retval != ERROR_OK)
480 return dap_run(swjdp);
484 * Asynchronous (queued) write of a word to memory or a system register.
486 * @param swjdp The DAP connected to the MEM-AP.
487 * @param address Address to be written; it must be writable by
488 * the currently selected MEM-AP.
489 * @param value Word that will be written to the address when transaction
490 * queue is flushed (assuming no errors).
492 * @return ERROR_OK for success. Otherwise a fault code.
494 int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
499 /* Use banked addressing (REG_BDx) to avoid some link traffic
500 * (updating TAR) when writing several consecutive addresses.
502 retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
503 address & 0xFFFFFFF0);
504 if (retval != ERROR_OK)
507 return dap_queue_ap_write(swjdp, AP_REG_BD0 | (address & 0xC),
512 * Synchronous write of a word to memory or a system register.
513 * As a side effect, this flushes any queued transactions.
515 * @param swjdp The DAP connected to the MEM-AP.
516 * @param address Address to be written; it must be writable by
517 * the currently selected MEM-AP.
518 * @param value Word that will be written.
520 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
522 int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
525 int retval = mem_ap_write_u32(swjdp, address, value);
527 if (retval != ERROR_OK)
530 return dap_run(swjdp);
533 /*****************************************************************************
535 * mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
537 * Write a buffer in target order (little endian) *
539 *****************************************************************************/
540 int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
542 int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
543 uint32_t adr = address;
544 uint8_t* pBuffer = buffer;
549 /* if we have an unaligned access - reorder data */
552 for (writecount = 0; writecount < count; writecount++)
556 memcpy(&outvalue, pBuffer, sizeof(uint32_t));
558 for (i = 0; i < 4; i++)
560 *((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
564 pBuffer += sizeof(uint32_t);
570 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
571 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
572 if (wcount < blocksize)
575 /* handle unaligned data at 4k boundary */
579 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
581 for (writecount = 0; writecount < blocksize; writecount++)
583 retval = dap_queue_ap_write(swjdp, AP_REG_DRW,
584 *(uint32_t *) (buffer + 4 * writecount));
585 if (retval != ERROR_OK)
589 if (dap_run(swjdp) == ERROR_OK)
591 wcount = wcount - blocksize;
592 address = address + 4 * blocksize;
593 buffer = buffer + 4 * blocksize;
602 LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
603 /* REVISIT return the *actual* fault code */
604 return ERROR_JTAG_DEVICE_ERROR;
611 static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
612 uint8_t *buffer, int count, uint32_t address)
614 int retval = ERROR_OK;
615 int wcount, blocksize, writecount, i;
623 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
624 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
626 if (wcount < blocksize)
629 /* handle unaligned data at 4k boundary */
633 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
634 writecount = blocksize;
638 nbytes = MIN((writecount << 1), 4);
642 if (mem_ap_write_buf_u16(swjdp, buffer,
643 nbytes, address) != ERROR_OK)
645 LOG_WARNING("Block write error address "
646 "0x%" PRIx32 ", count 0x%x",
648 return ERROR_JTAG_DEVICE_ERROR;
651 address += nbytes >> 1;
656 memcpy(&outvalue, buffer, sizeof(uint32_t));
658 for (i = 0; i < nbytes; i++)
660 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
665 memcpy(&outvalue, buffer, sizeof(uint32_t));
666 retval = dap_queue_ap_write(swjdp,
667 AP_REG_DRW, outvalue);
668 if (retval != ERROR_OK)
671 if (dap_run(swjdp) != ERROR_OK)
673 LOG_WARNING("Block write error address "
674 "0x%" PRIx32 ", count 0x%x",
676 /* REVISIT return *actual* fault code */
677 return ERROR_JTAG_DEVICE_ERROR;
681 buffer += nbytes >> 1;
682 writecount -= nbytes >> 1;
684 } while (writecount);
691 int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
693 int retval = ERROR_OK;
696 return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
700 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
702 memcpy(&svalue, buffer, sizeof(uint16_t));
703 uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
704 retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
705 if (retval != ERROR_OK)
708 retval = dap_run(swjdp);
709 if (retval != ERROR_OK)
720 static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
721 uint8_t *buffer, int count, uint32_t address)
723 int retval = ERROR_OK;
724 int wcount, blocksize, writecount, i;
732 /* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
733 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
735 if (wcount < blocksize)
738 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
739 writecount = blocksize;
743 nbytes = MIN(writecount, 4);
747 if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
749 LOG_WARNING("Block write error address "
750 "0x%" PRIx32 ", count 0x%x",
752 return ERROR_JTAG_DEVICE_ERROR;
760 memcpy(&outvalue, buffer, sizeof(uint32_t));
762 for (i = 0; i < nbytes; i++)
764 *((uint8_t*)buffer + (address & 0x3)) = outvalue;
769 memcpy(&outvalue, buffer, sizeof(uint32_t));
770 retval = dap_queue_ap_write(swjdp,
771 AP_REG_DRW, outvalue);
772 if (retval != ERROR_OK)
775 if (dap_run(swjdp) != ERROR_OK)
777 LOG_WARNING("Block write error address "
778 "0x%" PRIx32 ", count 0x%x",
780 /* REVISIT return *actual* fault code */
781 return ERROR_JTAG_DEVICE_ERROR;
786 writecount -= nbytes;
788 } while (writecount);
795 int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
797 int retval = ERROR_OK;
800 return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
804 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
805 uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
806 retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
807 if (retval != ERROR_OK)
810 retval = dap_run(swjdp);
811 if (retval != ERROR_OK)
823 * Synchronously read a block of 32-bit words into a buffer
824 * @param swjdp The DAP connected to the MEM-AP.
825 * @param buffer where the words will be stored (in host byte order).
826 * @param count How many words to read.
827 * @param address Memory address from which to read words; all the
828 * words must be readable by the currently selected MEM-AP.
830 int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
831 int count, uint32_t address)
833 int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
834 uint32_t adr = address;
835 uint8_t* pBuffer = buffer;
842 /* Adjust to read blocks within boundaries aligned to the
843 * TAR autoincrement size (at least 2^10). Autoincrement
844 * mode avoids an extra per-word roundtrip to update TAR.
846 blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
848 if (wcount < blocksize)
851 /* handle unaligned data at 4k boundary */
855 dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
858 /* FIXME remove these three calls to adi_jtag_dp_scan(),
859 * so this routine becomes transport-neutral. Be careful
860 * not to cause performance problems with JTAG; would it
861 * suffice to loop over dap_queue_ap_read(), or would that
862 * be slower when JTAG is the chosen transport?
865 /* Scan out first read */
866 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
867 DPAP_READ, 0, NULL, NULL);
868 for (readcount = 0; readcount < blocksize - 1; readcount++)
870 /* Scan out next read; scan in posted value for the
871 * previous one. Assumes read is acked "OK/FAULT",
872 * and CTRL_STAT says that meant "OK".
874 adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
875 DPAP_READ, 0, buffer + 4 * readcount,
879 /* Scan in last posted value; RDBUFF has no other effect,
880 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
882 adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
883 DPAP_READ, 0, buffer + 4 * readcount,
885 if (dap_run(swjdp) == ERROR_OK)
887 wcount = wcount - blocksize;
888 address += 4 * blocksize;
889 buffer += 4 * blocksize;
898 LOG_WARNING("Block read error address 0x%" PRIx32
899 ", count 0x%x", address, count);
900 /* REVISIT return the *actual* fault code */
901 return ERROR_JTAG_DEVICE_ERROR;
905 /* if we have an unaligned access - reorder data */
908 for (readcount = 0; readcount < count; readcount++)
912 memcpy(&data, pBuffer, sizeof(uint32_t));
914 for (i = 0; i < 4; i++)
916 *((uint8_t*)pBuffer) =
917 (data >> 8 * (adr & 0x3));
927 static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
928 uint8_t *buffer, int count, uint32_t address)
931 int retval = ERROR_OK;
932 int wcount, blocksize, readcount, i;
940 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
941 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
942 if (wcount < blocksize)
945 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
947 /* handle unaligned data at 4k boundary */
950 readcount = blocksize;
954 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
955 if (dap_run(swjdp) != ERROR_OK)
957 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
958 /* REVISIT return the *actual* fault code */
959 return ERROR_JTAG_DEVICE_ERROR;
962 nbytes = MIN((readcount << 1), 4);
964 for (i = 0; i < nbytes; i++)
966 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
971 readcount -= (nbytes >> 1);
980 * Synchronously read a block of 16-bit halfwords into a buffer
981 * @param swjdp The DAP connected to the MEM-AP.
982 * @param buffer where the halfwords will be stored (in host byte order).
983 * @param count How many halfwords to read.
984 * @param address Memory address from which to read words; all the
985 * words must be readable by the currently selected MEM-AP.
987 int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
988 int count, uint32_t address)
991 int retval = ERROR_OK;
994 return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
998 dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
999 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
1000 if (retval != ERROR_OK)
1003 retval = dap_run(swjdp);
1004 if (retval != ERROR_OK)
1009 for (i = 0; i < 2; i++)
1011 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1018 uint16_t svalue = (invalue >> 8 * (address & 0x3));
1019 memcpy(buffer, &svalue, sizeof(uint16_t));
1029 /* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
1030 * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
1032 * The solution is to arrange for a large out/in scan in this loop and
1033 * and convert data afterwards.
1035 static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
1036 uint8_t *buffer, int count, uint32_t address)
1039 int retval = ERROR_OK;
1040 int wcount, blocksize, readcount, i;
1048 /* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
1049 blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
1051 if (wcount < blocksize)
1054 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
1055 readcount = blocksize;
1059 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
1060 if (dap_run(swjdp) != ERROR_OK)
1062 LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
1063 /* REVISIT return the *actual* fault code */
1064 return ERROR_JTAG_DEVICE_ERROR;
1067 nbytes = MIN(readcount, 4);
1069 for (i = 0; i < nbytes; i++)
1071 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1076 readcount -= nbytes;
1077 } while (readcount);
1078 wcount -= blocksize;
1085 * Synchronously read a block of bytes into a buffer
1086 * @param swjdp The DAP connected to the MEM-AP.
1087 * @param buffer where the bytes will be stored.
1088 * @param count How many bytes to read.
1089 * @param address Memory address from which to read data; all the
1090 * data must be readable by the currently selected MEM-AP.
1092 int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
1093 int count, uint32_t address)
1096 int retval = ERROR_OK;
1099 return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
1103 dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
1104 retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
1105 retval = dap_run(swjdp);
1106 if (retval != ERROR_OK)
1109 *((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
1118 /*--------------------------------------------------------------------------*/
1120 static int jtag_idcode_q_read(struct adiv5_dap *dap,
1121 uint8_t *ack, uint32_t *data)
1123 struct arm_jtag *jtag_info = dap->jtag_info;
1125 struct scan_field fields[1];
1127 jtag_set_end_state(TAP_IDLE);
1129 /* This is a standard JTAG operation -- no DAP tweakage */
1130 retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
1131 if (retval != ERROR_OK)
1134 fields[0].tap = jtag_info->tap;
1135 fields[0].num_bits = 32;
1136 fields[0].out_value = NULL;
1137 fields[0].in_value = (void *) data;
1139 jtag_add_dr_scan(1, fields, jtag_get_end_state());
1140 retval = jtag_get_error();
1141 if (retval != ERROR_OK)
1144 jtag_add_callback(arm_le_to_h_u32,
1145 (jtag_callback_data_t) data);
1150 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
1153 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
1154 reg, DPAP_READ, 0, data);
1157 static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
1160 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
1161 reg, DPAP_WRITE, data, NULL);
1164 /** Select the AP register bank matching bits 7:4 of reg. */
1165 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
1167 uint32_t select = reg & 0x000000F0;
1169 if (select == dap->ap_bank_value)
1171 dap->ap_bank_value = select;
1173 select |= dap->apsel;
1175 return jtag_dp_q_write(dap, DP_SELECT, select);
1178 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
1181 int retval = jtag_ap_q_bankselect(dap, reg);
1183 if (retval != ERROR_OK)
1186 return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
1187 DPAP_READ, 0, data);
1190 static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
1193 uint8_t out_value_buf[4];
1195 int retval = jtag_ap_q_bankselect(dap, reg);
1196 if (retval != ERROR_OK)
1199 buf_set_u32(out_value_buf, 0, 32, data);
1201 return adi_jtag_ap_write_check(dap, reg, out_value_buf);
1204 static int jtag_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
1206 /* for JTAG, this is the only valid ABORT register operation */
1207 return adi_jtag_dp_scan_u32(dap, JTAG_DP_ABORT,
1208 0, DPAP_WRITE, 1, NULL, ack);
1211 static int jtag_dp_run(struct adiv5_dap *dap)
1213 return jtagdp_transaction_endcheck(dap);
1216 static const struct dap_ops jtag_dp_ops = {
1217 .queue_idcode_read = jtag_idcode_q_read,
1218 .queue_dp_read = jtag_dp_q_read,
1219 .queue_dp_write = jtag_dp_q_write,
1220 .queue_ap_read = jtag_ap_q_read,
1221 .queue_ap_write = jtag_ap_q_write,
1222 .queue_ap_abort = jtag_ap_q_abort,
1226 /*--------------------------------------------------------------------------*/
1229 * Initialize a DAP. This sets up the power domains, prepares the DP
1230 * for further use, and arranges to use AP #0 for all AP operations
1231 * until dap_ap-select() changes that policy.
1233 * @param swjdp The DAP being initialized.
1235 * @todo Rename this. We also need an initialization scheme which account
1236 * for SWD transports not just JTAG; that will need to address differences
1237 * in layering. (JTAG is useful without any debug target; but not SWD.)
1238 * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
1240 int ahbap_debugport_init(struct adiv5_dap *swjdp)
1242 uint32_t idreg, romaddr, dummy;
1249 /* JTAG-DP or SWJ-DP, in JTAG mode */
1250 swjdp->ops = &jtag_dp_ops;
1252 /* Default MEM-AP setup.
1254 * REVISIT AP #0 may be an inappropriate default for this.
1255 * Should we probe, or take a hint from the caller?
1256 * Presumably we can ignore the possibility of multiple APs.
1259 dap_ap_select(swjdp, 0);
1261 /* DP initialization */
1263 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1264 if (retval != ERROR_OK)
1267 retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
1268 if (retval != ERROR_OK)
1271 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1272 if (retval != ERROR_OK)
1275 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
1276 retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
1277 if (retval != ERROR_OK)
1280 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1281 if (retval != ERROR_OK)
1283 if ((retval = dap_run(swjdp)) != ERROR_OK)
1286 /* Check that we have debug power domains activated */
1287 while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
1289 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
1290 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1291 if (retval != ERROR_OK)
1293 if ((retval = dap_run(swjdp)) != ERROR_OK)
1298 while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
1300 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
1301 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
1302 if (retval != ERROR_OK)
1304 if ((retval = dap_run(swjdp)) != ERROR_OK)
1309 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1310 if (retval != ERROR_OK)
1312 /* With debug power on we can activate OVERRUN checking */
1313 swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
1314 retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
1315 if (retval != ERROR_OK)
1317 retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
1318 if (retval != ERROR_OK)
1322 * REVISIT this isn't actually *initializing* anything in an AP,
1323 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
1324 * Should it? If the ROM address is valid, is this the right
1325 * place to scan the table and do any topology detection?
1327 retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &idreg);
1328 retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &romaddr);
1330 LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
1331 ", Debug ROM Address 0x%" PRIx32,
1332 swjdp->apsel, idreg, romaddr);
1337 /* CID interpretation -- see ARM IHI 0029B section 3
1338 * and ARM IHI 0031A table 13-3.
1340 static const char *class_description[16] ={
1341 "Reserved", "ROM table", "Reserved", "Reserved",
1342 "Reserved", "Reserved", "Reserved", "Reserved",
1343 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
1344 "Reserved", "OptimoDE DESS",
1345 "Generic IP component", "PrimeCell or System component"
1349 is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
1351 return cid3 == 0xb1 && cid2 == 0x05
1352 && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
1355 int dap_info_command(struct command_context *cmd_ctx,
1356 struct adiv5_dap *swjdp, int apsel)
1359 uint32_t dbgbase, apid;
1360 int romtable_present = 0;
1364 /* AP address is in bits 31:24 of DP_SELECT */
1366 return ERROR_INVALID_ARGUMENTS;
1368 apselold = swjdp->apsel;
1369 dap_ap_select(swjdp, apsel);
1370 retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &dbgbase);
1371 retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
1372 retval = dap_run(swjdp);
1373 if (retval != ERROR_OK)
1376 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1377 mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1378 command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1384 command_print(cmd_ctx, "\tType is JTAG-AP");
1387 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1390 command_print(cmd_ctx, "\tType is MEM-AP APB");
1393 command_print(cmd_ctx, "\tUnknown AP type");
1397 /* NOTE: a MEM-AP may have a single CoreSight component that's
1398 * not a ROM table ... or have no such components at all.
1401 command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
1406 command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
1409 romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1410 if (romtable_present)
1412 uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
1413 uint16_t entry_offset;
1415 /* bit 16 of apid indicates a memory access port */
1417 command_print(cmd_ctx, "\tValid ROM table present");
1419 command_print(cmd_ctx, "\tROM table in legacy format");
1421 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1422 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
1423 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
1424 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
1425 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
1426 mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
1427 retval = dap_run(swjdp);
1428 if (retval != ERROR_OK)
1431 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1432 command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
1433 ", CID2 0x%2.2" PRIx32
1434 ", CID1 0x%2.2" PRIx32
1435 ", CID0 0x%2.2" PRIx32,
1436 cid3, cid2, cid1, cid0);
1438 command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
1440 command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
1441 "Dedicated debug bus.");
1443 /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
1447 mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
1448 command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
1451 uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
1452 uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
1453 uint32_t component_start, component_base;
1457 component_base = (uint32_t)((dbgbase & 0xFFFFF000)
1458 + (int)(romentry & 0xFFFFF000));
1459 mem_ap_read_atomic_u32(swjdp,
1460 (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
1461 mem_ap_read_atomic_u32(swjdp,
1462 (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
1463 mem_ap_read_atomic_u32(swjdp,
1464 (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
1465 mem_ap_read_atomic_u32(swjdp,
1466 (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
1467 mem_ap_read_atomic_u32(swjdp,
1468 (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
1469 mem_ap_read_atomic_u32(swjdp,
1470 (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
1471 mem_ap_read_atomic_u32(swjdp,
1472 (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
1473 mem_ap_read_atomic_u32(swjdp,
1474 (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
1475 mem_ap_read_atomic_u32(swjdp,
1476 (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
1477 component_start = component_base - 0x1000*(c_pid4 >> 4);
1479 command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
1480 ", start address 0x%" PRIx32,
1481 component_base, component_start);
1482 command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
1483 (int) (c_cid1 >> 4) & 0xf,
1484 /* See ARM IHI 0029B Table 3-3 */
1485 class_description[(c_cid1 >> 4) & 0xf]);
1487 /* CoreSight component? */
1488 if (((c_cid1 >> 4) & 0x0f) == 9) {
1491 char *major = "Reserved", *subtype = "Reserved";
1493 mem_ap_read_atomic_u32(swjdp,
1494 (component_base & 0xfffff000) | 0xfcc,
1496 minor = (devtype >> 4) & 0x0f;
1497 switch (devtype & 0x0f) {
1499 major = "Miscellaneous";
1505 subtype = "Validation component";
1510 major = "Trace Sink";
1524 major = "Trace Link";
1530 subtype = "Funnel, router";
1536 subtype = "FIFO, buffer";
1541 major = "Trace Source";
1547 subtype = "Processor";
1553 subtype = "Engine/Coprocessor";
1561 major = "Debug Control";
1567 subtype = "Trigger Matrix";
1570 subtype = "Debug Auth";
1575 major = "Debug Logic";
1581 subtype = "Processor";
1587 subtype = "Engine/Coprocessor";
1592 command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
1593 (unsigned) (devtype & 0xff),
1595 /* REVISIT also show 0xfc8 DevId */
1598 if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1599 command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
1600 ", CID2 0x%2.2" PRIx32
1601 ", CID1 0x%2.2" PRIx32
1602 ", CID0 0x%2.2" PRIx32,
1603 c_cid3, c_cid2, c_cid1, c_cid0);
1604 command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
1605 "%2.2x %2.2x %2.2x %2.2x %2.2x",
1607 (int) c_pid3, (int) c_pid2,
1608 (int) c_pid1, (int) c_pid0);
1610 /* Part number interpretations are from Cortex
1611 * core specs, the CoreSight components TRM
1612 * (ARM DDI 0314H), and ETM specs; also from
1613 * chip observation (e.g. TI SDTI).
1615 part_num = c_pid0 & 0xff;
1616 part_num |= (c_pid1 & 0x0f) << 8;
1619 type = "Cortex-M3 NVIC";
1620 full = "(Interrupt Controller)";
1623 type = "Cortex-M3 ITM";
1624 full = "(Instrumentation Trace Module)";
1627 type = "Cortex-M3 DWT";
1628 full = "(Data Watchpoint and Trace)";
1631 type = "Cortex-M3 FBP";
1632 full = "(Flash Patch and Breakpoint)";
1635 type = "CoreSight ETM11";
1636 full = "(Embedded Trace)";
1638 // case 0x113: what?
1639 case 0x120: /* from OMAP3 memmap */
1641 full = "(System Debug Trace Interface)";
1643 case 0x343: /* from OMAP3 memmap */
1648 type = "Coresight CTI";
1649 full = "(Cross Trigger)";
1652 type = "Coresight ETB";
1653 full = "(Trace Buffer)";
1656 type = "Coresight CSTF";
1657 full = "(Trace Funnel)";
1660 type = "CoreSight ETM9";
1661 full = "(Embedded Trace)";
1664 type = "Coresight TPIU";
1665 full = "(Trace Port Interface Unit)";
1668 type = "Cortex-A8 ETM";
1669 full = "(Embedded Trace)";
1672 type = "Cortex-A8 CTI";
1673 full = "(Cross Trigger)";
1676 type = "Cortex-M3 TPIU";
1677 full = "(Trace Port Interface Unit)";
1680 type = "Cortex-M3 ETM";
1681 full = "(Embedded Trace)";
1684 type = "Cortex-A8 Debug";
1685 full = "(Debug Unit)";
1688 type = "-*- unrecognized -*-";
1692 command_print(cmd_ctx, "\t\tPart is %s %s",
1698 command_print(cmd_ctx, "\t\tComponent not present");
1700 command_print(cmd_ctx, "\t\tEnd of ROM table");
1703 } while (romentry > 0);
1707 command_print(cmd_ctx, "\tNo ROM table present");
1709 dap_ap_select(swjdp, apselold);
1714 DAP_COMMAND_HANDLER(dap_baseaddr_command)
1716 uint32_t apsel, apselsave, baseaddr;
1719 apselsave = swjdp->apsel;
1722 apsel = swjdp->apsel;
1725 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1726 /* AP address is in bits 31:24 of DP_SELECT */
1728 return ERROR_INVALID_ARGUMENTS;
1731 return ERROR_COMMAND_SYNTAX_ERROR;
1734 if (apselsave != apsel)
1735 dap_ap_select(swjdp, apsel);
1737 /* NOTE: assumes we're talking to a MEM-AP, which
1738 * has a base address. There are other kinds of AP,
1739 * though they're not common for now. This should
1740 * use the ID register to verify it's a MEM-AP.
1742 retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &baseaddr);
1743 retval = dap_run(swjdp);
1744 if (retval != ERROR_OK)
1747 command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1749 if (apselsave != apsel)
1750 dap_ap_select(swjdp, apselsave);
1755 DAP_COMMAND_HANDLER(dap_memaccess_command)
1757 uint32_t memaccess_tck;
1761 memaccess_tck = swjdp->memaccess_tck;
1764 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1767 return ERROR_COMMAND_SYNTAX_ERROR;
1769 swjdp->memaccess_tck = memaccess_tck;
1771 command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1772 swjdp->memaccess_tck);
1777 DAP_COMMAND_HANDLER(dap_apsel_command)
1779 uint32_t apsel, apid;
1787 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1788 /* AP address is in bits 31:24 of DP_SELECT */
1790 return ERROR_INVALID_ARGUMENTS;
1793 return ERROR_COMMAND_SYNTAX_ERROR;
1796 dap_ap_select(swjdp, apsel);
1797 retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
1798 retval = dap_run(swjdp);
1799 if (retval != ERROR_OK)
1802 command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1808 DAP_COMMAND_HANDLER(dap_apid_command)
1810 uint32_t apsel, apselsave, apid;
1813 apselsave = swjdp->apsel;
1816 apsel = swjdp->apsel;
1819 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1820 /* AP address is in bits 31:24 of DP_SELECT */
1822 return ERROR_INVALID_ARGUMENTS;
1825 return ERROR_COMMAND_SYNTAX_ERROR;
1828 if (apselsave != apsel)
1829 dap_ap_select(swjdp, apsel);
1831 retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
1832 retval = dap_run(swjdp);
1833 if (retval != ERROR_OK)
1836 command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1837 if (apselsave != apsel)
1838 dap_ap_select(swjdp, apselsave);
1844 * This represents the bits which must be sent out on TMS/SWDIO to
1845 * switch a DAP implemented using an SWJ-DP module into SWD mode.
1846 * These bits are stored (and transmitted) LSB-first.
1848 * See the DAP-Lite specification, section 2.2.5 for information
1849 * about making the debug link select SWD or JTAG. (Similar info
1850 * is in a few other ARM documents.)
1852 static const uint8_t jtag2swd_bitseq[] = {
1853 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1854 * putting both JTAG and SWD logic into reset state.
1856 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1857 /* Switching sequence enables SWD and disables JTAG
1858 * NOTE: bits in the DP's IDCODE may expose the need for
1859 * an old/deprecated sequence (0xb6 0xed).
1862 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1863 * putting both JTAG and SWD logic into reset state.
1865 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1869 * Put the debug link into SWD mode, if the target supports it.
1870 * The link's initial mode may be either JTAG (for example,
1871 * with SWJ-DP after reset) or SWD.
1873 * @param target Enters SWD mode (if possible).
1875 * Note that targets using the JTAG-DP do not support SWD, and that
1876 * some targets which could otherwise support it may have have been
1877 * configured to disable SWD signaling
1879 * @return ERROR_OK or else a fault code.
1881 int dap_to_swd(struct target *target)
1885 LOG_DEBUG("Enter SWD mode");
1887 /* REVISIT it's nasty to need to make calls to a "jtag"
1888 * subsystem if the link isn't in JTAG mode...
1891 retval = jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
1892 jtag2swd_bitseq, TAP_INVALID);
1893 if (retval == ERROR_OK)
1894 retval = jtag_execute_queue();
1896 /* REVISIT set up the DAP's ops vector for SWD mode. */
1902 * This represents the bits which must be sent out on TMS/SWDIO to
1903 * switch a DAP implemented using an SWJ-DP module into JTAG mode.
1904 * These bits are stored (and transmitted) LSB-first.
1906 * These bits are stored (and transmitted) LSB-first.
1908 static const uint8_t swd2jtag_bitseq[] = {
1909 /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
1910 * putting both JTAG and SWD logic into reset state.
1912 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1913 /* Switching equence disables SWD and enables JTAG
1914 * NOTE: bits in the DP's IDCODE can expose the need for
1915 * the old/deprecated sequence (0xae 0xde).
1918 /* At least 50 TCK/SWCLK cycles with TMS/SWDIO high,
1919 * putting both JTAG and SWD logic into reset state.
1920 * NOTE: some docs say "at least 5".
1922 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1925 /** Put the debug link into JTAG mode, if the target supports it.
1926 * The link's initial mode may be either SWD or JTAG.
1928 * @param target Enters JTAG mode (if possible).
1930 * Note that targets implemented with SW-DP do not support JTAG, and
1931 * that some targets which could otherwise support it may have been
1932 * configured to disable JTAG signaling
1934 * @return ERROR_OK or else a fault code.
1936 int dap_to_jtag(struct target *target)
1940 LOG_DEBUG("Enter JTAG mode");
1942 /* REVISIT it's nasty to need to make calls to a "jtag"
1943 * subsystem if the link isn't in JTAG mode...
1946 retval = jtag_add_tms_seq(8 * sizeof(swd2jtag_bitseq),
1947 swd2jtag_bitseq, TAP_RESET);
1948 if (retval == ERROR_OK)
1949 retval = jtag_execute_queue();
1951 /* REVISIT set up the DAP's ops vector for JTAG mode. */