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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, MEM_AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, MEM_AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 static int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, MEM_AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 static int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 static int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, MEM_AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 static int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 static int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         uint32_t addr_xor;
 299         int retval;
 300
 301         /* TI BE-32 Quirks mode:
 302          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 303          *   size   write address   bytes written in order
 304          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 305          *   2      TAR ^ 2         (val >> 8), (val)
 306          *   1      TAR ^ 3         (val)
 307          * For example, if you attempt to write a single byte to address 0, the processor
 308          * will actually write a byte to address 3.
 309          *
 310          * To make writes of size < 4 work as expected, we xor a value with the address before
 311          * setting the TAP, and we set the TAP after every transfer rather then relying on
 312          * address increment. */
 313
 314         if (size == 4) {
 315                 csw_size = CSW_32BIT;
 316                 addr_xor = 0;
 317         } else if (size == 2) {
 318                 csw_size = CSW_16BIT;
 319                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 320         } else if (size == 1) {
 321                 csw_size = CSW_8BIT;
 322                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 323         } else {
 324                 return ERROR_TARGET_UNALIGNED_ACCESS;
 325         }
 326
 327         if (dap->unaligned_access_bad && (address % size != 0))
 328                 return ERROR_TARGET_UNALIGNED_ACCESS;
 329
 330         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         while (nbytes > 0) {
 335                 uint32_t this_size = size;
 336
 337                 /* Select packed transfer if possible */
 338                 if (addrinc && dap->packed_transfers && nbytes >= 4
 339                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 340                         this_size = 4;
 341                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 342                 } else {
 343                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 344                 }
 345
 346                 if (retval != ERROR_OK)
 347                         break;
 348
 349                 /* How many source bytes each transfer will consume, and their location in the DRW,
 350                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 351                 uint32_t outvalue = 0;
 352                 if (dap->ti_be_32_quirks) {
 353                         switch (this_size) {
 354                         case 4:
 355                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 356                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 357                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 358                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 359                                 break;
 360                         case 2:
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 1:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 366                                 break;
 367                         }
 368                 } else {
 369                         switch (this_size) {
 370                         case 4:
 371                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 372                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 373                         case 2:
 374                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 375                         case 1:
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         }
 378                 }
 379
 380                 nbytes -= this_size;
 381
 382                 retval = dap_queue_ap_write(dap, MEM_AP_REG_DRW, outvalue);
 383                 if (retval != ERROR_OK)
 384                         break;
 385
 386                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 387                 if (addrinc && (addr_xor || (address % dap->tar_autoincr_block < size && nbytes > 0))) {
 388                         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 389                         if (retval != ERROR_OK)
 390                                 break;
 391                 }
 392         }
 393
 394         /* REVISIT: Might want to have a queued version of this function that does not run. */
 395         if (retval == ERROR_OK)
 396                 retval = dap_run(dap);
 397
 398         if (retval != ERROR_OK) {
 399                 uint32_t tar;
 400                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 401                                 && dap_run(dap) == ERROR_OK)
 402                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 403                 else
 404                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 405         }
 406
 407         return retval;
 408 }
 409
 410 /**
 411  * Synchronous read of a block of memory, using a specific access size.
 412  *
 413  * @param dap The DAP connected to the MEM-AP.
 414  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 415  * @param size Which access size to use, in bytes. 1, 2 or 4.
 416  * @param count The number of reads to do (in size units, not bytes).
 417  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 418  * @param addrinc Whether the target address should be increased after each read or not. This
 419  *  should normally be true, except when reading from e.g. a FIFO.
 420  * @return ERROR_OK on success, otherwise an error code.
 421  */
 422 static int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 423                 uint32_t adr, bool addrinc)
 424 {
 425         size_t nbytes = size * count;
 426         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 427         uint32_t csw_size;
 428         uint32_t address = adr;
 429         int retval;
 430
 431         /* TI BE-32 Quirks mode:
 432          * Reads on big-endian TMS570 behave strangely differently than writes.
 433          * They read from the physical address requested, but with DRW byte-reversed.
 434          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 435          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 436          * so avoid them. */
 437
 438         if (size == 4)
 439                 csw_size = CSW_32BIT;
 440         else if (size == 2)
 441                 csw_size = CSW_16BIT;
 442         else if (size == 1)
 443                 csw_size = CSW_8BIT;
 444         else
 445                 return ERROR_TARGET_UNALIGNED_ACCESS;
 446
 447         if (dap->unaligned_access_bad && (adr % size != 0))
 448                 return ERROR_TARGET_UNALIGNED_ACCESS;
 449
 450         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 451          * over-allocation if packed transfers are going to be used, but determining the real need at
 452          * this point would be messy. */
 453         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 454         uint32_t *read_ptr = read_buf;
 455         if (read_buf == NULL) {
 456                 LOG_ERROR("Failed to allocate read buffer");
 457                 return ERROR_FAIL;
 458         }
 459
 460         retval = dap_setup_accessport_tar(dap, address);
 461         if (retval != ERROR_OK) {
 462                 free(read_buf);
 463                 return retval;
 464         }
 465
 466         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 467          * useful bytes it contains, and their location in the word, depends on the type of transfer
 468          * and alignment. */
 469         while (nbytes > 0) {
 470                 uint32_t this_size = size;
 471
 472                 /* Select packed transfer if possible */
 473                 if (addrinc && dap->packed_transfers && nbytes >= 4
 474                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 475                         this_size = 4;
 476                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 477                 } else {
 478                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 479                 }
 480                 if (retval != ERROR_OK)
 481                         break;
 482
 483                 retval = dap_queue_ap_read(dap, MEM_AP_REG_DRW, read_ptr++);
 484                 if (retval != ERROR_OK)
 485                         break;
 486
 487                 nbytes -= this_size;
 488                 address += this_size;
 489
 490                 /* Rewrite TAR if it wrapped */
 491                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 492                         retval = dap_setup_accessport_tar(dap, address);
 493                         if (retval != ERROR_OK)
 494                                 break;
 495                 }
 496         }
 497
 498         if (retval == ERROR_OK)
 499                 retval = dap_run(dap);
 500
 501         /* Restore state */
 502         address = adr;
 503         nbytes = size * count;
 504         read_ptr = read_buf;
 505
 506         /* If something failed, read TAR to find out how much data was successfully read, so we can
 507          * at least give the caller what we have. */
 508         if (retval != ERROR_OK) {
 509                 uint32_t tar;
 510                 if (dap_queue_ap_read(dap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 511                                 && dap_run(dap) == ERROR_OK) {
 512                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 513                         if (nbytes > tar - address)
 514                                 nbytes = tar - address;
 515                 } else {
 516                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 517                         nbytes = 0;
 518                 }
 519         }
 520
 521         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 522         while (nbytes > 0) {
 523                 uint32_t this_size = size;
 524
 525                 if (addrinc && dap->packed_transfers && nbytes >= 4
 526                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 527                         this_size = 4;
 528                 }
 529
 530                 if (dap->ti_be_32_quirks) {
 531                         switch (this_size) {
 532                         case 4:
 533                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 534                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 535                         case 2:
 536                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 537                         case 1:
 538                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 539                         }
 540                 } else {
 541                         switch (this_size) {
 542                         case 4:
 543                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 544                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 545                         case 2:
 546                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 547                         case 1:
 548                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 549                         }
 550                 }
 551
 552                 read_ptr++;
 553                 nbytes -= this_size;
 554         }
 555
 556         free(read_buf);
 557         return retval;
 558 }
 559
 560 /*--------------------------------------------------------------------*/
 561 /*          Wrapping function with selection of AP                    */
 562 /*--------------------------------------------------------------------*/
 563 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 564                 uint32_t address, uint32_t *value)
 565 {
 566         dap_ap_select(swjdp, ap);
 567         return mem_ap_read_u32(swjdp, address, value);
 568 }
 569
 570 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 571                 uint32_t address, uint32_t value)
 572 {
 573         dap_ap_select(swjdp, ap);
 574         return mem_ap_write_u32(swjdp, address, value);
 575 }
 576
 577 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 578                 uint32_t address, uint32_t *value)
 579 {
 580         dap_ap_select(swjdp, ap);
 581         return mem_ap_read_atomic_u32(swjdp, address, value);
 582 }
 583
 584 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 585                 uint32_t address, uint32_t value)
 586 {
 587         dap_ap_select(swjdp, ap);
 588         return mem_ap_write_atomic_u32(swjdp, address, value);
 589 }
 590
 591 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
 592                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 593 {
 594         dap_ap_select(swjdp, ap);
 595         return mem_ap_read(swjdp, buffer, size, count, address, true);
 596 }
 597
 598 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
 599                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 600 {
 601         dap_ap_select(swjdp, ap);
 602         return mem_ap_write(swjdp, buffer, size, count, address, true);
 603 }
 604
 605 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 606                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 607 {
 608         dap_ap_select(swjdp, ap);
 609         return mem_ap_read(swjdp, buffer, size, count, address, false);
 610 }
 611
 612 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 613                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 614 {
 615         dap_ap_select(swjdp, ap);
 616         return mem_ap_write(swjdp, buffer, size, count, address, false);
 617 }
 618
 619 /*--------------------------------------------------------------------------*/
 620
 621
 622 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 623
 624 /* FIXME don't import ... just initialize as
 625  * part of DAP transport setup
 626 */
 627 extern const struct dap_ops jtag_dp_ops;
 628
 629 /*--------------------------------------------------------------------------*/
 630
 631 /**
 632  * Initialize a DAP.  This sets up the power domains, prepares the DP
 633  * for further use, and arranges to use AP #0 for all AP operations
 634  * until dap_ap-select() changes that policy.
 635  *
 636  * @param dap The DAP being initialized.
 637  *
 638  * @todo Rename this.  We also need an initialization scheme which account
 639  * for SWD transports not just JTAG; that will need to address differences
 640  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 641  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 642  */
 643 int ahbap_debugport_init(struct adiv5_dap *dap, uint8_t apsel)
 644 {
 645         /* check that we support packed transfers */
 646         uint32_t csw, cfg;
 647         int retval;
 648
 649         LOG_DEBUG(" ");
 650
 651         /* JTAG-DP or SWJ-DP, in JTAG mode
 652          * ... for SWD mode this is patched as part
 653          * of link switchover
 654          */
 655         if (!dap->ops)
 656                 dap->ops = &jtag_dp_ops;
 657
 658         /* Default MEM-AP setup.
 659          *
 660          * REVISIT AP #0 may be an inappropriate default for this.
 661          * Should we probe, or take a hint from the caller?
 662          * Presumably we can ignore the possibility of multiple APs.
 663          */
 664         dap->ap_current = -1;
 665         dap_ap_select(dap, apsel);
 666         dap->last_read = NULL;
 667
 668         for (size_t i = 0; i < 10; i++) {
 669                 /* DP initialization */
 670
 671                 dap->dp_bank_value = 0;
 672
 673                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 674                 if (retval != ERROR_OK)
 675                         continue;
 676
 677                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 678                 if (retval != ERROR_OK)
 679                         continue;
 680
 681                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 682                 if (retval != ERROR_OK)
 683                         continue;
 684
 685                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 686                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 687                 if (retval != ERROR_OK)
 688                         continue;
 689
 690                 /* Check that we have debug power domains activated */
 691                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 692                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 693                                               CDBGPWRUPACK, CDBGPWRUPACK,
 694                                               DAP_POWER_DOMAIN_TIMEOUT);
 695                 if (retval != ERROR_OK)
 696                         continue;
 697
 698                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 699                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 700                                               CSYSPWRUPACK, CSYSPWRUPACK,
 701                                               DAP_POWER_DOMAIN_TIMEOUT);
 702                 if (retval != ERROR_OK)
 703                         continue;
 704
 705                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 706                 if (retval != ERROR_OK)
 707                         continue;
 708                 /* With debug power on we can activate OVERRUN checking */
 709                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 710                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 711                 if (retval != ERROR_OK)
 712                         continue;
 713                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 714                 if (retval != ERROR_OK)
 715                         continue;
 716
 717                 retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 718                 if (retval != ERROR_OK)
 719                         continue;
 720
 721                 retval = dap_queue_ap_read(dap, MEM_AP_REG_CSW, &csw);
 722                 if (retval != ERROR_OK)
 723                         continue;
 724
 725                 retval = dap_queue_ap_read(dap, MEM_AP_REG_CFG, &cfg);
 726                 if (retval != ERROR_OK)
 727                         continue;
 728
 729                 retval = dap_run(dap);
 730                 if (retval != ERROR_OK)
 731                         continue;
 732
 733                 break;
 734         }
 735
 736         if (retval != ERROR_OK)
 737                 return retval;
 738
 739         if (csw & CSW_ADDRINC_PACKED)
 740                 dap->packed_transfers = true;
 741         else
 742                 dap->packed_transfers = false;
 743
 744         /* Packed transfers on TI BE-32 processors do not work correctly in
 745          * many cases. */
 746         if (dap->ti_be_32_quirks)
 747                 dap->packed_transfers = false;
 748
 749         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 750                         dap->packed_transfers ? "enabled" : "disabled");
 751
 752         /* The ARM ADI spec leaves implementation-defined whether unaligned
 753          * memory accesses work, only work partially, or cause a sticky error.
 754          * On TI BE-32 processors, reads seem to return garbage in some bytes
 755          * and unaligned writes seem to cause a sticky error.
 756          * TODO: it would be nice to have a way to detect whether unaligned
 757          * operations are supported on other processors. */
 758         dap->unaligned_access_bad = dap->ti_be_32_quirks;
 759
 760         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 761                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 762
 763         return ERROR_OK;
 764 }
 765
 766 /* CID interpretation -- see ARM IHI 0029B section 3
 767  * and ARM IHI 0031A table 13-3.
 768  */
 769 static const char *class_description[16] = {
 770         "Reserved", "ROM table", "Reserved", "Reserved",
 771         "Reserved", "Reserved", "Reserved", "Reserved",
 772         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 773         "Reserved", "OptimoDE DESS",
 774         "Generic IP component", "PrimeCell or System component"
 775 };
 776
 777 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 778 {
 779         return cid3 == 0xb1 && cid2 == 0x05
 780                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 781 }
 782
 783 /*
 784  * This function checks the ID for each access port to find the requested Access Port type
 785  */
 786 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 787 {
 788         int ap;
 789
 790         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 791         for (ap = 0; ap <= 255; ap++) {
 792
 793                 /* read the IDR register of the Access Port */
 794                 uint32_t id_val = 0;
 795                 dap_ap_select(dap, ap);
 796
 797                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 798                 if (retval != ERROR_OK)
 799                         return retval;
 800
 801                 retval = dap_run(dap);
 802
 803                 /* IDR bits:
 804                  * 31-28 : Revision
 805                  * 27-24 : JEDEC bank (0x4 for ARM)
 806                  * 23-17 : JEDEC code (0x3B for ARM)
 807                  * 16    : Mem-AP
 808                  * 15-8  : Reserved
 809                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 810                  */
 811
 812                 /* Reading register for a non-existant AP should not cause an error,
 813                  * but just to be sure, try to continue searching if an error does happen.
 814                  */
 815                 if ((retval == ERROR_OK) &&                  /* Register read success */
 816                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 817                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 818
 819                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 820                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 821                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 822                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 823                                                 ap, id_val);
 824
 825                         *ap_num_out = ap;
 826                         return ERROR_OK;
 827                 }
 828         }
 829
 830         LOG_DEBUG("No %s found",
 831                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 832                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 833                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 834         return ERROR_FAIL;
 835 }
 836
 837 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 838                         uint32_t *dbgbase, uint32_t *apid)
 839 {
 840         uint32_t ap_old;
 841         int retval;
 842
 843         /* AP address is in bits 31:24 of DP_SELECT */
 844         if (ap >= 256)
 845                 return ERROR_COMMAND_SYNTAX_ERROR;
 846
 847         ap_old = dap_ap_get_select(dap);
 848         dap_ap_select(dap, ap);
 849
 850         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, dbgbase);
 851         if (retval != ERROR_OK)
 852                 return retval;
 853         retval = dap_queue_ap_read(dap, AP_REG_IDR, apid);
 854         if (retval != ERROR_OK)
 855                 return retval;
 856         retval = dap_run(dap);
 857         if (retval != ERROR_OK)
 858                 return retval;
 859
 860         dap_ap_select(dap, ap_old);
 861
 862         return ERROR_OK;
 863 }
 864
 865 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 866                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
 867 {
 868         uint32_t ap_old;
 869         uint32_t romentry, entry_offset = 0, component_base, devtype;
 870         int retval;
 871
 872         if (ap >= 256)
 873                 return ERROR_COMMAND_SYNTAX_ERROR;
 874
 875         *addr = 0;
 876         ap_old = dap_ap_get_select(dap);
 877         dap_ap_select(dap, ap);
 878
 879         do {
 880                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
 881                                                 entry_offset, &romentry);
 882                 if (retval != ERROR_OK)
 883                         return retval;
 884
 885                 component_base = (dbgbase & 0xFFFFF000)
 886                         + (romentry & 0xFFFFF000);
 887
 888                 if (romentry & 0x1) {
 889                         uint32_t c_cid1;
 890                         retval = mem_ap_read_atomic_u32(dap, component_base | 0xff4, &c_cid1);
 891                         if (retval != ERROR_OK) {
 892                                 LOG_ERROR("Can't read component with base address 0x%" PRIx32
 893                                           ", the corresponding core might be turned off", component_base);
 894                                 return retval;
 895                         }
 896                         if (((c_cid1 >> 4) & 0x0f) == 1) {
 897                                 retval = dap_lookup_cs_component(dap, ap, component_base,
 898                                                         type, addr, idx);
 899                                 if (retval == ERROR_OK)
 900                                         break;
 901                                 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 902                                         return retval;
 903                         }
 904
 905                         retval = mem_ap_read_atomic_u32(dap,
 906                                         (component_base & 0xfffff000) | 0xfcc,
 907                                         &devtype);
 908                         if (retval != ERROR_OK)
 909                                 return retval;
 910                         if ((devtype & 0xff) == type) {
 911                                 if (!*idx) {
 912                                         *addr = component_base;
 913                                         break;
 914                                 } else
 915                                         (*idx)--;
 916                         }
 917                 }
 918                 entry_offset += 4;
 919         } while (romentry > 0);
 920
 921         dap_ap_select(dap, ap_old);
 922
 923         if (!*addr)
 924                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 925
 926         return ERROR_OK;
 927 }
 928
 929 static int dap_rom_display(struct command_context *cmd_ctx,
 930                                 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
 931 {
 932         int retval;
 933         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 934         uint16_t entry_offset;
 935         char tabs[7] = "";
 936
 937         if (depth > 16) {
 938                 command_print(cmd_ctx, "\tTables too deep");
 939                 return ERROR_FAIL;
 940         }
 941
 942         if (depth)
 943                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 944
 945         /* bit 16 of apid indicates a memory access port */
 946         if (dbgbase & 0x02)
 947                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 948         else
 949                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 950
 951         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 952         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 953         if (retval != ERROR_OK)
 954                 return retval;
 955         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 956         if (retval != ERROR_OK)
 957                 return retval;
 958         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 962         if (retval != ERROR_OK)
 963                 return retval;
 964         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 965         if (retval != ERROR_OK)
 966                 return retval;
 967         retval = dap_run(dap);
 968         if (retval != ERROR_OK)
 969                 return retval;
 970
 971         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 972                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 973                                 ", CID2 0x%02x"
 974                                 ", CID1 0x%02x"
 975                                 ", CID0 0x%02x",
 976                                 tabs,
 977                                 (unsigned)cid3, (unsigned)cid2,
 978                                 (unsigned)cid1, (unsigned)cid0);
 979         if (memtype & 0x01)
 980                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
 981         else
 982                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
 983
 984         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
 985         for (entry_offset = 0; ; entry_offset += 4) {
 986                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 987                 if (retval != ERROR_OK)
 988                         return retval;
 989                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 990                                 tabs, entry_offset, romentry);
 991                 if (romentry & 0x01) {
 992                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
 993                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
 994                         uint32_t component_base;
 995                         uint32_t part_num;
 996                         const char *type, *full;
 997
 998                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
 999
1000                         /* IDs are in last 4K section */
1001                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1002                         if (retval != ERROR_OK) {
1003                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1004                                               ", the corresponding core might be turned off", tabs, component_base);
1005                                 continue;
1006                         }
1007                         c_pid0 &= 0xff;
1008                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1009                         if (retval != ERROR_OK)
1010                                 return retval;
1011                         c_pid1 &= 0xff;
1012                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1013                         if (retval != ERROR_OK)
1014                                 return retval;
1015                         c_pid2 &= 0xff;
1016                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1017                         if (retval != ERROR_OK)
1018                                 return retval;
1019                         c_pid3 &= 0xff;
1020                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1021                         if (retval != ERROR_OK)
1022                                 return retval;
1023                         c_pid4 &= 0xff;
1024
1025                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1026                         if (retval != ERROR_OK)
1027                                 return retval;
1028                         c_cid0 &= 0xff;
1029                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1030                         if (retval != ERROR_OK)
1031                                 return retval;
1032                         c_cid1 &= 0xff;
1033                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1034                         if (retval != ERROR_OK)
1035                                 return retval;
1036                         c_cid2 &= 0xff;
1037                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1038                         if (retval != ERROR_OK)
1039                                 return retval;
1040                         c_cid3 &= 0xff;
1041
1042                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1043                                       "start address 0x%" PRIx32, component_base,
1044                                       /* component may take multiple 4K pages */
1045                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1046                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1047                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1048                                         /* See ARM IHI 0029B Table 3-3 */
1049                                         class_description[(c_cid1 >> 4) & 0xf]);
1050
1051                         /* CoreSight component? */
1052                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1053                                 uint32_t devtype;
1054                                 unsigned minor;
1055                                 const char *major = "Reserved", *subtype = "Reserved";
1056
1057                                 retval = mem_ap_read_atomic_u32(dap,
1058                                                 (component_base & 0xfffff000) | 0xfcc,
1059                                                 &devtype);
1060                                 if (retval != ERROR_OK)
1061                                         return retval;
1062                                 minor = (devtype >> 4) & 0x0f;
1063                                 switch (devtype & 0x0f) {
1064                                 case 0:
1065                                         major = "Miscellaneous";
1066                                         switch (minor) {
1067                                         case 0:
1068                                                 subtype = "other";
1069                                                 break;
1070                                         case 4:
1071                                                 subtype = "Validation component";
1072                                                 break;
1073                                         }
1074                                         break;
1075                                 case 1:
1076                                         major = "Trace Sink";
1077                                         switch (minor) {
1078                                         case 0:
1079                                                 subtype = "other";
1080                                                 break;
1081                                         case 1:
1082                                                 subtype = "Port";
1083                                                 break;
1084                                         case 2:
1085                                                 subtype = "Buffer";
1086                                                 break;
1087                                         case 3:
1088                                                 subtype = "Router";
1089                                                 break;
1090                                         }
1091                                         break;
1092                                 case 2:
1093                                         major = "Trace Link";
1094                                         switch (minor) {
1095                                         case 0:
1096                                                 subtype = "other";
1097                                                 break;
1098                                         case 1:
1099                                                 subtype = "Funnel, router";
1100                                                 break;
1101                                         case 2:
1102                                                 subtype = "Filter";
1103                                                 break;
1104                                         case 3:
1105                                                 subtype = "FIFO, buffer";
1106                                                 break;
1107                                         }
1108                                         break;
1109                                 case 3:
1110                                         major = "Trace Source";
1111                                         switch (minor) {
1112                                         case 0:
1113                                                 subtype = "other";
1114                                                 break;
1115                                         case 1:
1116                                                 subtype = "Processor";
1117                                                 break;
1118                                         case 2:
1119                                                 subtype = "DSP";
1120                                                 break;
1121                                         case 3:
1122                                                 subtype = "Engine/Coprocessor";
1123                                                 break;
1124                                         case 4:
1125                                                 subtype = "Bus";
1126                                                 break;
1127                                         case 6:
1128                                                 subtype = "Software";
1129                                                 break;
1130                                         }
1131                                         break;
1132                                 case 4:
1133                                         major = "Debug Control";
1134                                         switch (minor) {
1135                                         case 0:
1136                                                 subtype = "other";
1137                                                 break;
1138                                         case 1:
1139                                                 subtype = "Trigger Matrix";
1140                                                 break;
1141                                         case 2:
1142                                                 subtype = "Debug Auth";
1143                                                 break;
1144                                         case 3:
1145                                                 subtype = "Power Requestor";
1146                                                 break;
1147                                         }
1148                                         break;
1149                                 case 5:
1150                                         major = "Debug Logic";
1151                                         switch (minor) {
1152                                         case 0:
1153                                                 subtype = "other";
1154                                                 break;
1155                                         case 1:
1156                                                 subtype = "Processor";
1157                                                 break;
1158                                         case 2:
1159                                                 subtype = "DSP";
1160                                                 break;
1161                                         case 3:
1162                                                 subtype = "Engine/Coprocessor";
1163                                                 break;
1164                                         case 4:
1165                                                 subtype = "Bus";
1166                                                 break;
1167                                         case 5:
1168                                                 subtype = "Memory";
1169                                                 break;
1170                                         }
1171                                         break;
1172                                 case 6:
1173                                         major = "Perfomance Monitor";
1174                                         switch (minor) {
1175                                         case 0:
1176                                                 subtype = "other";
1177                                                 break;
1178                                         case 1:
1179                                                 subtype = "Processor";
1180                                                 break;
1181                                         case 2:
1182                                                 subtype = "DSP";
1183                                                 break;
1184                                         case 3:
1185                                                 subtype = "Engine/Coprocessor";
1186                                                 break;
1187                                         case 4:
1188                                                 subtype = "Bus";
1189                                                 break;
1190                                         case 5:
1191                                                 subtype = "Memory";
1192                                                 break;
1193                                         }
1194                                         break;
1195                                 }
1196                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1197                                                 (uint8_t)(devtype & 0xff),
1198                                                 major, subtype);
1199                                 /* REVISIT also show 0xfc8 DevId */
1200                         }
1201
1202                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1203                                 command_print(cmd_ctx,
1204                                                 "\t\tCID3 0%02x"
1205                                                 ", CID2 0%02x"
1206                                                 ", CID1 0%02x"
1207                                                 ", CID0 0%02x",
1208                                                 (int)c_cid3,
1209                                                 (int)c_cid2,
1210                                                 (int)c_cid1,
1211                                                 (int)c_cid0);
1212                         command_print(cmd_ctx,
1213                                 "\t\tPeripheral ID[4..0] = hex "
1214                                 "%02x %02x %02x %02x %02x",
1215                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1216                                 (int)c_pid1, (int)c_pid0);
1217
1218                         /* Part number interpretations are from Cortex
1219                          * core specs, the CoreSight components TRM
1220                          * (ARM DDI 0314H), CoreSight System Design
1221                          * Guide (ARM DGI 0012D) and ETM specs; also
1222                          * from chip observation (e.g. TI SDTI).
1223                          */
1224                         part_num = (c_pid0 & 0xff);
1225                         part_num |= (c_pid1 & 0x0f) << 8;
1226                         switch (part_num) {
1227                         case 0x000:
1228                                 type = "Cortex-M3 NVIC";
1229                                 full = "(Interrupt Controller)";
1230                                 break;
1231                         case 0x001:
1232                                 type = "Cortex-M3 ITM";
1233                                 full = "(Instrumentation Trace Module)";
1234                                 break;
1235                         case 0x002:
1236                                 type = "Cortex-M3 DWT";
1237                                 full = "(Data Watchpoint and Trace)";
1238                                 break;
1239                         case 0x003:
1240                                 type = "Cortex-M3 FBP";
1241                                 full = "(Flash Patch and Breakpoint)";
1242                                 break;
1243                         case 0x008:
1244                                 type = "Cortex-M0 SCS";
1245                                 full = "(System Control Space)";
1246                                 break;
1247                         case 0x00a:
1248                                 type = "Cortex-M0 DWT";
1249                                 full = "(Data Watchpoint and Trace)";
1250                                 break;
1251                         case 0x00b:
1252                                 type = "Cortex-M0 BPU";
1253                                 full = "(Breakpoint Unit)";
1254                                 break;
1255                         case 0x00c:
1256                                 type = "Cortex-M4 SCS";
1257                                 full = "(System Control Space)";
1258                                 break;
1259                         case 0x00d:
1260                                 type = "CoreSight ETM11";
1261                                 full = "(Embedded Trace)";
1262                                 break;
1263                         /* case 0x113: what? */
1264                         case 0x120:             /* from OMAP3 memmap */
1265                                 type = "TI SDTI";
1266                                 full = "(System Debug Trace Interface)";
1267                                 break;
1268                         case 0x343:             /* from OMAP3 memmap */
1269                                 type = "TI DAPCTL";
1270                                 full = "";
1271                                 break;
1272                         case 0x906:
1273                                 type = "Coresight CTI";
1274                                 full = "(Cross Trigger)";
1275                                 break;
1276                         case 0x907:
1277                                 type = "Coresight ETB";
1278                                 full = "(Trace Buffer)";
1279                                 break;
1280                         case 0x908:
1281                                 type = "Coresight CSTF";
1282                                 full = "(Trace Funnel)";
1283                                 break;
1284                         case 0x910:
1285                                 type = "CoreSight ETM9";
1286                                 full = "(Embedded Trace)";
1287                                 break;
1288                         case 0x912:
1289                                 type = "Coresight TPIU";
1290                                 full = "(Trace Port Interface Unit)";
1291                                 break;
1292                         case 0x913:
1293                                 type = "Coresight ITM";
1294                                 full = "(Instrumentation Trace Macrocell)";
1295                                 break;
1296                         case 0x914:
1297                                 type = "Coresight SWO";
1298                                 full = "(Single Wire Output)";
1299                                 break;
1300                         case 0x917:
1301                                 type = "Coresight HTM";
1302                                 full = "(AHB Trace Macrocell)";
1303                                 break;
1304                         case 0x920:
1305                                 type = "CoreSight ETM11";
1306                                 full = "(Embedded Trace)";
1307                                 break;
1308                         case 0x921:
1309                                 type = "Cortex-A8 ETM";
1310                                 full = "(Embedded Trace)";
1311                                 break;
1312                         case 0x922:
1313                                 type = "Cortex-A8 CTI";
1314                                 full = "(Cross Trigger)";
1315                                 break;
1316                         case 0x923:
1317                                 type = "Cortex-M3 TPIU";
1318                                 full = "(Trace Port Interface Unit)";
1319                                 break;
1320                         case 0x924:
1321                                 type = "Cortex-M3 ETM";
1322                                 full = "(Embedded Trace)";
1323                                 break;
1324                         case 0x925:
1325                                 type = "Cortex-M4 ETM";
1326                                 full = "(Embedded Trace)";
1327                                 break;
1328                         case 0x930:
1329                                 type = "Cortex-R4 ETM";
1330                                 full = "(Embedded Trace)";
1331                                 break;
1332                         case 0x950:
1333                                 type = "CoreSight Component";
1334                                 full = "(unidentified Cortex-A9 component)";
1335                                 break;
1336                         case 0x961:
1337                                 type = "CoreSight TMC";
1338                                 full = "(Trace Memory Controller)";
1339                                 break;
1340                         case 0x962:
1341                                 type = "CoreSight STM";
1342                                 full = "(System Trace Macrocell)";
1343                                 break;
1344                         case 0x9a0:
1345                                 type = "CoreSight PMU";
1346                                 full = "(Performance Monitoring Unit)";
1347                                 break;
1348                         case 0x9a1:
1349                                 type = "Cortex-M4 TPUI";
1350                                 full = "(Trace Port Interface Unit)";
1351                                 break;
1352                         case 0x9a5:
1353                                 type = "Cortex-A5 ETM";
1354                                 full = "(Embedded Trace)";
1355                                 break;
1356                         case 0xc05:
1357                                 type = "Cortex-A5 Debug";
1358                                 full = "(Debug Unit)";
1359                                 break;
1360                         case 0xc08:
1361                                 type = "Cortex-A8 Debug";
1362                                 full = "(Debug Unit)";
1363                                 break;
1364                         case 0xc09:
1365                                 type = "Cortex-A9 Debug";
1366                                 full = "(Debug Unit)";
1367                                 break;
1368                         case 0x4af:
1369                                 type = "Cortex-A15 Debug";
1370                                 full = "(Debug Unit)";
1371                                 break;
1372                         default:
1373                                 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1374                                 type = "-*- unrecognized -*-";
1375                                 full = "";
1376                                 break;
1377                         }
1378                         command_print(cmd_ctx, "\t\tPart is %s %s",
1379                                         type, full);
1380
1381                         /* ROM Table? */
1382                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1383                                 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1384                                 if (retval != ERROR_OK)
1385                                         return retval;
1386                         }
1387                 } else {
1388                         if (romentry)
1389                                 command_print(cmd_ctx, "\t\tComponent not present");
1390                         else
1391                                 break;
1392                 }
1393         }
1394         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1395         return ERROR_OK;
1396 }
1397
1398 static int dap_info_command(struct command_context *cmd_ctx,
1399                 struct adiv5_dap *dap, int ap)
1400 {
1401         int retval;
1402         uint32_t dbgbase, apid;
1403         int romtable_present = 0;
1404         uint8_t mem_ap;
1405         uint32_t ap_old;
1406
1407         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1408         if (retval != ERROR_OK)
1409                 return retval;
1410
1411         ap_old = dap_ap_get_select(dap);
1412         dap_ap_select(dap, ap);
1413
1414         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1415         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1416         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1417         if (apid) {
1418                 switch (apid&0x0F) {
1419                         case 0:
1420                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1421                                 break;
1422                         case 1:
1423                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1424                                 break;
1425                         case 2:
1426                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1427                                 break;
1428                         default:
1429                                 command_print(cmd_ctx, "\tUnknown AP type");
1430                                 break;
1431                 }
1432
1433                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1434                  * not a ROM table ... or have no such components at all.
1435                  */
1436                 if (mem_ap)
1437                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1438         } else
1439                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1440
1441         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1442         if (romtable_present)
1443                 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1444         else
1445                 command_print(cmd_ctx, "\tNo ROM table present");
1446         dap_ap_select(dap, ap_old);
1447
1448         return ERROR_OK;
1449 }
1450
1451 COMMAND_HANDLER(handle_dap_info_command)
1452 {
1453         struct target *target = get_current_target(CMD_CTX);
1454         struct arm *arm = target_to_arm(target);
1455         struct adiv5_dap *dap = arm->dap;
1456         uint32_t apsel;
1457
1458         switch (CMD_ARGC) {
1459         case 0:
1460                 apsel = dap->apsel;
1461                 break;
1462         case 1:
1463                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1464                 break;
1465         default:
1466                 return ERROR_COMMAND_SYNTAX_ERROR;
1467         }
1468
1469         return dap_info_command(CMD_CTX, dap, apsel);
1470 }
1471
1472 COMMAND_HANDLER(dap_baseaddr_command)
1473 {
1474         struct target *target = get_current_target(CMD_CTX);
1475         struct arm *arm = target_to_arm(target);
1476         struct adiv5_dap *dap = arm->dap;
1477
1478         uint32_t apsel, baseaddr;
1479         int retval;
1480
1481         switch (CMD_ARGC) {
1482         case 0:
1483                 apsel = dap->apsel;
1484                 break;
1485         case 1:
1486                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1487                 /* AP address is in bits 31:24 of DP_SELECT */
1488                 if (apsel >= 256)
1489                         return ERROR_COMMAND_SYNTAX_ERROR;
1490                 break;
1491         default:
1492                 return ERROR_COMMAND_SYNTAX_ERROR;
1493         }
1494
1495         dap_ap_select(dap, apsel);
1496
1497         /* NOTE:  assumes we're talking to a MEM-AP, which
1498          * has a base address.  There are other kinds of AP,
1499          * though they're not common for now.  This should
1500          * use the ID register to verify it's a MEM-AP.
1501          */
1502         retval = dap_queue_ap_read(dap, MEM_AP_REG_BASE, &baseaddr);
1503         if (retval != ERROR_OK)
1504                 return retval;
1505         retval = dap_run(dap);
1506         if (retval != ERROR_OK)
1507                 return retval;
1508
1509         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1510
1511         return retval;
1512 }
1513
1514 COMMAND_HANDLER(dap_memaccess_command)
1515 {
1516         struct target *target = get_current_target(CMD_CTX);
1517         struct arm *arm = target_to_arm(target);
1518         struct adiv5_dap *dap = arm->dap;
1519
1520         uint32_t memaccess_tck;
1521
1522         switch (CMD_ARGC) {
1523         case 0:
1524                 memaccess_tck = dap->memaccess_tck;
1525                 break;
1526         case 1:
1527                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1528                 break;
1529         default:
1530                 return ERROR_COMMAND_SYNTAX_ERROR;
1531         }
1532         dap->memaccess_tck = memaccess_tck;
1533
1534         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1535                         dap->memaccess_tck);
1536
1537         return ERROR_OK;
1538 }
1539
1540 COMMAND_HANDLER(dap_apsel_command)
1541 {
1542         struct target *target = get_current_target(CMD_CTX);
1543         struct arm *arm = target_to_arm(target);
1544         struct adiv5_dap *dap = arm->dap;
1545
1546         uint32_t apsel, apid;
1547         int retval;
1548
1549         switch (CMD_ARGC) {
1550         case 0:
1551                 apsel = 0;
1552                 break;
1553         case 1:
1554                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1555                 /* AP address is in bits 31:24 of DP_SELECT */
1556                 if (apsel >= 256)
1557                         return ERROR_COMMAND_SYNTAX_ERROR;
1558                 break;
1559         default:
1560                 return ERROR_COMMAND_SYNTAX_ERROR;
1561         }
1562
1563         dap->apsel = apsel;
1564         dap_ap_select(dap, apsel);
1565
1566         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1567         if (retval != ERROR_OK)
1568                 return retval;
1569         retval = dap_run(dap);
1570         if (retval != ERROR_OK)
1571                 return retval;
1572
1573         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1574                         apsel, apid);
1575
1576         return retval;
1577 }
1578
1579 COMMAND_HANDLER(dap_apcsw_command)
1580 {
1581         struct target *target = get_current_target(CMD_CTX);
1582         struct arm *arm = target_to_arm(target);
1583         struct adiv5_dap *dap = arm->dap;
1584
1585         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1586
1587         switch (CMD_ARGC) {
1588         case 0:
1589                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1590                         (dap->apsel), apcsw);
1591                 break;
1592         case 1:
1593                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1594                 /* AP address is in bits 31:24 of DP_SELECT */
1595                 if (sprot > 1)
1596                         return ERROR_COMMAND_SYNTAX_ERROR;
1597                 if (sprot)
1598                         apcsw |= CSW_SPROT;
1599                 else
1600                         apcsw &= ~CSW_SPROT;
1601                 break;
1602         default:
1603                 return ERROR_COMMAND_SYNTAX_ERROR;
1604         }
1605         dap->apcsw[dap->apsel] = apcsw;
1606
1607         return 0;
1608 }
1609
1610
1611
1612 COMMAND_HANDLER(dap_apid_command)
1613 {
1614         struct target *target = get_current_target(CMD_CTX);
1615         struct arm *arm = target_to_arm(target);
1616         struct adiv5_dap *dap = arm->dap;
1617
1618         uint32_t apsel, apid;
1619         int retval;
1620
1621         switch (CMD_ARGC) {
1622         case 0:
1623                 apsel = dap->apsel;
1624                 break;
1625         case 1:
1626                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1627                 /* AP address is in bits 31:24 of DP_SELECT */
1628                 if (apsel >= 256)
1629                         return ERROR_COMMAND_SYNTAX_ERROR;
1630                 break;
1631         default:
1632                 return ERROR_COMMAND_SYNTAX_ERROR;
1633         }
1634
1635         dap_ap_select(dap, apsel);
1636
1637         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1638         if (retval != ERROR_OK)
1639                 return retval;
1640         retval = dap_run(dap);
1641         if (retval != ERROR_OK)
1642                 return retval;
1643
1644         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1645
1646         return retval;
1647 }
1648
1649 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1650 {
1651         struct target *target = get_current_target(CMD_CTX);
1652         struct arm *arm = target_to_arm(target);
1653         struct adiv5_dap *dap = arm->dap;
1654
1655         uint32_t enable = dap->ti_be_32_quirks;
1656
1657         switch (CMD_ARGC) {
1658         case 0:
1659                 break;
1660         case 1:
1661                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1662                 if (enable > 1)
1663                         return ERROR_COMMAND_SYNTAX_ERROR;
1664                 break;
1665         default:
1666                 return ERROR_COMMAND_SYNTAX_ERROR;
1667         }
1668         dap->ti_be_32_quirks = enable;
1669         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1670                 enable ? "enabled" : "disabled");
1671
1672         return 0;
1673 }
1674
1675 static const struct command_registration dap_commands[] = {
1676         {
1677                 .name = "info",
1678                 .handler = handle_dap_info_command,
1679                 .mode = COMMAND_EXEC,
1680                 .help = "display ROM table for MEM-AP "
1681                         "(default currently selected AP)",
1682                 .usage = "[ap_num]",
1683         },
1684         {
1685                 .name = "apsel",
1686                 .handler = dap_apsel_command,
1687                 .mode = COMMAND_EXEC,
1688                 .help = "Set the currently selected AP (default 0) "
1689                         "and display the result",
1690                 .usage = "[ap_num]",
1691         },
1692         {
1693                 .name = "apcsw",
1694                 .handler = dap_apcsw_command,
1695                 .mode = COMMAND_EXEC,
1696                 .help = "Set csw access bit ",
1697                 .usage = "[sprot]",
1698         },
1699
1700         {
1701                 .name = "apid",
1702                 .handler = dap_apid_command,
1703                 .mode = COMMAND_EXEC,
1704                 .help = "return ID register from AP "
1705                         "(default currently selected AP)",
1706                 .usage = "[ap_num]",
1707         },
1708         {
1709                 .name = "baseaddr",
1710                 .handler = dap_baseaddr_command,
1711                 .mode = COMMAND_EXEC,
1712                 .help = "return debug base address from MEM-AP "
1713                         "(default currently selected AP)",
1714                 .usage = "[ap_num]",
1715         },
1716         {
1717                 .name = "memaccess",
1718                 .handler = dap_memaccess_command,
1719                 .mode = COMMAND_EXEC,
1720                 .help = "set/get number of extra tck for MEM-AP memory "
1721                         "bus access [0-255]",
1722                 .usage = "[cycles]",
1723         },
1724         {
1725                 .name = "ti_be_32_quirks",
1726                 .handler = dap_ti_be_32_quirks_command,
1727                 .mode = COMMAND_CONFIG,
1728                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1729                 .usage = "[enable]",
1730         },
1731         COMMAND_REGISTRATION_DONE
1732 };
1733
1734 const struct command_registration dap_command_handlers[] = {
1735         {
1736                 .name = "dap",
1737                 .mode = COMMAND_EXEC,
1738                 .help = "DAP command group",
1739                 .usage = "",
1740                 .chain = dap_commands,
1741         },
1742         COMMAND_REGISTRATION_DONE
1743 };