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   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
  98 {
  99         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 100                 ap->csw_default;
 101
 102         if (csw != ap->csw_value) {
 103                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 104                 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
 105                 if (retval != ERROR_OK)
 106                         return retval;
 107                 ap->csw_value = csw;
 108         }
 109         return ERROR_OK;
 110 }
 111
 112 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
 113 {
 114         if (tar != ap->tar_value ||
 115                         (ap->csw_value & CSW_ADDRINC_MASK)) {
 116                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 117                 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
 118                 if (retval != ERROR_OK)
 119                         return retval;
 120                 ap->tar_value = tar;
 121         }
 122         return ERROR_OK;
 123 }
 124
 125 /**
 126  * Queue transactions setting up transfer parameters for the
 127  * currently selected MEM-AP.
 128  *
 129  * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
 130  * initiate data reads or writes using memory or peripheral addresses.
 131  * If the CSW is configured for it, the TAR may be automatically
 132  * incremented after each transfer.
 133  *
 134  * @param ap The MEM-AP.
 135  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 136  *      matches the cached value, the register is not changed.
 137  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 138  *      matches the cached address, the register is not changed.
 139  *
 140  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 141  */
 142 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
 143 {
 144         int retval;
 145         retval = mem_ap_setup_csw(ap, csw);
 146         if (retval != ERROR_OK)
 147                 return retval;
 148         retval = mem_ap_setup_tar(ap, tar);
 149         if (retval != ERROR_OK)
 150                 return retval;
 151         return ERROR_OK;
 152 }
 153
 154 /**
 155  * Asynchronous (queued) read of a word from memory or a system register.
 156  *
 157  * @param ap The MEM-AP to access.
 158  * @param address Address of the 32-bit word to read; it must be
 159  *      readable by the currently selected MEM-AP.
 160  * @param value points to where the word will be stored when the
 161  *      transaction queue is flushed (assuming no errors).
 162  *
 163  * @return ERROR_OK for success.  Otherwise a fault code.
 164  */
 165 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
 166                 uint32_t *value)
 167 {
 168         int retval;
 169
 170         /* Use banked addressing (REG_BDx) to avoid some link traffic
 171          * (updating TAR) when reading several consecutive addresses.
 172          */
 173         retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
 174                         address & 0xFFFFFFF0);
 175         if (retval != ERROR_OK)
 176                 return retval;
 177
 178         return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
 179 }
 180
 181 /**
 182  * Synchronous read of a word from memory or a system register.
 183  * As a side effect, this flushes any queued transactions.
 184  *
 185  * @param ap The MEM-AP to access.
 186  * @param address Address of the 32-bit word to read; it must be
 187  *      readable by the currently selected MEM-AP.
 188  * @param value points to where the result will be stored.
 189  *
 190  * @return ERROR_OK for success; *value holds the result.
 191  * Otherwise a fault code.
 192  */
 193 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 194                 uint32_t *value)
 195 {
 196         int retval;
 197
 198         retval = mem_ap_read_u32(ap, address, value);
 199         if (retval != ERROR_OK)
 200                 return retval;
 201
 202         return dap_run(ap->dap);
 203 }
 204
 205 /**
 206  * Asynchronous (queued) write of a word to memory or a system register.
 207  *
 208  * @param ap The MEM-AP to access.
 209  * @param address Address to be written; it must be writable by
 210  *      the currently selected MEM-AP.
 211  * @param value Word that will be written to the address when transaction
 212  *      queue is flushed (assuming no errors).
 213  *
 214  * @return ERROR_OK for success.  Otherwise a fault code.
 215  */
 216 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
 217                 uint32_t value)
 218 {
 219         int retval;
 220
 221         /* Use banked addressing (REG_BDx) to avoid some link traffic
 222          * (updating TAR) when writing several consecutive addresses.
 223          */
 224         retval = mem_ap_setup_transfer(ap, CSW_32BIT | CSW_ADDRINC_OFF,
 225                         address & 0xFFFFFFF0);
 226         if (retval != ERROR_OK)
 227                 return retval;
 228
 229         return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
 230                         value);
 231 }
 232
 233 /**
 234  * Synchronous write of a word to memory or a system register.
 235  * As a side effect, this flushes any queued transactions.
 236  *
 237  * @param ap The MEM-AP to access.
 238  * @param address Address to be written; it must be writable by
 239  *      the currently selected MEM-AP.
 240  * @param value Word that will be written.
 241  *
 242  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 243  */
 244 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
 245                 uint32_t value)
 246 {
 247         int retval = mem_ap_write_u32(ap, address, value);
 248
 249         if (retval != ERROR_OK)
 250                 return retval;
 251
 252         return dap_run(ap->dap);
 253 }
 254
 255 /**
 256  * Synchronous write of a block of memory, using a specific access size.
 257  *
 258  * @param ap The MEM-AP to access.
 259  * @param buffer The data buffer to write. No particular alignment is assumed.
 260  * @param size Which access size to use, in bytes. 1, 2 or 4.
 261  * @param count The number of writes to do (in size units, not bytes).
 262  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 263  * @param addrinc Whether the target address should be increased for each write or not. This
 264  *  should normally be true, except when writing to e.g. a FIFO.
 265  * @return ERROR_OK on success, otherwise an error code.
 266  */
 267 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
 268                 uint32_t address, bool addrinc)
 269 {
 270         struct adiv5_dap *dap = ap->dap;
 271         size_t nbytes = size * count;
 272         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 273         uint32_t csw_size;
 274         uint32_t addr_xor;
 275         int retval;
 276
 277         /* TI BE-32 Quirks mode:
 278          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 279          *   size   write address   bytes written in order
 280          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 281          *   2      TAR ^ 2         (val >> 8), (val)
 282          *   1      TAR ^ 3         (val)
 283          * For example, if you attempt to write a single byte to address 0, the processor
 284          * will actually write a byte to address 3.
 285          *
 286          * To make writes of size < 4 work as expected, we xor a value with the address before
 287          * setting the TAP, and we set the TAP after every transfer rather then relying on
 288          * address increment. */
 289
 290         if (size == 4) {
 291                 csw_size = CSW_32BIT;
 292                 addr_xor = 0;
 293         } else if (size == 2) {
 294                 csw_size = CSW_16BIT;
 295                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 296         } else if (size == 1) {
 297                 csw_size = CSW_8BIT;
 298                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 299         } else {
 300                 return ERROR_TARGET_UNALIGNED_ACCESS;
 301         }
 302
 303         if (ap->unaligned_access_bad && (address % size != 0))
 304                 return ERROR_TARGET_UNALIGNED_ACCESS;
 305
 306         retval = mem_ap_setup_tar(ap, address ^ addr_xor);
 307         if (retval != ERROR_OK)
 308                 return retval;
 309
 310         while (nbytes > 0) {
 311                 uint32_t this_size = size;
 312
 313                 /* Select packed transfer if possible */
 314                 if (addrinc && ap->packed_transfers && nbytes >= 4
 315                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 316                         this_size = 4;
 317                         retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
 318                 } else {
 319                         retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
 320                 }
 321
 322                 if (retval != ERROR_OK)
 323                         break;
 324
 325                 /* How many source bytes each transfer will consume, and their location in the DRW,
 326                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 327                 uint32_t outvalue = 0;
 328                 if (dap->ti_be_32_quirks) {
 329                         switch (this_size) {
 330                         case 4:
 331                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 332                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 333                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 334                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 335                                 break;
 336                         case 2:
 337                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 338                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 339                                 break;
 340                         case 1:
 341                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 342                                 break;
 343                         }
 344                 } else {
 345                         switch (this_size) {
 346                         case 4:
 347                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 348                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 349                         case 2:
 350                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 351                         case 1:
 352                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 353                         }
 354                 }
 355
 356                 nbytes -= this_size;
 357
 358                 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
 359                 if (retval != ERROR_OK)
 360                         break;
 361
 362                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 363                 if (addrinc && (addr_xor || (address % ap->tar_autoincr_block < size && nbytes > 0))) {
 364                         retval = mem_ap_setup_tar(ap, address ^ addr_xor);
 365                         if (retval != ERROR_OK)
 366                                 break;
 367                 }
 368         }
 369
 370         /* REVISIT: Might want to have a queued version of this function that does not run. */
 371         if (retval == ERROR_OK)
 372                 retval = dap_run(dap);
 373
 374         if (retval != ERROR_OK) {
 375                 uint32_t tar;
 376                 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 377                                 && dap_run(dap) == ERROR_OK)
 378                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 379                 else
 380                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 381         }
 382
 383         return retval;
 384 }
 385
 386 /**
 387  * Synchronous read of a block of memory, using a specific access size.
 388  *
 389  * @param ap The MEM-AP to access.
 390  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 391  * @param size Which access size to use, in bytes. 1, 2 or 4.
 392  * @param count The number of reads to do (in size units, not bytes).
 393  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 394  * @param addrinc Whether the target address should be increased after each read or not. This
 395  *  should normally be true, except when reading from e.g. a FIFO.
 396  * @return ERROR_OK on success, otherwise an error code.
 397  */
 398 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
 399                 uint32_t adr, bool addrinc)
 400 {
 401         struct adiv5_dap *dap = ap->dap;
 402         size_t nbytes = size * count;
 403         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 404         uint32_t csw_size;
 405         uint32_t address = adr;
 406         int retval;
 407
 408         /* TI BE-32 Quirks mode:
 409          * Reads on big-endian TMS570 behave strangely differently than writes.
 410          * They read from the physical address requested, but with DRW byte-reversed.
 411          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 412          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 413          * so avoid them. */
 414
 415         if (size == 4)
 416                 csw_size = CSW_32BIT;
 417         else if (size == 2)
 418                 csw_size = CSW_16BIT;
 419         else if (size == 1)
 420                 csw_size = CSW_8BIT;
 421         else
 422                 return ERROR_TARGET_UNALIGNED_ACCESS;
 423
 424         if (ap->unaligned_access_bad && (adr % size != 0))
 425                 return ERROR_TARGET_UNALIGNED_ACCESS;
 426
 427         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 428          * over-allocation if packed transfers are going to be used, but determining the real need at
 429          * this point would be messy. */
 430         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 431         uint32_t *read_ptr = read_buf;
 432         if (read_buf == NULL) {
 433                 LOG_ERROR("Failed to allocate read buffer");
 434                 return ERROR_FAIL;
 435         }
 436
 437         retval = mem_ap_setup_tar(ap, address);
 438         if (retval != ERROR_OK) {
 439                 free(read_buf);
 440                 return retval;
 441         }
 442
 443         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 444          * useful bytes it contains, and their location in the word, depends on the type of transfer
 445          * and alignment. */
 446         while (nbytes > 0) {
 447                 uint32_t this_size = size;
 448
 449                 /* Select packed transfer if possible */
 450                 if (addrinc && ap->packed_transfers && nbytes >= 4
 451                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 452                         this_size = 4;
 453                         retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
 454                 } else {
 455                         retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
 456                 }
 457                 if (retval != ERROR_OK)
 458                         break;
 459
 460                 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
 461                 if (retval != ERROR_OK)
 462                         break;
 463
 464                 nbytes -= this_size;
 465                 address += this_size;
 466
 467                 /* Rewrite TAR if it wrapped */
 468                 if (addrinc && address % ap->tar_autoincr_block < size && nbytes > 0) {
 469                         retval = mem_ap_setup_tar(ap, address);
 470                         if (retval != ERROR_OK)
 471                                 break;
 472                 }
 473         }
 474
 475         if (retval == ERROR_OK)
 476                 retval = dap_run(dap);
 477
 478         /* Restore state */
 479         address = adr;
 480         nbytes = size * count;
 481         read_ptr = read_buf;
 482
 483         /* If something failed, read TAR to find out how much data was successfully read, so we can
 484          * at least give the caller what we have. */
 485         if (retval != ERROR_OK) {
 486                 uint32_t tar;
 487                 if (dap_queue_ap_read(ap, MEM_AP_REG_TAR, &tar) == ERROR_OK
 488                                 && dap_run(dap) == ERROR_OK) {
 489                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 490                         if (nbytes > tar - address)
 491                                 nbytes = tar - address;
 492                 } else {
 493                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 494                         nbytes = 0;
 495                 }
 496         }
 497
 498         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 499         while (nbytes > 0) {
 500                 uint32_t this_size = size;
 501
 502                 if (addrinc && ap->packed_transfers && nbytes >= 4
 503                                 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
 504                         this_size = 4;
 505                 }
 506
 507                 if (dap->ti_be_32_quirks) {
 508                         switch (this_size) {
 509                         case 4:
 510                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 511                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 512                         case 2:
 513                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 514                         case 1:
 515                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 516                         }
 517                 } else {
 518                         switch (this_size) {
 519                         case 4:
 520                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 521                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 522                         case 2:
 523                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 524                         case 1:
 525                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 526                         }
 527                 }
 528
 529                 read_ptr++;
 530                 nbytes -= this_size;
 531         }
 532
 533         free(read_buf);
 534         return retval;
 535 }
 536
 537 int mem_ap_read_buf(struct adiv5_ap *ap,
 538                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 539 {
 540         return mem_ap_read(ap, buffer, size, count, address, true);
 541 }
 542
 543 int mem_ap_write_buf(struct adiv5_ap *ap,
 544                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 545 {
 546         return mem_ap_write(ap, buffer, size, count, address, true);
 547 }
 548
 549 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
 550                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 551 {
 552         return mem_ap_read(ap, buffer, size, count, address, false);
 553 }
 554
 555 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
 556                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 557 {
 558         return mem_ap_write(ap, buffer, size, count, address, false);
 559 }
 560
 561 /*--------------------------------------------------------------------------*/
 562
 563
 564 #define DAP_POWER_DOMAIN_TIMEOUT (10)
 565
 566 /* FIXME don't import ... just initialize as
 567  * part of DAP transport setup
 568 */
 569 extern const struct dap_ops jtag_dp_ops;
 570
 571 /*--------------------------------------------------------------------------*/
 572
 573 /**
 574  * Create a new DAP
 575  */
 576 struct adiv5_dap *dap_init(void)
 577 {
 578         struct adiv5_dap *dap = calloc(1, sizeof(struct adiv5_dap));
 579         int i;
 580         /* Set up with safe defaults */
 581         for (i = 0; i <= 255; i++) {
 582                 dap->ap[i].dap = dap;
 583                 dap->ap[i].ap_num = i;
 584                 /* memaccess_tck max is 255 */
 585                 dap->ap[i].memaccess_tck = 255;
 586                 /* Number of bits for tar autoincrement, impl. dep. at least 10 */
 587                 dap->ap[i].tar_autoincr_block = (1<<10);
 588         }
 589         return dap;
 590 }
 591
 592 /**
 593  * Initialize a DAP.  This sets up the power domains, prepares the DP
 594  * for further use and activates overrun checking.
 595  *
 596  * @param dap The DAP being initialized.
 597  */
 598 int dap_dp_init(struct adiv5_dap *dap)
 599 {
 600         int retval;
 601
 602         LOG_DEBUG(" ");
 603         /* JTAG-DP or SWJ-DP, in JTAG mode
 604          * ... for SWD mode this is patched as part
 605          * of link switchover
 606          * FIXME: This should already be setup by the respective transport specific DAP creation.
 607          */
 608         if (!dap->ops)
 609                 dap->ops = &jtag_dp_ops;
 610
 611         dap->select = DP_SELECT_INVALID;
 612         dap->last_read = NULL;
 613
 614         for (size_t i = 0; i < 10; i++) {
 615                 /* DP initialization */
 616
 617                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 618                 if (retval != ERROR_OK)
 619                         continue;
 620
 621                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 622                 if (retval != ERROR_OK)
 623                         continue;
 624
 625                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 626                 if (retval != ERROR_OK)
 627                         continue;
 628
 629                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 630                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 631                 if (retval != ERROR_OK)
 632                         continue;
 633
 634                 /* Check that we have debug power domains activated */
 635                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 636                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 637                                               CDBGPWRUPACK, CDBGPWRUPACK,
 638                                               DAP_POWER_DOMAIN_TIMEOUT);
 639                 if (retval != ERROR_OK)
 640                         continue;
 641
 642                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 643                 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
 644                                               CSYSPWRUPACK, CSYSPWRUPACK,
 645                                               DAP_POWER_DOMAIN_TIMEOUT);
 646                 if (retval != ERROR_OK)
 647                         continue;
 648
 649                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 650                 if (retval != ERROR_OK)
 651                         continue;
 652
 653                 /* With debug power on we can activate OVERRUN checking */
 654                 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 655                 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 656                 if (retval != ERROR_OK)
 657                         continue;
 658                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 659                 if (retval != ERROR_OK)
 660                         continue;
 661
 662                 retval = dap_run(dap);
 663                 if (retval != ERROR_OK)
 664                         continue;
 665
 666                 break;
 667         }
 668
 669         return retval;
 670 }
 671
 672 /**
 673  * Initialize a DAP.  This sets up the power domains, prepares the DP
 674  * for further use, and arranges to use AP #0 for all AP operations
 675  * until dap_ap-select() changes that policy.
 676  *
 677  * @param ap The MEM-AP being initialized.
 678  */
 679 int mem_ap_init(struct adiv5_ap *ap)
 680 {
 681         /* check that we support packed transfers */
 682         uint32_t csw, cfg;
 683         int retval;
 684         struct adiv5_dap *dap = ap->dap;
 685
 686         retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 687         if (retval != ERROR_OK)
 688                 return retval;
 689
 690         retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
 691         if (retval != ERROR_OK)
 692                 return retval;
 693
 694         retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
 695         if (retval != ERROR_OK)
 696                 return retval;
 697
 698         retval = dap_run(dap);
 699         if (retval != ERROR_OK)
 700                 return retval;
 701
 702         if (csw & CSW_ADDRINC_PACKED)
 703                 ap->packed_transfers = true;
 704         else
 705                 ap->packed_transfers = false;
 706
 707         /* Packed transfers on TI BE-32 processors do not work correctly in
 708          * many cases. */
 709         if (dap->ti_be_32_quirks)
 710                 ap->packed_transfers = false;
 711
 712         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 713                         ap->packed_transfers ? "enabled" : "disabled");
 714
 715         /* The ARM ADI spec leaves implementation-defined whether unaligned
 716          * memory accesses work, only work partially, or cause a sticky error.
 717          * On TI BE-32 processors, reads seem to return garbage in some bytes
 718          * and unaligned writes seem to cause a sticky error.
 719          * TODO: it would be nice to have a way to detect whether unaligned
 720          * operations are supported on other processors. */
 721         ap->unaligned_access_bad = dap->ti_be_32_quirks;
 722
 723         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 724                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 725
 726         return ERROR_OK;
 727 }
 728
 729 /* CID interpretation -- see ARM IHI 0029B section 3
 730  * and ARM IHI 0031A table 13-3.
 731  */
 732 static const char *class_description[16] = {
 733         "Reserved", "ROM table", "Reserved", "Reserved",
 734         "Reserved", "Reserved", "Reserved", "Reserved",
 735         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 736         "Reserved", "OptimoDE DESS",
 737         "Generic IP component", "PrimeCell or System component"
 738 };
 739
 740 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 741 {
 742         return cid3 == 0xb1 && cid2 == 0x05
 743                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 744 }
 745
 746 /*
 747  * This function checks the ID for each access port to find the requested Access Port type
 748  */
 749 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
 750 {
 751         int ap_num;
 752
 753         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 754         for (ap_num = 0; ap_num <= 255; ap_num++) {
 755
 756                 /* read the IDR register of the Access Port */
 757                 uint32_t id_val = 0;
 758
 759                 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
 760                 if (retval != ERROR_OK)
 761                         return retval;
 762
 763                 retval = dap_run(dap);
 764
 765                 /* IDR bits:
 766                  * 31-28 : Revision
 767                  * 27-24 : JEDEC bank (0x4 for ARM)
 768                  * 23-17 : JEDEC code (0x3B for ARM)
 769                  * 16-13 : Class (0b1000=Mem-AP)
 770                  * 12-8  : Reserved
 771                  *  7-4  : AP Variant (non-zero for JTAG-AP)
 772                  *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
 773                  */
 774
 775                 /* Reading register for a non-existant AP should not cause an error,
 776                  * but just to be sure, try to continue searching if an error does happen.
 777                  */
 778                 if ((retval == ERROR_OK) &&                  /* Register read success */
 779                         ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
 780                         ((id_val & IDR_TYPE) == type_to_find)) {      /* type matches*/
 781
 782                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 783                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 784                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 785                                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 786                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 787                                                 ap_num, id_val);
 788
 789                         *ap_out = &dap->ap[ap_num];
 790                         return ERROR_OK;
 791                 }
 792         }
 793
 794         LOG_DEBUG("No %s found",
 795                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 796                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 797                                 (type_to_find == AP_TYPE_AXI_AP)  ? "AXI-AP"  :
 798                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 799         return ERROR_FAIL;
 800 }
 801
 802 int dap_get_debugbase(struct adiv5_ap *ap,
 803                         uint32_t *dbgbase, uint32_t *apid)
 804 {
 805         struct adiv5_dap *dap = ap->dap;
 806         int retval;
 807
 808         retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
 809         if (retval != ERROR_OK)
 810                 return retval;
 811         retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
 812         if (retval != ERROR_OK)
 813                 return retval;
 814         retval = dap_run(dap);
 815         if (retval != ERROR_OK)
 816                 return retval;
 817
 818         return ERROR_OK;
 819 }
 820
 821 int dap_lookup_cs_component(struct adiv5_ap *ap,
 822                         uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
 823 {
 824         uint32_t romentry, entry_offset = 0, component_base, devtype;
 825         int retval;
 826
 827         *addr = 0;
 828
 829         do {
 830                 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
 831                                                 entry_offset, &romentry);
 832                 if (retval != ERROR_OK)
 833                         return retval;
 834
 835                 component_base = (dbgbase & 0xFFFFF000)
 836                         + (romentry & 0xFFFFF000);
 837
 838                 if (romentry & 0x1) {
 839                         uint32_t c_cid1;
 840                         retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
 841                         if (retval != ERROR_OK) {
 842                                 LOG_ERROR("Can't read component with base address 0x%" PRIx32
 843                                           ", the corresponding core might be turned off", component_base);
 844                                 return retval;
 845                         }
 846                         if (((c_cid1 >> 4) & 0x0f) == 1) {
 847                                 retval = dap_lookup_cs_component(ap, component_base,
 848                                                         type, addr, idx);
 849                                 if (retval == ERROR_OK)
 850                                         break;
 851                                 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
 852                                         return retval;
 853                         }
 854
 855                         retval = mem_ap_read_atomic_u32(ap,
 856                                         (component_base & 0xfffff000) | 0xfcc,
 857                                         &devtype);
 858                         if (retval != ERROR_OK)
 859                                 return retval;
 860                         if ((devtype & 0xff) == type) {
 861                                 if (!*idx) {
 862                                         *addr = component_base;
 863                                         break;
 864                                 } else
 865                                         (*idx)--;
 866                         }
 867                 }
 868                 entry_offset += 4;
 869         } while (romentry > 0);
 870
 871         if (!*addr)
 872                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 873
 874         return ERROR_OK;
 875 }
 876
 877 static int dap_rom_display(struct command_context *cmd_ctx,
 878                                 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
 879 {
 880         struct adiv5_dap *dap = ap->dap;
 881         int retval;
 882         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 883         uint16_t entry_offset;
 884         char tabs[7] = "";
 885
 886         if (depth > 16) {
 887                 command_print(cmd_ctx, "\tTables too deep");
 888                 return ERROR_FAIL;
 889         }
 890
 891         if (depth)
 892                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 893
 894         /* bit 16 of apid indicates a memory access port */
 895         if (dbgbase & 0x02)
 896                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 897         else
 898                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 899
 900         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 901         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 902         if (retval != ERROR_OK)
 903                 return retval;
 904         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 905         if (retval != ERROR_OK)
 906                 return retval;
 907         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 908         if (retval != ERROR_OK)
 909                 return retval;
 910         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 911         if (retval != ERROR_OK)
 912                 return retval;
 913         retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 914         if (retval != ERROR_OK)
 915                 return retval;
 916         retval = dap_run(dap);
 917         if (retval != ERROR_OK)
 918                 return retval;
 919
 920         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 921                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 922                                 ", CID2 0x%02x"
 923                                 ", CID1 0x%02x"
 924                                 ", CID0 0x%02x",
 925                                 tabs,
 926                                 (unsigned)cid3, (unsigned)cid2,
 927                                 (unsigned)cid1, (unsigned)cid0);
 928         if (memtype & 0x01)
 929                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
 930         else
 931                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
 932
 933         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
 934         for (entry_offset = 0; ; entry_offset += 4) {
 935                 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 936                 if (retval != ERROR_OK)
 937                         return retval;
 938                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 939                                 tabs, entry_offset, romentry);
 940                 if (romentry & 0x01) {
 941                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
 942                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
 943                         uint32_t component_base;
 944                         uint32_t part_num;
 945                         const char *type, *full;
 946
 947                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
 948
 949                         /* IDs are in last 4K section */
 950                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
 951                         if (retval != ERROR_OK) {
 952                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
 953                                               ", the corresponding core might be turned off", tabs, component_base);
 954                                 continue;
 955                         }
 956                         c_pid0 &= 0xff;
 957                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
 958                         if (retval != ERROR_OK)
 959                                 return retval;
 960                         c_pid1 &= 0xff;
 961                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
 962                         if (retval != ERROR_OK)
 963                                 return retval;
 964                         c_pid2 &= 0xff;
 965                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
 966                         if (retval != ERROR_OK)
 967                                 return retval;
 968                         c_pid3 &= 0xff;
 969                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
 970                         if (retval != ERROR_OK)
 971                                 return retval;
 972                         c_pid4 &= 0xff;
 973
 974                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
 975                         if (retval != ERROR_OK)
 976                                 return retval;
 977                         c_cid0 &= 0xff;
 978                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
 979                         if (retval != ERROR_OK)
 980                                 return retval;
 981                         c_cid1 &= 0xff;
 982                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
 983                         if (retval != ERROR_OK)
 984                                 return retval;
 985                         c_cid2 &= 0xff;
 986                         retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
 987                         if (retval != ERROR_OK)
 988                                 return retval;
 989                         c_cid3 &= 0xff;
 990
 991                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
 992                                       "start address 0x%" PRIx32, component_base,
 993                                       /* component may take multiple 4K pages */
 994                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
 995                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
 996                                         (uint8_t)((c_cid1 >> 4) & 0xf),
 997                                         /* See ARM IHI 0029B Table 3-3 */
 998                                         class_description[(c_cid1 >> 4) & 0xf]);
 999
1000                         /* CoreSight component? */
1001                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1002                                 uint32_t devtype;
1003                                 unsigned minor;
1004                                 const char *major = "Reserved", *subtype = "Reserved";
1005
1006                                 retval = mem_ap_read_atomic_u32(ap,
1007                                                 (component_base & 0xfffff000) | 0xfcc,
1008                                                 &devtype);
1009                                 if (retval != ERROR_OK)
1010                                         return retval;
1011                                 minor = (devtype >> 4) & 0x0f;
1012                                 switch (devtype & 0x0f) {
1013                                 case 0:
1014                                         major = "Miscellaneous";
1015                                         switch (minor) {
1016                                         case 0:
1017                                                 subtype = "other";
1018                                                 break;
1019                                         case 4:
1020                                                 subtype = "Validation component";
1021                                                 break;
1022                                         }
1023                                         break;
1024                                 case 1:
1025                                         major = "Trace Sink";
1026                                         switch (minor) {
1027                                         case 0:
1028                                                 subtype = "other";
1029                                                 break;
1030                                         case 1:
1031                                                 subtype = "Port";
1032                                                 break;
1033                                         case 2:
1034                                                 subtype = "Buffer";
1035                                                 break;
1036                                         case 3:
1037                                                 subtype = "Router";
1038                                                 break;
1039                                         }
1040                                         break;
1041                                 case 2:
1042                                         major = "Trace Link";
1043                                         switch (minor) {
1044                                         case 0:
1045                                                 subtype = "other";
1046                                                 break;
1047                                         case 1:
1048                                                 subtype = "Funnel, router";
1049                                                 break;
1050                                         case 2:
1051                                                 subtype = "Filter";
1052                                                 break;
1053                                         case 3:
1054                                                 subtype = "FIFO, buffer";
1055                                                 break;
1056                                         }
1057                                         break;
1058                                 case 3:
1059                                         major = "Trace Source";
1060                                         switch (minor) {
1061                                         case 0:
1062                                                 subtype = "other";
1063                                                 break;
1064                                         case 1:
1065                                                 subtype = "Processor";
1066                                                 break;
1067                                         case 2:
1068                                                 subtype = "DSP";
1069                                                 break;
1070                                         case 3:
1071                                                 subtype = "Engine/Coprocessor";
1072                                                 break;
1073                                         case 4:
1074                                                 subtype = "Bus";
1075                                                 break;
1076                                         case 6:
1077                                                 subtype = "Software";
1078                                                 break;
1079                                         }
1080                                         break;
1081                                 case 4:
1082                                         major = "Debug Control";
1083                                         switch (minor) {
1084                                         case 0:
1085                                                 subtype = "other";
1086                                                 break;
1087                                         case 1:
1088                                                 subtype = "Trigger Matrix";
1089                                                 break;
1090                                         case 2:
1091                                                 subtype = "Debug Auth";
1092                                                 break;
1093                                         case 3:
1094                                                 subtype = "Power Requestor";
1095                                                 break;
1096                                         }
1097                                         break;
1098                                 case 5:
1099                                         major = "Debug Logic";
1100                                         switch (minor) {
1101                                         case 0:
1102                                                 subtype = "other";
1103                                                 break;
1104                                         case 1:
1105                                                 subtype = "Processor";
1106                                                 break;
1107                                         case 2:
1108                                                 subtype = "DSP";
1109                                                 break;
1110                                         case 3:
1111                                                 subtype = "Engine/Coprocessor";
1112                                                 break;
1113                                         case 4:
1114                                                 subtype = "Bus";
1115                                                 break;
1116                                         case 5:
1117                                                 subtype = "Memory";
1118                                                 break;
1119                                         }
1120                                         break;
1121                                 case 6:
1122                                         major = "Perfomance Monitor";
1123                                         switch (minor) {
1124                                         case 0:
1125                                                 subtype = "other";
1126                                                 break;
1127                                         case 1:
1128                                                 subtype = "Processor";
1129                                                 break;
1130                                         case 2:
1131                                                 subtype = "DSP";
1132                                                 break;
1133                                         case 3:
1134                                                 subtype = "Engine/Coprocessor";
1135                                                 break;
1136                                         case 4:
1137                                                 subtype = "Bus";
1138                                                 break;
1139                                         case 5:
1140                                                 subtype = "Memory";
1141                                                 break;
1142                                         }
1143                                         break;
1144                                 }
1145                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1146                                                 (uint8_t)(devtype & 0xff),
1147                                                 major, subtype);
1148                                 /* REVISIT also show 0xfc8 DevId */
1149                         }
1150
1151                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1152                                 command_print(cmd_ctx,
1153                                                 "\t\tCID3 0%02x"
1154                                                 ", CID2 0%02x"
1155                                                 ", CID1 0%02x"
1156                                                 ", CID0 0%02x",
1157                                                 (int)c_cid3,
1158                                                 (int)c_cid2,
1159                                                 (int)c_cid1,
1160                                                 (int)c_cid0);
1161                         command_print(cmd_ctx,
1162                                 "\t\tPeripheral ID[4..0] = hex "
1163                                 "%02x %02x %02x %02x %02x",
1164                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1165                                 (int)c_pid1, (int)c_pid0);
1166
1167                         /* Part number interpretations are from Cortex
1168                          * core specs, the CoreSight components TRM
1169                          * (ARM DDI 0314H), CoreSight System Design
1170                          * Guide (ARM DGI 0012D) and ETM specs; also
1171                          * from chip observation (e.g. TI SDTI).
1172                          */
1173                         part_num = (c_pid0 & 0xff);
1174                         part_num |= (c_pid1 & 0x0f) << 8;
1175                         switch (part_num) {
1176                         case 0x000:
1177                                 type = "Cortex-M3 NVIC";
1178                                 full = "(Interrupt Controller)";
1179                                 break;
1180                         case 0x001:
1181                                 type = "Cortex-M3 ITM";
1182                                 full = "(Instrumentation Trace Module)";
1183                                 break;
1184                         case 0x002:
1185                                 type = "Cortex-M3 DWT";
1186                                 full = "(Data Watchpoint and Trace)";
1187                                 break;
1188                         case 0x003:
1189                                 type = "Cortex-M3 FBP";
1190                                 full = "(Flash Patch and Breakpoint)";
1191                                 break;
1192                         case 0x008:
1193                                 type = "Cortex-M0 SCS";
1194                                 full = "(System Control Space)";
1195                                 break;
1196                         case 0x00a:
1197                                 type = "Cortex-M0 DWT";
1198                                 full = "(Data Watchpoint and Trace)";
1199                                 break;
1200                         case 0x00b:
1201                                 type = "Cortex-M0 BPU";
1202                                 full = "(Breakpoint Unit)";
1203                                 break;
1204                         case 0x00c:
1205                                 type = "Cortex-M4 SCS";
1206                                 full = "(System Control Space)";
1207                                 break;
1208                         case 0x00d:
1209                                 type = "CoreSight ETM11";
1210                                 full = "(Embedded Trace)";
1211                                 break;
1212                         /* case 0x113: what? */
1213                         case 0x120:             /* from OMAP3 memmap */
1214                                 type = "TI SDTI";
1215                                 full = "(System Debug Trace Interface)";
1216                                 break;
1217                         case 0x343:             /* from OMAP3 memmap */
1218                                 type = "TI DAPCTL";
1219                                 full = "";
1220                                 break;
1221                         case 0x906:
1222                                 type = "Coresight CTI";
1223                                 full = "(Cross Trigger)";
1224                                 break;
1225                         case 0x907:
1226                                 type = "Coresight ETB";
1227                                 full = "(Trace Buffer)";
1228                                 break;
1229                         case 0x908:
1230                                 type = "Coresight CSTF";
1231                                 full = "(Trace Funnel)";
1232                                 break;
1233                         case 0x910:
1234                                 type = "CoreSight ETM9";
1235                                 full = "(Embedded Trace)";
1236                                 break;
1237                         case 0x912:
1238                                 type = "Coresight TPIU";
1239                                 full = "(Trace Port Interface Unit)";
1240                                 break;
1241                         case 0x913:
1242                                 type = "Coresight ITM";
1243                                 full = "(Instrumentation Trace Macrocell)";
1244                                 break;
1245                         case 0x914:
1246                                 type = "Coresight SWO";
1247                                 full = "(Single Wire Output)";
1248                                 break;
1249                         case 0x917:
1250                                 type = "Coresight HTM";
1251                                 full = "(AHB Trace Macrocell)";
1252                                 break;
1253                         case 0x920:
1254                                 type = "CoreSight ETM11";
1255                                 full = "(Embedded Trace)";
1256                                 break;
1257                         case 0x921:
1258                                 type = "Cortex-A8 ETM";
1259                                 full = "(Embedded Trace)";
1260                                 break;
1261                         case 0x922:
1262                                 type = "Cortex-A8 CTI";
1263                                 full = "(Cross Trigger)";
1264                                 break;
1265                         case 0x923:
1266                                 type = "Cortex-M3 TPIU";
1267                                 full = "(Trace Port Interface Unit)";
1268                                 break;
1269                         case 0x924:
1270                                 type = "Cortex-M3 ETM";
1271                                 full = "(Embedded Trace)";
1272                                 break;
1273                         case 0x925:
1274                                 type = "Cortex-M4 ETM";
1275                                 full = "(Embedded Trace)";
1276                                 break;
1277                         case 0x930:
1278                                 type = "Cortex-R4 ETM";
1279                                 full = "(Embedded Trace)";
1280                                 break;
1281                         case 0x950:
1282                                 type = "CoreSight Component";
1283                                 full = "(unidentified Cortex-A9 component)";
1284                                 break;
1285                         case 0x961:
1286                                 type = "CoreSight TMC";
1287                                 full = "(Trace Memory Controller)";
1288                                 break;
1289                         case 0x962:
1290                                 type = "CoreSight STM";
1291                                 full = "(System Trace Macrocell)";
1292                                 break;
1293                         case 0x9a0:
1294                                 type = "CoreSight PMU";
1295                                 full = "(Performance Monitoring Unit)";
1296                                 break;
1297                         case 0x9a1:
1298                                 type = "Cortex-M4 TPUI";
1299                                 full = "(Trace Port Interface Unit)";
1300                                 break;
1301                         case 0x9a5:
1302                                 type = "Cortex-A5 ETM";
1303                                 full = "(Embedded Trace)";
1304                                 break;
1305                         case 0xc05:
1306                                 type = "Cortex-A5 Debug";
1307                                 full = "(Debug Unit)";
1308                                 break;
1309                         case 0xc08:
1310                                 type = "Cortex-A8 Debug";
1311                                 full = "(Debug Unit)";
1312                                 break;
1313                         case 0xc09:
1314                                 type = "Cortex-A9 Debug";
1315                                 full = "(Debug Unit)";
1316                                 break;
1317                         case 0x4af:
1318                                 type = "Cortex-A15 Debug";
1319                                 full = "(Debug Unit)";
1320                                 break;
1321                         default:
1322                                 LOG_DEBUG("Unrecognized Part number 0x%" PRIx32, part_num);
1323                                 type = "-*- unrecognized -*-";
1324                                 full = "";
1325                                 break;
1326                         }
1327                         command_print(cmd_ctx, "\t\tPart is %s %s",
1328                                         type, full);
1329
1330                         /* ROM Table? */
1331                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1332                                 retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
1333                                 if (retval != ERROR_OK)
1334                                         return retval;
1335                         }
1336                 } else {
1337                         if (romentry)
1338                                 command_print(cmd_ctx, "\t\tComponent not present");
1339                         else
1340                                 break;
1341                 }
1342         }
1343         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1344         return ERROR_OK;
1345 }
1346
1347 static int dap_info_command(struct command_context *cmd_ctx,
1348                 struct adiv5_ap *ap)
1349 {
1350         int retval;
1351         uint32_t dbgbase, apid;
1352         int romtable_present = 0;
1353         uint8_t mem_ap;
1354
1355         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1356         retval = dap_get_debugbase(ap, &dbgbase, &apid);
1357         if (retval != ERROR_OK)
1358                 return retval;
1359
1360         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1361         if (apid == 0) {
1362                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap->ap_num);
1363                 return ERROR_FAIL;
1364         }
1365
1366         switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1367         case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1368                 command_print(cmd_ctx, "\tType is JTAG-AP");
1369                 break;
1370         case IDR_JEP106_ARM | AP_TYPE_AHB_AP:
1371                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1372                 break;
1373         case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1374                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1375                 break;
1376         case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1377                 command_print(cmd_ctx, "\tType is MEM-AP AXI");
1378                 break;
1379         default:
1380                 command_print(cmd_ctx, "\tUnknown AP type");
1381                 break;
1382         }
1383
1384         /* NOTE: a MEM-AP may have a single CoreSight component that's
1385          * not a ROM table ... or have no such components at all.
1386          */
1387         mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1388         if (mem_ap) {
1389                 command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1390
1391                 romtable_present = dbgbase != 0xFFFFFFFF;
1392                 if (romtable_present)
1393                         dap_rom_display(cmd_ctx, ap, dbgbase, 0);
1394                 else
1395                         command_print(cmd_ctx, "\tNo ROM table present");
1396         }
1397
1398         return ERROR_OK;
1399 }
1400
1401 COMMAND_HANDLER(handle_dap_info_command)
1402 {
1403         struct target *target = get_current_target(CMD_CTX);
1404         struct arm *arm = target_to_arm(target);
1405         struct adiv5_dap *dap = arm->dap;
1406         uint32_t apsel;
1407
1408         switch (CMD_ARGC) {
1409         case 0:
1410                 apsel = dap->apsel;
1411                 break;
1412         case 1:
1413                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1414                 if (apsel >= 256)
1415                         return ERROR_COMMAND_SYNTAX_ERROR;
1416                 break;
1417         default:
1418                 return ERROR_COMMAND_SYNTAX_ERROR;
1419         }
1420
1421         return dap_info_command(CMD_CTX, &dap->ap[apsel]);
1422 }
1423
1424 COMMAND_HANDLER(dap_baseaddr_command)
1425 {
1426         struct target *target = get_current_target(CMD_CTX);
1427         struct arm *arm = target_to_arm(target);
1428         struct adiv5_dap *dap = arm->dap;
1429
1430         uint32_t apsel, baseaddr;
1431         int retval;
1432
1433         switch (CMD_ARGC) {
1434         case 0:
1435                 apsel = dap->apsel;
1436                 break;
1437         case 1:
1438                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1439                 /* AP address is in bits 31:24 of DP_SELECT */
1440                 if (apsel >= 256)
1441                         return ERROR_COMMAND_SYNTAX_ERROR;
1442                 break;
1443         default:
1444                 return ERROR_COMMAND_SYNTAX_ERROR;
1445         }
1446
1447         /* NOTE:  assumes we're talking to a MEM-AP, which
1448          * has a base address.  There are other kinds of AP,
1449          * though they're not common for now.  This should
1450          * use the ID register to verify it's a MEM-AP.
1451          */
1452         retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1453         if (retval != ERROR_OK)
1454                 return retval;
1455         retval = dap_run(dap);
1456         if (retval != ERROR_OK)
1457                 return retval;
1458
1459         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1460
1461         return retval;
1462 }
1463
1464 COMMAND_HANDLER(dap_memaccess_command)
1465 {
1466         struct target *target = get_current_target(CMD_CTX);
1467         struct arm *arm = target_to_arm(target);
1468         struct adiv5_dap *dap = arm->dap;
1469
1470         uint32_t memaccess_tck;
1471
1472         switch (CMD_ARGC) {
1473         case 0:
1474                 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1475                 break;
1476         case 1:
1477                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1478                 break;
1479         default:
1480                 return ERROR_COMMAND_SYNTAX_ERROR;
1481         }
1482         dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1483
1484         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1485                         dap->ap[dap->apsel].memaccess_tck);
1486
1487         return ERROR_OK;
1488 }
1489
1490 COMMAND_HANDLER(dap_apsel_command)
1491 {
1492         struct target *target = get_current_target(CMD_CTX);
1493         struct arm *arm = target_to_arm(target);
1494         struct adiv5_dap *dap = arm->dap;
1495
1496         uint32_t apsel, apid;
1497         int retval;
1498
1499         switch (CMD_ARGC) {
1500         case 0:
1501                 apsel = dap->apsel;
1502                 break;
1503         case 1:
1504                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1505                 /* AP address is in bits 31:24 of DP_SELECT */
1506                 if (apsel >= 256)
1507                         return ERROR_COMMAND_SYNTAX_ERROR;
1508                 break;
1509         default:
1510                 return ERROR_COMMAND_SYNTAX_ERROR;
1511         }
1512
1513         dap->apsel = apsel;
1514
1515         retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1516         if (retval != ERROR_OK)
1517                 return retval;
1518         retval = dap_run(dap);
1519         if (retval != ERROR_OK)
1520                 return retval;
1521
1522         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1523                         apsel, apid);
1524
1525         return retval;
1526 }
1527
1528 COMMAND_HANDLER(dap_apcsw_command)
1529 {
1530         struct target *target = get_current_target(CMD_CTX);
1531         struct arm *arm = target_to_arm(target);
1532         struct adiv5_dap *dap = arm->dap;
1533
1534         uint32_t apcsw = dap->ap[dap->apsel].csw_default, sprot = 0;
1535
1536         switch (CMD_ARGC) {
1537         case 0:
1538                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1539                         (dap->apsel), apcsw);
1540                 break;
1541         case 1:
1542                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1543                 /* AP address is in bits 31:24 of DP_SELECT */
1544                 if (sprot > 1)
1545                         return ERROR_COMMAND_SYNTAX_ERROR;
1546                 if (sprot)
1547                         apcsw |= CSW_SPROT;
1548                 else
1549                         apcsw &= ~CSW_SPROT;
1550                 break;
1551         default:
1552                 return ERROR_COMMAND_SYNTAX_ERROR;
1553         }
1554         dap->ap[dap->apsel].csw_default = apcsw;
1555
1556         return 0;
1557 }
1558
1559
1560
1561 COMMAND_HANDLER(dap_apid_command)
1562 {
1563         struct target *target = get_current_target(CMD_CTX);
1564         struct arm *arm = target_to_arm(target);
1565         struct adiv5_dap *dap = arm->dap;
1566
1567         uint32_t apsel, apid;
1568         int retval;
1569
1570         switch (CMD_ARGC) {
1571         case 0:
1572                 apsel = dap->apsel;
1573                 break;
1574         case 1:
1575                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1576                 /* AP address is in bits 31:24 of DP_SELECT */
1577                 if (apsel >= 256)
1578                         return ERROR_COMMAND_SYNTAX_ERROR;
1579                 break;
1580         default:
1581                 return ERROR_COMMAND_SYNTAX_ERROR;
1582         }
1583
1584         retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1585         if (retval != ERROR_OK)
1586                 return retval;
1587         retval = dap_run(dap);
1588         if (retval != ERROR_OK)
1589                 return retval;
1590
1591         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1592
1593         return retval;
1594 }
1595
1596 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1597 {
1598         struct target *target = get_current_target(CMD_CTX);
1599         struct arm *arm = target_to_arm(target);
1600         struct adiv5_dap *dap = arm->dap;
1601
1602         uint32_t enable = dap->ti_be_32_quirks;
1603
1604         switch (CMD_ARGC) {
1605         case 0:
1606                 break;
1607         case 1:
1608                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1609                 if (enable > 1)
1610                         return ERROR_COMMAND_SYNTAX_ERROR;
1611                 break;
1612         default:
1613                 return ERROR_COMMAND_SYNTAX_ERROR;
1614         }
1615         dap->ti_be_32_quirks = enable;
1616         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1617                 enable ? "enabled" : "disabled");
1618
1619         return 0;
1620 }
1621
1622 static const struct command_registration dap_commands[] = {
1623         {
1624                 .name = "info",
1625                 .handler = handle_dap_info_command,
1626                 .mode = COMMAND_EXEC,
1627                 .help = "display ROM table for MEM-AP "
1628                         "(default currently selected AP)",
1629                 .usage = "[ap_num]",
1630         },
1631         {
1632                 .name = "apsel",
1633                 .handler = dap_apsel_command,
1634                 .mode = COMMAND_EXEC,
1635                 .help = "Set the currently selected AP (default 0) "
1636                         "and display the result",
1637                 .usage = "[ap_num]",
1638         },
1639         {
1640                 .name = "apcsw",
1641                 .handler = dap_apcsw_command,
1642                 .mode = COMMAND_EXEC,
1643                 .help = "Set csw access bit ",
1644                 .usage = "[sprot]",
1645         },
1646
1647         {
1648                 .name = "apid",
1649                 .handler = dap_apid_command,
1650                 .mode = COMMAND_EXEC,
1651                 .help = "return ID register from AP "
1652                         "(default currently selected AP)",
1653                 .usage = "[ap_num]",
1654         },
1655         {
1656                 .name = "baseaddr",
1657                 .handler = dap_baseaddr_command,
1658                 .mode = COMMAND_EXEC,
1659                 .help = "return debug base address from MEM-AP "
1660                         "(default currently selected AP)",
1661                 .usage = "[ap_num]",
1662         },
1663         {
1664                 .name = "memaccess",
1665                 .handler = dap_memaccess_command,
1666                 .mode = COMMAND_EXEC,
1667                 .help = "set/get number of extra tck for MEM-AP memory "
1668                         "bus access [0-255]",
1669                 .usage = "[cycles]",
1670         },
1671         {
1672                 .name = "ti_be_32_quirks",
1673                 .handler = dap_ti_be_32_quirks_command,
1674                 .mode = COMMAND_CONFIG,
1675                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1676                 .usage = "[enable]",
1677         },
1678         COMMAND_REGISTRATION_DONE
1679 };
1680
1681 const struct command_registration dap_command_handlers[] = {
1682         {
1683                 .name = "dap",
1684                 .mode = COMMAND_EXEC,
1685                 .help = "DAP command group",
1686                 .usage = "",
1687                 .chain = dap_commands,
1688         },
1689         COMMAND_REGISTRATION_DONE
1690 };