1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2009-2010 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * Copyright (C) 2009-2010 by David Brownell *
13 * Copyright (C) 2013 by Andreas Fritiofson *
14 * andreas.fritiofson@gmail.com *
16 * This program is free software; you can redistribute it and/or modify *
17 * it under the terms of the GNU General Public License as published by *
18 * the Free Software Foundation; either version 2 of the License, or *
19 * (at your option) any later version. *
21 * This program is distributed in the hope that it will be useful, *
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
24 * GNU General Public License for more details. *
26 * You should have received a copy of the GNU General Public License *
27 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
28 ***************************************************************************/
32 * This file implements support for the ARM Debug Interface version 5 (ADIv5)
33 * debugging architecture. Compared with previous versions, this includes
34 * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
35 * transport, and focuses on memory mapped resources as defined by the
36 * CoreSight architecture.
38 * A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
39 * basic components: a Debug Port (DP) transporting messages to and from a
40 * debugger, and an Access Port (AP) accessing resources. Three types of DP
41 * are defined. One uses only JTAG for communication, and is called JTAG-DP.
42 * One uses only SWD for communication, and is called SW-DP. The third can
43 * use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
44 * is used to access memory mapped resources and is called a MEM-AP. Also a
45 * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
47 * This programming interface allows DAP pipelined operations through a
48 * transaction queue. This primarily affects AP operations (such as using
49 * a MEM-AP to access memory or registers). If the current transaction has
50 * not finished by the time the next one must begin, and the ORUNDETECT bit
51 * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
52 * further AP operations will fail. There are two basic methods to avoid
53 * such overrun errors. One involves polling for status instead of using
54 * transaction pipelining. The other involves adding delays to ensure the
55 * AP has enough time to complete one operation before starting the next
56 * one. (For JTAG these delays are controlled by memaccess_tck.)
60 * Relevant specifications from ARM include:
62 * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031E
63 * CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
65 * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
66 * Cortex-M3(tm) TRM, ARM DDI 0337G
73 #include "jtag/interface.h"
75 #include "arm_adi_v5.h"
77 #include "transport/transport.h"
78 #include <helper/jep106.h>
79 #include <helper/time_support.h>
80 #include <helper/list.h>
81 #include <helper/jim-nvp.h>
83 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement */
86 uint32_t tar_block_size(uint32_t address)
87 Return the largest block starting at address that does not cross a tar block size alignment boundary
89 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
91 return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
94 /***************************************************************************
96 * DP and MEM-AP register access through APACC and DPACC *
98 ***************************************************************************/
100 static int mem_ap_setup_csw(struct adiv5_ap *ap, uint32_t csw)
102 csw |= ap->csw_default;
104 if (csw != ap->csw_value) {
105 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
106 int retval = dap_queue_ap_write(ap, MEM_AP_REG_CSW, csw);
107 if (retval != ERROR_OK) {
116 static int mem_ap_setup_tar(struct adiv5_ap *ap, uint32_t tar)
118 if (!ap->tar_valid || tar != ap->tar_value) {
119 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
120 int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR, tar);
121 if (retval != ERROR_OK) {
122 ap->tar_valid = false;
126 ap->tar_valid = true;
131 static int mem_ap_read_tar(struct adiv5_ap *ap, uint32_t *tar)
133 int retval = dap_queue_ap_read(ap, MEM_AP_REG_TAR, tar);
134 if (retval != ERROR_OK) {
135 ap->tar_valid = false;
139 retval = dap_run(ap->dap);
140 if (retval != ERROR_OK) {
141 ap->tar_valid = false;
145 ap->tar_value = *tar;
146 ap->tar_valid = true;
150 static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
152 switch (ap->csw_value & CSW_ADDRINC_MASK) {
153 case CSW_ADDRINC_SINGLE:
154 switch (ap->csw_value & CSW_SIZE_MASK) {
164 case CSW_ADDRINC_PACKED:
170 /* mem_ap_update_tar_cache is called after an access to MEM_AP_REG_DRW
172 static void mem_ap_update_tar_cache(struct adiv5_ap *ap)
177 uint32_t inc = mem_ap_get_tar_increment(ap);
178 if (inc >= max_tar_block_size(ap->tar_autoincr_block, ap->tar_value))
179 ap->tar_valid = false;
181 ap->tar_value += inc;
185 * Queue transactions setting up transfer parameters for the
186 * currently selected MEM-AP.
188 * Subsequent transfers using registers like MEM_AP_REG_DRW or MEM_AP_REG_BD2
189 * initiate data reads or writes using memory or peripheral addresses.
190 * If the CSW is configured for it, the TAR may be automatically
191 * incremented after each transfer.
193 * @param ap The MEM-AP.
194 * @param csw MEM-AP Control/Status Word (CSW) register to assign. If this
195 * matches the cached value, the register is not changed.
196 * @param tar MEM-AP Transfer Address Register (TAR) to assign. If this
197 * matches the cached address, the register is not changed.
199 * @return ERROR_OK if the transaction was properly queued, else a fault code.
201 static int mem_ap_setup_transfer(struct adiv5_ap *ap, uint32_t csw, uint32_t tar)
204 retval = mem_ap_setup_csw(ap, csw);
205 if (retval != ERROR_OK)
207 retval = mem_ap_setup_tar(ap, tar);
208 if (retval != ERROR_OK)
214 * Asynchronous (queued) read of a word from memory or a system register.
216 * @param ap The MEM-AP to access.
217 * @param address Address of the 32-bit word to read; it must be
218 * readable by the currently selected MEM-AP.
219 * @param value points to where the word will be stored when the
220 * transaction queue is flushed (assuming no errors).
222 * @return ERROR_OK for success. Otherwise a fault code.
224 int mem_ap_read_u32(struct adiv5_ap *ap, uint32_t address,
229 /* Use banked addressing (REG_BDx) to avoid some link traffic
230 * (updating TAR) when reading several consecutive addresses.
232 retval = mem_ap_setup_transfer(ap,
233 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
234 address & 0xFFFFFFF0);
235 if (retval != ERROR_OK)
238 return dap_queue_ap_read(ap, MEM_AP_REG_BD0 | (address & 0xC), value);
242 * Synchronous read of a word from memory or a system register.
243 * As a side effect, this flushes any queued transactions.
245 * @param ap The MEM-AP to access.
246 * @param address Address of the 32-bit word to read; it must be
247 * readable by the currently selected MEM-AP.
248 * @param value points to where the result will be stored.
250 * @return ERROR_OK for success; *value holds the result.
251 * Otherwise a fault code.
253 int mem_ap_read_atomic_u32(struct adiv5_ap *ap, uint32_t address,
258 retval = mem_ap_read_u32(ap, address, value);
259 if (retval != ERROR_OK)
262 return dap_run(ap->dap);
266 * Asynchronous (queued) write of a word to memory or a system register.
268 * @param ap The MEM-AP to access.
269 * @param address Address to be written; it must be writable by
270 * the currently selected MEM-AP.
271 * @param value Word that will be written to the address when transaction
272 * queue is flushed (assuming no errors).
274 * @return ERROR_OK for success. Otherwise a fault code.
276 int mem_ap_write_u32(struct adiv5_ap *ap, uint32_t address,
281 /* Use banked addressing (REG_BDx) to avoid some link traffic
282 * (updating TAR) when writing several consecutive addresses.
284 retval = mem_ap_setup_transfer(ap,
285 CSW_32BIT | (ap->csw_value & CSW_ADDRINC_MASK),
286 address & 0xFFFFFFF0);
287 if (retval != ERROR_OK)
290 return dap_queue_ap_write(ap, MEM_AP_REG_BD0 | (address & 0xC),
295 * Synchronous write of a word to memory or a system register.
296 * As a side effect, this flushes any queued transactions.
298 * @param ap The MEM-AP to access.
299 * @param address Address to be written; it must be writable by
300 * the currently selected MEM-AP.
301 * @param value Word that will be written.
303 * @return ERROR_OK for success; the data was written. Otherwise a fault code.
305 int mem_ap_write_atomic_u32(struct adiv5_ap *ap, uint32_t address,
308 int retval = mem_ap_write_u32(ap, address, value);
310 if (retval != ERROR_OK)
313 return dap_run(ap->dap);
317 * Synchronous write of a block of memory, using a specific access size.
319 * @param ap The MEM-AP to access.
320 * @param buffer The data buffer to write. No particular alignment is assumed.
321 * @param size Which access size to use, in bytes. 1, 2 or 4.
322 * @param count The number of writes to do (in size units, not bytes).
323 * @param address Address to be written; it must be writable by the currently selected MEM-AP.
324 * @param addrinc Whether the target address should be increased for each write or not. This
325 * should normally be true, except when writing to e.g. a FIFO.
326 * @return ERROR_OK on success, otherwise an error code.
328 static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t size, uint32_t count,
329 uint32_t address, bool addrinc)
331 struct adiv5_dap *dap = ap->dap;
332 size_t nbytes = size * count;
333 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
336 int retval = ERROR_OK;
338 /* TI BE-32 Quirks mode:
339 * Writes on big-endian TMS570 behave very strangely. Observed behavior:
340 * size write address bytes written in order
341 * 4 TAR ^ 0 (val >> 24), (val >> 16), (val >> 8), (val)
342 * 2 TAR ^ 2 (val >> 8), (val)
344 * For example, if you attempt to write a single byte to address 0, the processor
345 * will actually write a byte to address 3.
347 * To make writes of size < 4 work as expected, we xor a value with the address before
348 * setting the TAP, and we set the TAP after every transfer rather then relying on
349 * address increment. */
352 csw_size = CSW_32BIT;
354 } else if (size == 2) {
355 csw_size = CSW_16BIT;
356 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
357 } else if (size == 1) {
359 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
361 return ERROR_TARGET_UNALIGNED_ACCESS;
364 if (ap->unaligned_access_bad && (address % size != 0))
365 return ERROR_TARGET_UNALIGNED_ACCESS;
368 uint32_t this_size = size;
370 /* Select packed transfer if possible */
371 if (addrinc && ap->packed_transfers && nbytes >= 4
372 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
374 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
376 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
379 if (retval != ERROR_OK)
382 retval = mem_ap_setup_tar(ap, address ^ addr_xor);
383 if (retval != ERROR_OK)
386 /* How many source bytes each transfer will consume, and their location in the DRW,
387 * depends on the type of transfer and alignment. See ARM document IHI0031C. */
388 uint32_t outvalue = 0;
389 uint32_t drw_byte_idx = address;
390 if (dap->ti_be_32_quirks) {
393 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
394 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
395 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx++ & 3) ^ addr_xor);
396 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (drw_byte_idx & 3) ^ addr_xor);
399 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx++ & 3) ^ addr_xor);
400 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (drw_byte_idx & 3) ^ addr_xor);
403 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
409 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
410 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
413 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
416 outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
422 retval = dap_queue_ap_write(ap, MEM_AP_REG_DRW, outvalue);
423 if (retval != ERROR_OK)
426 mem_ap_update_tar_cache(ap);
428 address += this_size;
431 /* REVISIT: Might want to have a queued version of this function that does not run. */
432 if (retval == ERROR_OK)
433 retval = dap_run(dap);
435 if (retval != ERROR_OK) {
437 if (mem_ap_read_tar(ap, &tar) == ERROR_OK)
438 LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
440 LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
447 * Synchronous read of a block of memory, using a specific access size.
449 * @param ap The MEM-AP to access.
450 * @param buffer The data buffer to receive the data. No particular alignment is assumed.
451 * @param size Which access size to use, in bytes. 1, 2 or 4.
452 * @param count The number of reads to do (in size units, not bytes).
453 * @param adr Address to be read; it must be readable by the currently selected MEM-AP.
454 * @param addrinc Whether the target address should be increased after each read or not. This
455 * should normally be true, except when reading from e.g. a FIFO.
456 * @return ERROR_OK on success, otherwise an error code.
458 static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint32_t count,
459 uint32_t adr, bool addrinc)
461 struct adiv5_dap *dap = ap->dap;
462 size_t nbytes = size * count;
463 const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
465 uint32_t address = adr;
466 int retval = ERROR_OK;
468 /* TI BE-32 Quirks mode:
469 * Reads on big-endian TMS570 behave strangely differently than writes.
470 * They read from the physical address requested, but with DRW byte-reversed.
471 * For example, a byte read from address 0 will place the result in the high bytes of DRW.
472 * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
476 csw_size = CSW_32BIT;
478 csw_size = CSW_16BIT;
482 return ERROR_TARGET_UNALIGNED_ACCESS;
484 if (ap->unaligned_access_bad && (adr % size != 0))
485 return ERROR_TARGET_UNALIGNED_ACCESS;
487 /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
488 * over-allocation if packed transfers are going to be used, but determining the real need at
489 * this point would be messy. */
490 uint32_t *read_buf = calloc(count, sizeof(uint32_t));
491 /* Multiplication count * sizeof(uint32_t) may overflow, calloc() is safe */
492 uint32_t *read_ptr = read_buf;
493 if (read_buf == NULL) {
494 LOG_ERROR("Failed to allocate read buffer");
498 /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
499 * useful bytes it contains, and their location in the word, depends on the type of transfer
502 uint32_t this_size = size;
504 /* Select packed transfer if possible */
505 if (addrinc && ap->packed_transfers && nbytes >= 4
506 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
508 retval = mem_ap_setup_csw(ap, csw_size | CSW_ADDRINC_PACKED);
510 retval = mem_ap_setup_csw(ap, csw_size | csw_addrincr);
512 if (retval != ERROR_OK)
515 retval = mem_ap_setup_tar(ap, address);
516 if (retval != ERROR_OK)
519 retval = dap_queue_ap_read(ap, MEM_AP_REG_DRW, read_ptr++);
520 if (retval != ERROR_OK)
525 address += this_size;
527 mem_ap_update_tar_cache(ap);
530 if (retval == ERROR_OK)
531 retval = dap_run(dap);
535 nbytes = size * count;
538 /* If something failed, read TAR to find out how much data was successfully read, so we can
539 * at least give the caller what we have. */
540 if (retval != ERROR_OK) {
542 if (mem_ap_read_tar(ap, &tar) == ERROR_OK) {
543 /* TAR is incremented after failed transfer on some devices (eg Cortex-M4) */
544 LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
545 if (nbytes > tar - address)
546 nbytes = tar - address;
548 LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
553 /* Replay loop to populate caller's buffer from the correct word and byte lane */
555 uint32_t this_size = size;
557 if (addrinc && ap->packed_transfers && nbytes >= 4
558 && max_tar_block_size(ap->tar_autoincr_block, address) >= 4) {
562 if (dap->ti_be_32_quirks) {
565 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
566 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
569 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
572 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
577 *buffer++ = *read_ptr >> 8 * (address++ & 3);
578 *buffer++ = *read_ptr >> 8 * (address++ & 3);
581 *buffer++ = *read_ptr >> 8 * (address++ & 3);
584 *buffer++ = *read_ptr >> 8 * (address++ & 3);
596 int mem_ap_read_buf(struct adiv5_ap *ap,
597 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
599 return mem_ap_read(ap, buffer, size, count, address, true);
602 int mem_ap_write_buf(struct adiv5_ap *ap,
603 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
605 return mem_ap_write(ap, buffer, size, count, address, true);
608 int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
609 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
611 return mem_ap_read(ap, buffer, size, count, address, false);
614 int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
615 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
617 return mem_ap_write(ap, buffer, size, count, address, false);
620 /*--------------------------------------------------------------------------*/
623 #define DAP_POWER_DOMAIN_TIMEOUT (10)
625 /*--------------------------------------------------------------------------*/
628 * Invalidate cached DP select and cached TAR and CSW of all APs
630 void dap_invalidate_cache(struct adiv5_dap *dap)
632 dap->select = DP_SELECT_INVALID;
633 dap->last_read = NULL;
636 for (i = 0; i <= 255; i++) {
637 /* force csw and tar write on the next mem-ap access */
638 dap->ap[i].tar_valid = false;
639 dap->ap[i].csw_value = 0;
644 * Initialize a DAP. This sets up the power domains, prepares the DP
645 * for further use and activates overrun checking.
647 * @param dap The DAP being initialized.
649 int dap_dp_init(struct adiv5_dap *dap)
653 LOG_DEBUG("%s", adiv5_dap_name(dap));
655 dap->do_reconnect = false;
656 dap_invalidate_cache(dap);
659 * Early initialize dap->dp_ctrl_stat.
660 * In jtag mode only, if the following queue run (in dap_dp_poll_register)
661 * fails and sets the sticky error, it will trigger the clearing
662 * of the sticky. Without this initialization system and debug power
663 * would be disabled while clearing the sticky error bit.
665 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
668 * This write operation clears the sticky error bit in jtag mode only and
669 * is ignored in swd mode. It also powers-up system and debug domains in
670 * both jtag and swd modes, if not done before.
672 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat | SSTICKYERR);
673 if (retval != ERROR_OK)
676 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
677 if (retval != ERROR_OK)
680 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
681 if (retval != ERROR_OK)
684 /* Check that we have debug power domains activated */
685 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
686 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
687 CDBGPWRUPACK, CDBGPWRUPACK,
688 DAP_POWER_DOMAIN_TIMEOUT);
689 if (retval != ERROR_OK)
692 if (!dap->ignore_syspwrupack) {
693 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
694 retval = dap_dp_poll_register(dap, DP_CTRL_STAT,
695 CSYSPWRUPACK, CSYSPWRUPACK,
696 DAP_POWER_DOMAIN_TIMEOUT);
697 if (retval != ERROR_OK)
701 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
702 if (retval != ERROR_OK)
705 /* With debug power on we can activate OVERRUN checking */
706 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
707 retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
708 if (retval != ERROR_OK)
710 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
711 if (retval != ERROR_OK)
714 retval = dap_run(dap);
715 if (retval != ERROR_OK)
722 * Initialize a DAP or do reconnect if DAP is not accessible.
724 * @param dap The DAP being initialized.
726 int dap_dp_init_or_reconnect(struct adiv5_dap *dap)
728 LOG_DEBUG("%s", adiv5_dap_name(dap));
731 * Early initialize dap->dp_ctrl_stat.
732 * In jtag mode only, if the following atomic reads fail and set the
733 * sticky error, it will trigger the clearing of the sticky. Without this
734 * initialization system and debug power would be disabled while clearing
735 * the sticky error bit.
737 dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
739 dap->do_reconnect = false;
741 dap_dp_read_atomic(dap, DP_CTRL_STAT, NULL);
742 if (dap->do_reconnect) {
743 /* dap connect calls dap_dp_init() after transport dependent initialization */
744 return dap->ops->connect(dap);
746 return dap_dp_init(dap);
751 * Initialize a DAP. This sets up the power domains, prepares the DP
752 * for further use, and arranges to use AP #0 for all AP operations
753 * until dap_ap-select() changes that policy.
755 * @param ap The MEM-AP being initialized.
757 int mem_ap_init(struct adiv5_ap *ap)
759 /* check that we support packed transfers */
762 struct adiv5_dap *dap = ap->dap;
764 ap->tar_valid = false;
765 ap->csw_value = 0; /* force csw and tar write */
766 retval = mem_ap_setup_transfer(ap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
767 if (retval != ERROR_OK)
770 retval = dap_queue_ap_read(ap, MEM_AP_REG_CSW, &csw);
771 if (retval != ERROR_OK)
774 retval = dap_queue_ap_read(ap, MEM_AP_REG_CFG, &cfg);
775 if (retval != ERROR_OK)
778 retval = dap_run(dap);
779 if (retval != ERROR_OK)
782 if (csw & CSW_ADDRINC_PACKED)
783 ap->packed_transfers = true;
785 ap->packed_transfers = false;
787 /* Packed transfers on TI BE-32 processors do not work correctly in
789 if (dap->ti_be_32_quirks)
790 ap->packed_transfers = false;
792 LOG_DEBUG("MEM_AP Packed Transfers: %s",
793 ap->packed_transfers ? "enabled" : "disabled");
795 /* The ARM ADI spec leaves implementation-defined whether unaligned
796 * memory accesses work, only work partially, or cause a sticky error.
797 * On TI BE-32 processors, reads seem to return garbage in some bytes
798 * and unaligned writes seem to cause a sticky error.
799 * TODO: it would be nice to have a way to detect whether unaligned
800 * operations are supported on other processors. */
801 ap->unaligned_access_bad = dap->ti_be_32_quirks;
803 LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
804 !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
810 * Put the debug link into SWD mode, if the target supports it.
811 * The link's initial mode may be either JTAG (for example,
812 * with SWJ-DP after reset) or SWD.
814 * Note that targets using the JTAG-DP do not support SWD, and that
815 * some targets which could otherwise support it may have been
816 * configured to disable SWD signaling
818 * @param dap The DAP used
819 * @return ERROR_OK or else a fault code.
821 int dap_to_swd(struct adiv5_dap *dap)
823 LOG_DEBUG("Enter SWD mode");
825 return dap_send_sequence(dap, JTAG_TO_SWD);
829 * Put the debug link into JTAG mode, if the target supports it.
830 * The link's initial mode may be either SWD or JTAG.
832 * Note that targets implemented with SW-DP do not support JTAG, and
833 * that some targets which could otherwise support it may have been
834 * configured to disable JTAG signaling
836 * @param dap The DAP used
837 * @return ERROR_OK or else a fault code.
839 int dap_to_jtag(struct adiv5_dap *dap)
841 LOG_DEBUG("Enter JTAG mode");
843 return dap_send_sequence(dap, SWD_TO_JTAG);
846 /* CID interpretation -- see ARM IHI 0029B section 3
847 * and ARM IHI 0031A table 13-3.
849 static const char *class_description[16] = {
850 "Reserved", "ROM table", "Reserved", "Reserved",
851 "Reserved", "Reserved", "Reserved", "Reserved",
852 "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
853 "Reserved", "OptimoDE DESS",
854 "Generic IP component", "PrimeCell or System component"
857 static bool is_dap_cid_ok(uint32_t cid)
859 return (cid & 0xffff0fff) == 0xb105000d;
863 * This function checks the ID for each access port to find the requested Access Port type
865 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_ap **ap_out)
869 /* Maximum AP number is 255 since the SELECT register is 8 bits */
870 for (ap_num = 0; ap_num <= DP_APSEL_MAX; ap_num++) {
872 /* read the IDR register of the Access Port */
875 int retval = dap_queue_ap_read(dap_ap(dap, ap_num), AP_REG_IDR, &id_val);
876 if (retval != ERROR_OK)
879 retval = dap_run(dap);
883 * 27-24 : JEDEC bank (0x4 for ARM)
884 * 23-17 : JEDEC code (0x3B for ARM)
885 * 16-13 : Class (0b1000=Mem-AP)
887 * 7-4 : AP Variant (non-zero for JTAG-AP)
888 * 3-0 : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
891 /* Reading register for a non-existent AP should not cause an error,
892 * but just to be sure, try to continue searching if an error does happen.
894 if ((retval == ERROR_OK) && /* Register read success */
895 ((id_val & IDR_JEP106) == IDR_JEP106_ARM) && /* Jedec codes match */
896 ((id_val & IDR_TYPE) == type_to_find)) { /* type matches*/
898 LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
899 (type_to_find == AP_TYPE_AHB3_AP) ? "AHB3-AP" :
900 (type_to_find == AP_TYPE_AHB5_AP) ? "AHB5-AP" :
901 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
902 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
903 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
906 *ap_out = &dap->ap[ap_num];
911 LOG_DEBUG("No %s found",
912 (type_to_find == AP_TYPE_AHB3_AP) ? "AHB3-AP" :
913 (type_to_find == AP_TYPE_AHB5_AP) ? "AHB5-AP" :
914 (type_to_find == AP_TYPE_APB_AP) ? "APB-AP" :
915 (type_to_find == AP_TYPE_AXI_AP) ? "AXI-AP" :
916 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
920 int dap_get_debugbase(struct adiv5_ap *ap,
921 uint32_t *dbgbase, uint32_t *apid)
923 struct adiv5_dap *dap = ap->dap;
926 retval = dap_queue_ap_read(ap, MEM_AP_REG_BASE, dbgbase);
927 if (retval != ERROR_OK)
929 retval = dap_queue_ap_read(ap, AP_REG_IDR, apid);
930 if (retval != ERROR_OK)
932 retval = dap_run(dap);
933 if (retval != ERROR_OK)
939 int dap_lookup_cs_component(struct adiv5_ap *ap,
940 uint32_t dbgbase, uint8_t type, uint32_t *addr, int32_t *idx)
942 uint32_t romentry, entry_offset = 0, component_base, devtype;
948 retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) |
949 entry_offset, &romentry);
950 if (retval != ERROR_OK)
953 component_base = (dbgbase & 0xFFFFF000)
954 + (romentry & 0xFFFFF000);
956 if (romentry & 0x1) {
958 retval = mem_ap_read_atomic_u32(ap, component_base | 0xff4, &c_cid1);
959 if (retval != ERROR_OK) {
960 LOG_ERROR("Can't read component with base address 0x%" PRIx32
961 ", the corresponding core might be turned off", component_base);
964 if (((c_cid1 >> 4) & 0x0f) == 1) {
965 retval = dap_lookup_cs_component(ap, component_base,
967 if (retval == ERROR_OK)
969 if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
973 retval = mem_ap_read_atomic_u32(ap,
974 (component_base & 0xfffff000) | 0xfcc,
976 if (retval != ERROR_OK)
978 if ((devtype & 0xff) == type) {
980 *addr = component_base;
987 } while (romentry > 0);
990 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
995 static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
997 assert((component_base & 0xFFF) == 0);
998 assert(ap != NULL && cid != NULL && pid != NULL);
1000 uint32_t cid0, cid1, cid2, cid3;
1001 uint32_t pid0, pid1, pid2, pid3, pid4;
1004 /* IDs are in last 4K section */
1005 retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
1006 if (retval != ERROR_OK)
1008 retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
1009 if (retval != ERROR_OK)
1011 retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
1012 if (retval != ERROR_OK)
1014 retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
1015 if (retval != ERROR_OK)
1017 retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
1018 if (retval != ERROR_OK)
1020 retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
1021 if (retval != ERROR_OK)
1023 retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
1024 if (retval != ERROR_OK)
1026 retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
1027 if (retval != ERROR_OK)
1029 retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
1030 if (retval != ERROR_OK)
1033 retval = dap_run(ap->dap);
1034 if (retval != ERROR_OK)
1037 *cid = (cid3 & 0xff) << 24
1038 | (cid2 & 0xff) << 16
1039 | (cid1 & 0xff) << 8
1041 *pid = (uint64_t)(pid4 & 0xff) << 32
1042 | (pid3 & 0xff) << 24
1043 | (pid2 & 0xff) << 16
1044 | (pid1 & 0xff) << 8
1050 /* The designer identity code is encoded as:
1051 * bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
1052 * bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
1053 * a legacy ASCII Identity Code.
1054 * bits 6:0 : JEP106 Identity Code (without parity) or legacy ASCII code according to bit 7.
1055 * JEP106 is a standard available from jedec.org
1058 /* Part number interpretations are from Cortex
1059 * core specs, the CoreSight components TRM
1060 * (ARM DDI 0314H), CoreSight System Design
1061 * Guide (ARM DGI 0012D) and ETM specs; also
1062 * from chip observation (e.g. TI SDTI).
1065 /* The legacy code only used the part number field to identify CoreSight peripherals.
1066 * This meant that the same part number from two different manufacturers looked the same.
1067 * It is desirable for all future additions to identify with both part number and JEP106.
1068 * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
1071 #define ANY_ID 0x1000
1073 #define ARM_ID 0x4BB
1075 static const struct {
1076 uint16_t designer_id;
1080 } dap_partnums[] = {
1081 { ARM_ID, 0x000, "Cortex-M3 SCS", "(System Control Space)", },
1082 { ARM_ID, 0x001, "Cortex-M3 ITM", "(Instrumentation Trace Module)", },
1083 { ARM_ID, 0x002, "Cortex-M3 DWT", "(Data Watchpoint and Trace)", },
1084 { ARM_ID, 0x003, "Cortex-M3 FPB", "(Flash Patch and Breakpoint)", },
1085 { ARM_ID, 0x008, "Cortex-M0 SCS", "(System Control Space)", },
1086 { ARM_ID, 0x00a, "Cortex-M0 DWT", "(Data Watchpoint and Trace)", },
1087 { ARM_ID, 0x00b, "Cortex-M0 BPU", "(Breakpoint Unit)", },
1088 { ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
1089 { ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
1090 { ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
1091 { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
1092 { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
1093 { ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
1094 { ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
1095 { ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
1096 { ARM_ID, 0x4a3, "Cortex-A53 ROM", "(v7 Memory Map ROM Table)", },
1097 { ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
1098 { ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
1099 { ARM_ID, 0x4aa, "Cortex-A35 ROM", "(v8 Memory Map ROM Table)", },
1100 { ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
1101 { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
1102 { ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
1103 { ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
1104 { ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
1105 { ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
1106 { ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
1107 { ARM_ID, 0x4e0, "Cortex-A35 ROM", "(v7 Memory Map ROM Table)", },
1108 { ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
1109 { ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
1110 { ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
1111 { ARM_ID, 0x909, "CoreSight ATBR", "(Advanced Trace Bus Replicator)", },
1112 { ARM_ID, 0x910, "CoreSight ETM9", "(Embedded Trace)", },
1113 { ARM_ID, 0x912, "CoreSight TPIU", "(Trace Port Interface Unit)", },
1114 { ARM_ID, 0x913, "CoreSight ITM", "(Instrumentation Trace Macrocell)", },
1115 { ARM_ID, 0x914, "CoreSight SWO", "(Single Wire Output)", },
1116 { ARM_ID, 0x917, "CoreSight HTM", "(AHB Trace Macrocell)", },
1117 { ARM_ID, 0x920, "CoreSight ETM11", "(Embedded Trace)", },
1118 { ARM_ID, 0x921, "Cortex-A8 ETM", "(Embedded Trace)", },
1119 { ARM_ID, 0x922, "Cortex-A8 CTI", "(Cross Trigger)", },
1120 { ARM_ID, 0x923, "Cortex-M3 TPIU", "(Trace Port Interface Unit)", },
1121 { ARM_ID, 0x924, "Cortex-M3 ETM", "(Embedded Trace)", },
1122 { ARM_ID, 0x925, "Cortex-M4 ETM", "(Embedded Trace)", },
1123 { ARM_ID, 0x930, "Cortex-R4 ETM", "(Embedded Trace)", },
1124 { ARM_ID, 0x931, "Cortex-R5 ETM", "(Embedded Trace)", },
1125 { ARM_ID, 0x932, "CoreSight MTB-M0+", "(Micro Trace Buffer)", },
1126 { ARM_ID, 0x941, "CoreSight TPIU-Lite", "(Trace Port Interface Unit)", },
1127 { ARM_ID, 0x950, "Cortex-A9 PTM", "(Program Trace Macrocell)", },
1128 { ARM_ID, 0x955, "Cortex-A5 ETM", "(Embedded Trace)", },
1129 { ARM_ID, 0x95a, "Cortex-A72 ETM", "(Embedded Trace)", },
1130 { ARM_ID, 0x95b, "Cortex-A17 PTM", "(Program Trace Macrocell)", },
1131 { ARM_ID, 0x95d, "Cortex-A53 ETM", "(Embedded Trace)", },
1132 { ARM_ID, 0x95e, "Cortex-A57 ETM", "(Embedded Trace)", },
1133 { ARM_ID, 0x95f, "Cortex-A15 PTM", "(Program Trace Macrocell)", },
1134 { ARM_ID, 0x961, "CoreSight TMC", "(Trace Memory Controller)", },
1135 { ARM_ID, 0x962, "CoreSight STM", "(System Trace Macrocell)", },
1136 { ARM_ID, 0x975, "Cortex-M7 ETM", "(Embedded Trace)", },
1137 { ARM_ID, 0x9a0, "CoreSight PMU", "(Performance Monitoring Unit)", },
1138 { ARM_ID, 0x9a1, "Cortex-M4 TPIU", "(Trace Port Interface Unit)", },
1139 { ARM_ID, 0x9a4, "CoreSight GPR", "(Granular Power Requester)", },
1140 { ARM_ID, 0x9a5, "Cortex-A5 PMU", "(Performance Monitor Unit)", },
1141 { ARM_ID, 0x9a7, "Cortex-A7 PMU", "(Performance Monitor Unit)", },
1142 { ARM_ID, 0x9a8, "Cortex-A53 CTI", "(Cross Trigger)", },
1143 { ARM_ID, 0x9a9, "Cortex-M7 TPIU", "(Trace Port Interface Unit)", },
1144 { ARM_ID, 0x9ae, "Cortex-A17 PMU", "(Performance Monitor Unit)", },
1145 { ARM_ID, 0x9af, "Cortex-A15 PMU", "(Performance Monitor Unit)", },
1146 { ARM_ID, 0x9b7, "Cortex-R7 PMU", "(Performance Monitor Unit)", },
1147 { ARM_ID, 0x9d3, "Cortex-A53 PMU", "(Performance Monitor Unit)", },
1148 { ARM_ID, 0x9d7, "Cortex-A57 PMU", "(Performance Monitor Unit)", },
1149 { ARM_ID, 0x9d8, "Cortex-A72 PMU", "(Performance Monitor Unit)", },
1150 { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM", "(Performance Monitor Unit/Cross Trigger/ETM)", },
1151 { ARM_ID, 0xc05, "Cortex-A5 Debug", "(Debug Unit)", },
1152 { ARM_ID, 0xc07, "Cortex-A7 Debug", "(Debug Unit)", },
1153 { ARM_ID, 0xc08, "Cortex-A8 Debug", "(Debug Unit)", },
1154 { ARM_ID, 0xc09, "Cortex-A9 Debug", "(Debug Unit)", },
1155 { ARM_ID, 0xc0e, "Cortex-A17 Debug", "(Debug Unit)", },
1156 { ARM_ID, 0xc0f, "Cortex-A15 Debug", "(Debug Unit)", },
1157 { ARM_ID, 0xc14, "Cortex-R4 Debug", "(Debug Unit)", },
1158 { ARM_ID, 0xc15, "Cortex-R5 Debug", "(Debug Unit)", },
1159 { ARM_ID, 0xc17, "Cortex-R7 Debug", "(Debug Unit)", },
1160 { ARM_ID, 0xd03, "Cortex-A53 Debug", "(Debug Unit)", },
1161 { ARM_ID, 0xd04, "Cortex-A35 Debug", "(Debug Unit)", },
1162 { ARM_ID, 0xd07, "Cortex-A57 Debug", "(Debug Unit)", },
1163 { ARM_ID, 0xd08, "Cortex-A72 Debug", "(Debug Unit)", },
1164 { 0x097, 0x9af, "MSP432 ROM", "(ROM Table)" },
1165 { 0x09f, 0xcd0, "Atmel CPU with DSU", "(CPU)" },
1166 { 0x0c1, 0x1db, "XMC4500 ROM", "(ROM Table)" },
1167 { 0x0c1, 0x1df, "XMC4700/4800 ROM", "(ROM Table)" },
1168 { 0x0c1, 0x1ed, "XMC1000 ROM", "(ROM Table)" },
1169 { 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
1170 { 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
1171 { 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
1172 { 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
1173 { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
1174 { 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
1175 { 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
1176 /* legacy comment: 0x113: what? */
1177 { ANY_ID, 0x120, "TI SDTI", "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
1178 { ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
1181 static int dap_rom_display(struct command_invocation *cmd,
1182 struct adiv5_ap *ap, uint32_t dbgbase, int depth)
1190 command_print(cmd, "\tTables too deep");
1195 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
1197 uint32_t base_addr = dbgbase & 0xFFFFF000;
1198 command_print(cmd, "\t\tComponent base address 0x%08" PRIx32, base_addr);
1200 retval = dap_read_part_id(ap, base_addr, &cid, &pid);
1201 if (retval != ERROR_OK) {
1202 command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
1203 return ERROR_OK; /* Don't abort recursion */
1206 if (!is_dap_cid_ok(cid)) {
1207 command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
1208 return ERROR_OK; /* Don't abort recursion */
1211 /* component may take multiple 4K pages */
1212 uint32_t size = (pid >> 36) & 0xf;
1214 command_print(cmd, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
1216 command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
1218 uint8_t class = (cid >> 12) & 0xf;
1219 uint16_t part_num = pid & 0xfff;
1220 uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
1222 if (designer_id & 0x80) {
1224 command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
1225 designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
1227 /* Legacy ASCII ID, clear invalid bits */
1228 designer_id &= 0x7f;
1229 command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
1230 designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
1233 /* default values to be overwritten upon finding a match */
1234 const char *type = "Unrecognized";
1235 const char *full = "";
1237 /* search dap_partnums[] array for a match */
1238 for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
1240 if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
1243 if (dap_partnums[entry].part_num != part_num)
1246 type = dap_partnums[entry].type;
1247 full = dap_partnums[entry].full;
1251 command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
1252 command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
1254 if (class == 1) { /* ROM Table */
1256 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
1257 if (retval != ERROR_OK)
1261 command_print(cmd, "\t\tMEMTYPE system memory present on bus");
1263 command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
1265 /* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
1266 for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
1268 retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
1269 if (retval != ERROR_OK)
1271 command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
1272 tabs, entry_offset, romentry);
1273 if (romentry & 0x01) {
1275 retval = dap_rom_display(cmd, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
1276 if (retval != ERROR_OK)
1278 } else if (romentry != 0) {
1279 command_print(cmd, "\t\tComponent not present");
1281 command_print(cmd, "\t%s\tEnd of ROM table", tabs);
1285 } else if (class == 9) { /* CoreSight component */
1286 const char *major = "Reserved", *subtype = "Reserved";
1289 retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
1290 if (retval != ERROR_OK)
1292 unsigned minor = (devtype >> 4) & 0x0f;
1293 switch (devtype & 0x0f) {
1295 major = "Miscellaneous";
1301 subtype = "Validation component";
1306 major = "Trace Sink";
1323 major = "Trace Link";
1329 subtype = "Funnel, router";
1335 subtype = "FIFO, buffer";
1340 major = "Trace Source";
1346 subtype = "Processor";
1352 subtype = "Engine/Coprocessor";
1358 subtype = "Software";
1363 major = "Debug Control";
1369 subtype = "Trigger Matrix";
1372 subtype = "Debug Auth";
1375 subtype = "Power Requestor";
1380 major = "Debug Logic";
1386 subtype = "Processor";
1392 subtype = "Engine/Coprocessor";
1403 major = "Performance Monitor";
1409 subtype = "Processor";
1415 subtype = "Engine/Coprocessor";
1426 command_print(cmd, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1427 (uint8_t)(devtype & 0xff),
1429 /* REVISIT also show 0xfc8 DevId */
1435 int dap_info_command(struct command_invocation *cmd,
1436 struct adiv5_ap *ap)
1439 uint32_t dbgbase, apid;
1442 /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
1443 retval = dap_get_debugbase(ap, &dbgbase, &apid);
1444 if (retval != ERROR_OK)
1447 command_print(cmd, "AP ID register 0x%8.8" PRIx32, apid);
1449 command_print(cmd, "No AP found at this ap 0x%x", ap->ap_num);
1453 switch (apid & (IDR_JEP106 | IDR_TYPE)) {
1454 case IDR_JEP106_ARM | AP_TYPE_JTAG_AP:
1455 command_print(cmd, "\tType is JTAG-AP");
1457 case IDR_JEP106_ARM | AP_TYPE_AHB3_AP:
1458 command_print(cmd, "\tType is MEM-AP AHB3");
1460 case IDR_JEP106_ARM | AP_TYPE_AHB5_AP:
1461 command_print(cmd, "\tType is MEM-AP AHB5");
1463 case IDR_JEP106_ARM | AP_TYPE_APB_AP:
1464 command_print(cmd, "\tType is MEM-AP APB");
1466 case IDR_JEP106_ARM | AP_TYPE_AXI_AP:
1467 command_print(cmd, "\tType is MEM-AP AXI");
1470 command_print(cmd, "\tUnknown AP type");
1474 /* NOTE: a MEM-AP may have a single CoreSight component that's
1475 * not a ROM table ... or have no such components at all.
1477 mem_ap = (apid & IDR_CLASS) == AP_CLASS_MEM_AP;
1479 command_print(cmd, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
1481 if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
1482 command_print(cmd, "\tNo ROM table present");
1485 command_print(cmd, "\tValid ROM table present");
1487 command_print(cmd, "\tROM table in legacy format");
1489 dap_rom_display(cmd, ap, dbgbase & 0xFFFFF000, 0);
1496 enum adiv5_cfg_param {
1500 CFG_CTIBASE, /* DEPRECATED */
1503 static const struct jim_nvp nvp_config_opts[] = {
1504 { .name = "-dap", .value = CFG_DAP },
1505 { .name = "-ap-num", .value = CFG_AP_NUM },
1506 { .name = "-baseaddr", .value = CFG_BASEADDR },
1507 { .name = "-ctibase", .value = CFG_CTIBASE }, /* DEPRECATED */
1508 { .name = NULL, .value = -1 }
1511 static int adiv5_jim_spot_configure(struct jim_getopt_info *goi,
1512 struct adiv5_dap **dap_p, int *ap_num_p, uint32_t *base_p)
1517 Jim_SetEmptyResult(goi->interp);
1520 int e = jim_nvp_name2value_obj(goi->interp, nvp_config_opts,
1523 return JIM_CONTINUE;
1525 /* base_p can be NULL, then '-baseaddr' option is treated as unknown */
1526 if (!base_p && (n->value == CFG_BASEADDR || n->value == CFG_CTIBASE))
1527 return JIM_CONTINUE;
1529 e = jim_getopt_obj(goi, NULL);
1535 if (goi->isconfigure) {
1537 struct adiv5_dap *dap;
1538 e = jim_getopt_obj(goi, &o_t);
1541 dap = dap_instance_by_jim_obj(goi->interp, o_t);
1543 Jim_SetResultString(goi->interp, "DAP name invalid!", -1);
1546 if (*dap_p && *dap_p != dap) {
1547 Jim_SetResultString(goi->interp,
1548 "DAP assignment cannot be changed!", -1);
1556 Jim_SetResultString(goi->interp, "DAP not configured", -1);
1559 Jim_SetResultString(goi->interp, adiv5_dap_name(*dap_p), -1);
1564 if (goi->isconfigure) {
1566 e = jim_getopt_wide(goi, &ap_num);
1569 if (ap_num < 0 || ap_num > DP_APSEL_MAX) {
1570 Jim_SetResultString(goi->interp, "Invalid AP number!", -1);
1577 if (*ap_num_p == DP_APSEL_INVALID) {
1578 Jim_SetResultString(goi->interp, "AP number not configured", -1);
1581 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *ap_num_p));
1586 LOG_WARNING("DEPRECATED! use \'-baseaddr' not \'-ctibase\'");
1589 if (goi->isconfigure) {
1591 e = jim_getopt_wide(goi, &base);
1594 *base_p = (uint32_t)base;
1598 Jim_SetResult(goi->interp, Jim_NewIntObj(goi->interp, *base_p));
1606 Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "NO PARAMS");
1610 int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
1612 struct adiv5_private_config *pc;
1615 pc = (struct adiv5_private_config *)target->private_config;
1617 pc = calloc(1, sizeof(struct adiv5_private_config));
1618 pc->ap_num = DP_APSEL_INVALID;
1619 target->private_config = pc;
1622 target->has_dap = true;
1624 e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
1628 if (pc->dap && !target->dap_configured) {
1629 if (target->tap_configured) {
1631 Jim_SetResultString(goi->interp,
1632 "-chain-position and -dap configparams are mutually exclusive!", -1);
1635 target->tap = pc->dap->tap;
1636 target->dap_configured = true;
1642 int adiv5_verify_config(struct adiv5_private_config *pc)
1647 if (pc->dap == NULL)
1653 int adiv5_jim_mem_ap_spot_configure(struct adiv5_mem_ap_spot *cfg,
1654 struct jim_getopt_info *goi)
1656 return adiv5_jim_spot_configure(goi, &cfg->dap, &cfg->ap_num, &cfg->base);
1659 int adiv5_mem_ap_spot_init(struct adiv5_mem_ap_spot *p)
1662 p->ap_num = DP_APSEL_INVALID;
1667 COMMAND_HANDLER(handle_dap_info_command)
1669 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1677 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1678 if (apsel > DP_APSEL_MAX) {
1679 command_print(CMD, "Invalid AP number");
1680 return ERROR_COMMAND_ARGUMENT_INVALID;
1684 return ERROR_COMMAND_SYNTAX_ERROR;
1687 return dap_info_command(CMD, &dap->ap[apsel]);
1690 COMMAND_HANDLER(dap_baseaddr_command)
1692 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1693 uint32_t apsel, baseaddr;
1701 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1702 /* AP address is in bits 31:24 of DP_SELECT */
1703 if (apsel > DP_APSEL_MAX) {
1704 command_print(CMD, "Invalid AP number");
1705 return ERROR_COMMAND_ARGUMENT_INVALID;
1709 return ERROR_COMMAND_SYNTAX_ERROR;
1712 /* NOTE: assumes we're talking to a MEM-AP, which
1713 * has a base address. There are other kinds of AP,
1714 * though they're not common for now. This should
1715 * use the ID register to verify it's a MEM-AP.
1717 retval = dap_queue_ap_read(dap_ap(dap, apsel), MEM_AP_REG_BASE, &baseaddr);
1718 if (retval != ERROR_OK)
1720 retval = dap_run(dap);
1721 if (retval != ERROR_OK)
1724 command_print(CMD, "0x%8.8" PRIx32, baseaddr);
1729 COMMAND_HANDLER(dap_memaccess_command)
1731 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1732 uint32_t memaccess_tck;
1736 memaccess_tck = dap->ap[dap->apsel].memaccess_tck;
1739 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1742 return ERROR_COMMAND_SYNTAX_ERROR;
1744 dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
1746 command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
1747 dap->ap[dap->apsel].memaccess_tck);
1752 COMMAND_HANDLER(dap_apsel_command)
1754 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1759 command_print(CMD, "%" PRIu32, dap->apsel);
1762 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1763 /* AP address is in bits 31:24 of DP_SELECT */
1764 if (apsel > DP_APSEL_MAX) {
1765 command_print(CMD, "Invalid AP number");
1766 return ERROR_COMMAND_ARGUMENT_INVALID;
1770 return ERROR_COMMAND_SYNTAX_ERROR;
1777 COMMAND_HANDLER(dap_apcsw_command)
1779 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1780 uint32_t apcsw = dap->ap[dap->apsel].csw_default;
1781 uint32_t csw_val, csw_mask;
1785 command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
1789 if (strcmp(CMD_ARGV[0], "default") == 0)
1790 csw_val = CSW_AHB_DEFAULT;
1792 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1794 if (csw_val & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1795 LOG_ERROR("CSW value cannot include 'Size' and 'AddrInc' bit-fields");
1796 return ERROR_COMMAND_ARGUMENT_INVALID;
1801 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
1802 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], csw_mask);
1803 if (csw_mask & (CSW_SIZE_MASK | CSW_ADDRINC_MASK)) {
1804 LOG_ERROR("CSW mask cannot include 'Size' and 'AddrInc' bit-fields");
1805 return ERROR_COMMAND_ARGUMENT_INVALID;
1807 apcsw = (apcsw & ~csw_mask) | (csw_val & csw_mask);
1810 return ERROR_COMMAND_SYNTAX_ERROR;
1812 dap->ap[dap->apsel].csw_default = apcsw;
1819 COMMAND_HANDLER(dap_apid_command)
1821 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1822 uint32_t apsel, apid;
1830 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1831 /* AP address is in bits 31:24 of DP_SELECT */
1832 if (apsel > DP_APSEL_MAX) {
1833 command_print(CMD, "Invalid AP number");
1834 return ERROR_COMMAND_ARGUMENT_INVALID;
1838 return ERROR_COMMAND_SYNTAX_ERROR;
1841 retval = dap_queue_ap_read(dap_ap(dap, apsel), AP_REG_IDR, &apid);
1842 if (retval != ERROR_OK)
1844 retval = dap_run(dap);
1845 if (retval != ERROR_OK)
1848 command_print(CMD, "0x%8.8" PRIx32, apid);
1853 COMMAND_HANDLER(dap_apreg_command)
1855 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1856 uint32_t apsel, reg, value;
1857 struct adiv5_ap *ap;
1860 if (CMD_ARGC < 2 || CMD_ARGC > 3)
1861 return ERROR_COMMAND_SYNTAX_ERROR;
1863 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1864 /* AP address is in bits 31:24 of DP_SELECT */
1865 if (apsel > DP_APSEL_MAX) {
1866 command_print(CMD, "Invalid AP number");
1867 return ERROR_COMMAND_ARGUMENT_INVALID;
1870 ap = dap_ap(dap, apsel);
1872 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], reg);
1873 if (reg >= 256 || (reg & 3)) {
1874 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
1875 return ERROR_COMMAND_ARGUMENT_INVALID;
1878 if (CMD_ARGC == 3) {
1879 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
1881 case MEM_AP_REG_CSW:
1882 ap->csw_value = 0; /* invalid, in case write fails */
1883 retval = dap_queue_ap_write(ap, reg, value);
1884 if (retval == ERROR_OK)
1885 ap->csw_value = value;
1887 case MEM_AP_REG_TAR:
1888 ap->tar_valid = false; /* invalid, force write */
1889 retval = mem_ap_setup_tar(ap, value);
1892 retval = dap_queue_ap_write(ap, reg, value);
1896 retval = dap_queue_ap_read(ap, reg, &value);
1898 if (retval == ERROR_OK)
1899 retval = dap_run(dap);
1901 if (retval != ERROR_OK)
1905 command_print(CMD, "0x%08" PRIx32, value);
1910 COMMAND_HANDLER(dap_dpreg_command)
1912 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1913 uint32_t reg, value;
1916 if (CMD_ARGC < 1 || CMD_ARGC > 2)
1917 return ERROR_COMMAND_SYNTAX_ERROR;
1919 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg);
1920 if (reg >= 256 || (reg & 3)) {
1921 command_print(CMD, "Invalid reg value (should be less than 256 and 4 bytes aligned)");
1922 return ERROR_COMMAND_ARGUMENT_INVALID;
1925 if (CMD_ARGC == 2) {
1926 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1927 retval = dap_queue_dp_write(dap, reg, value);
1929 retval = dap_queue_dp_read(dap, reg, &value);
1931 if (retval == ERROR_OK)
1932 retval = dap_run(dap);
1934 if (retval != ERROR_OK)
1938 command_print(CMD, "0x%08" PRIx32, value);
1943 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1945 struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
1946 return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->ti_be_32_quirks,
1947 "TI BE-32 quirks mode");
1950 const struct command_registration dap_instance_commands[] = {
1953 .handler = handle_dap_info_command,
1954 .mode = COMMAND_EXEC,
1955 .help = "display ROM table for MEM-AP "
1956 "(default currently selected AP)",
1957 .usage = "[ap_num]",
1961 .handler = dap_apsel_command,
1962 .mode = COMMAND_ANY,
1963 .help = "Set the currently selected AP (default 0) "
1964 "and display the result",
1965 .usage = "[ap_num]",
1969 .handler = dap_apcsw_command,
1970 .mode = COMMAND_ANY,
1971 .help = "Set CSW default bits",
1972 .usage = "[value [mask]]",
1977 .handler = dap_apid_command,
1978 .mode = COMMAND_EXEC,
1979 .help = "return ID register from AP "
1980 "(default currently selected AP)",
1981 .usage = "[ap_num]",
1985 .handler = dap_apreg_command,
1986 .mode = COMMAND_EXEC,
1987 .help = "read/write a register from AP "
1988 "(reg is byte address of a word register, like 0 4 8...)",
1989 .usage = "ap_num reg [value]",
1993 .handler = dap_dpreg_command,
1994 .mode = COMMAND_EXEC,
1995 .help = "read/write a register from DP "
1996 "(reg is byte address (bank << 4 | reg) of a word register, like 0 4 8...)",
1997 .usage = "reg [value]",
2001 .handler = dap_baseaddr_command,
2002 .mode = COMMAND_EXEC,
2003 .help = "return debug base address from MEM-AP "
2004 "(default currently selected AP)",
2005 .usage = "[ap_num]",
2008 .name = "memaccess",
2009 .handler = dap_memaccess_command,
2010 .mode = COMMAND_EXEC,
2011 .help = "set/get number of extra tck for MEM-AP memory "
2012 "bus access [0-255]",
2013 .usage = "[cycles]",
2016 .name = "ti_be_32_quirks",
2017 .handler = dap_ti_be_32_quirks_command,
2018 .mode = COMMAND_CONFIG,
2019 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
2020 .usage = "[enable]",
2022 COMMAND_REGISTRATION_DONE