git.gag.com Git - fw/openocd/blob - src/target/arm_adi_v5.c

   1 /***************************************************************************
   2  *   Copyright (C) 2006 by Magnus Lundin                                   *
   3  *   lundin@mlu.mine.nu                                                    *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009-2010 by Oyvind Harboe                              *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   Copyright (C) 2009-2010 by David Brownell                             *
  12  *                                                                         *
  13  *   Copyright (C) 2013 by Andreas Fritiofson                              *
  14  *   andreas.fritiofson@gmail.com                                          *
  15  *                                                                         *
  16  *   This program is free software; you can redistribute it and/or modify  *
  17  *   it under the terms of the GNU General Public License as published by  *
  18  *   the Free Software Foundation; either version 2 of the License, or     *
  19  *   (at your option) any later version.                                   *
  20  *                                                                         *
  21  *   This program is distributed in the hope that it will be useful,       *
  22  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  23  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  24  *   GNU General Public License for more details.                          *
  25  *                                                                         *
  26  *   You should have received a copy of the GNU General Public License     *
  27  *   along with this program; if not, write to the                         *
  28  *   Free Software Foundation, Inc.,                                       *
  29  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  30  ***************************************************************************/
  31
  32 /**
  33  * @file
  34  * This file implements support for the ARM Debug Interface version 5 (ADIv5)
  35  * debugging architecture.  Compared with previous versions, this includes
  36  * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
  37  * transport, and focusses on memory mapped resources as defined by the
  38  * CoreSight architecture.
  39  *
  40  * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
  41  * basic components:  a Debug Port (DP) transporting messages to and from a
  42  * debugger, and an Access Port (AP) accessing resources.  Three types of DP
  43  * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
  44  * One uses only SWD for communication, and is called SW-DP.  The third can
  45  * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
  46  * is used to access memory mapped resources and is called a MEM-AP.  Also a
  47  * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
  48  *
  49  * This programming interface allows DAP pipelined operations through a
  50  * transaction queue.  This primarily affects AP operations (such as using
  51  * a MEM-AP to access memory or registers).  If the current transaction has
  52  * not finished by the time the next one must begin, and the ORUNDETECT bit
  53  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  54  * further AP operations will fail.  There are two basic methods to avoid
  55  * such overrun errors.  One involves polling for status instead of using
  56  * transaction piplining.  The other involves adding delays to ensure the
  57  * AP has enough time to complete one operation before starting the next
  58  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  59  */
  60
  61 /*
  62  * Relevant specifications from ARM include:
  63  *
  64  * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
  65  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  66  *
  67  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
  68  * Cortex-M3(tm) TRM, ARM DDI 0337G
  69  */
  70
  71 #ifdef HAVE_CONFIG_H
  72 #include "config.h"
  73 #endif
  74
  75 #include "jtag/interface.h"
  76 #include "arm.h"
  77 #include "arm_adi_v5.h"
  78 #include <helper/time_support.h>
  79
  80 /* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
  81
  82 /*
  83         uint32_t tar_block_size(uint32_t address)
  84         Return the largest block starting at address that does not cross a tar block size alignment boundary
  85 */
  86 static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
  87 {
  88         return tar_autoincr_block - ((tar_autoincr_block - 1) & address);
  89 }
  90
  91 /***************************************************************************
  92  *                                                                         *
  93  * DP and MEM-AP  register access  through APACC and DPACC                 *
  94  *                                                                         *
  95 ***************************************************************************/
  96
  97 /**
  98  * Select one of the APs connected to the specified DAP.  The
  99  * selection is implicitly used with future AP transactions.
 100  * This is a NOP if the specified AP is already selected.
 101  *
 102  * @param dap The DAP
 103  * @param apsel Number of the AP to (implicitly) use with further
 104  *      transactions.  This normally identifies a MEM-AP.
 105  */
 106 void dap_ap_select(struct adiv5_dap *dap, uint8_t ap)
 107 {
 108         uint32_t new_ap = (ap << 24) & 0xFF000000;
 109
 110         if (new_ap != dap->ap_current) {
 111                 dap->ap_current = new_ap;
 112                 /* Switching AP invalidates cached values.
 113                  * Values MUST BE UPDATED BEFORE AP ACCESS.
 114                  */
 115                 dap->ap_bank_value = -1;
 116                 dap->ap_csw_value = -1;
 117                 dap->ap_tar_value = -1;
 118         }
 119 }
 120
 121 static int dap_setup_accessport_csw(struct adiv5_dap *dap, uint32_t csw)
 122 {
 123         csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT |
 124                 dap->apcsw[dap->ap_current >> 24];
 125
 126         if (csw != dap->ap_csw_value) {
 127                 /* LOG_DEBUG("DAP: Set CSW %x",csw); */
 128                 int retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 129                 if (retval != ERROR_OK)
 130                         return retval;
 131                 dap->ap_csw_value = csw;
 132         }
 133         return ERROR_OK;
 134 }
 135
 136 static int dap_setup_accessport_tar(struct adiv5_dap *dap, uint32_t tar)
 137 {
 138         if (tar != dap->ap_tar_value || dap->ap_csw_value & CSW_ADDRINC_MASK) {
 139                 /* LOG_DEBUG("DAP: Set TAR %x",tar); */
 140                 int retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 141                 if (retval != ERROR_OK)
 142                         return retval;
 143                 dap->ap_tar_value = tar;
 144         }
 145         return ERROR_OK;
 146 }
 147
 148 /**
 149  * Queue transactions setting up transfer parameters for the
 150  * currently selected MEM-AP.
 151  *
 152  * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
 153  * initiate data reads or writes using memory or peripheral addresses.
 154  * If the CSW is configured for it, the TAR may be automatically
 155  * incremented after each transfer.
 156  *
 157  * @todo Rename to reflect it being specifically a MEM-AP function.
 158  *
 159  * @param dap The DAP connected to the MEM-AP.
 160  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
 161  *      matches the cached value, the register is not changed.
 162  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
 163  *      matches the cached address, the register is not changed.
 164  *
 165  * @return ERROR_OK if the transaction was properly queued, else a fault code.
 166  */
 167 int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 168 {
 169         int retval;
 170         retval = dap_setup_accessport_csw(dap, csw);
 171         if (retval != ERROR_OK)
 172                 return retval;
 173         retval = dap_setup_accessport_tar(dap, tar);
 174         if (retval != ERROR_OK)
 175                 return retval;
 176         return ERROR_OK;
 177 }
 178
 179 /**
 180  * Asynchronous (queued) read of a word from memory or a system register.
 181  *
 182  * @param dap The DAP connected to the MEM-AP performing the read.
 183  * @param address Address of the 32-bit word to read; it must be
 184  *      readable by the currently selected MEM-AP.
 185  * @param value points to where the word will be stored when the
 186  *      transaction queue is flushed (assuming no errors).
 187  *
 188  * @return ERROR_OK for success.  Otherwise a fault code.
 189  */
 190 int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 191                 uint32_t *value)
 192 {
 193         int retval;
 194
 195         /* Use banked addressing (REG_BDx) to avoid some link traffic
 196          * (updating TAR) when reading several consecutive addresses.
 197          */
 198         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 199                         address & 0xFFFFFFF0);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 204 }
 205
 206 /**
 207  * Synchronous read of a word from memory or a system register.
 208  * As a side effect, this flushes any queued transactions.
 209  *
 210  * @param dap The DAP connected to the MEM-AP performing the read.
 211  * @param address Address of the 32-bit word to read; it must be
 212  *      readable by the currently selected MEM-AP.
 213  * @param value points to where the result will be stored.
 214  *
 215  * @return ERROR_OK for success; *value holds the result.
 216  * Otherwise a fault code.
 217  */
 218 int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 219                 uint32_t *value)
 220 {
 221         int retval;
 222
 223         retval = mem_ap_read_u32(dap, address, value);
 224         if (retval != ERROR_OK)
 225                 return retval;
 226
 227         return dap_run(dap);
 228 }
 229
 230 /**
 231  * Asynchronous (queued) write of a word to memory or a system register.
 232  *
 233  * @param dap The DAP connected to the MEM-AP.
 234  * @param address Address to be written; it must be writable by
 235  *      the currently selected MEM-AP.
 236  * @param value Word that will be written to the address when transaction
 237  *      queue is flushed (assuming no errors).
 238  *
 239  * @return ERROR_OK for success.  Otherwise a fault code.
 240  */
 241 int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 242                 uint32_t value)
 243 {
 244         int retval;
 245
 246         /* Use banked addressing (REG_BDx) to avoid some link traffic
 247          * (updating TAR) when writing several consecutive addresses.
 248          */
 249         retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 250                         address & 0xFFFFFFF0);
 251         if (retval != ERROR_OK)
 252                 return retval;
 253
 254         return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 255                         value);
 256 }
 257
 258 /**
 259  * Synchronous write of a word to memory or a system register.
 260  * As a side effect, this flushes any queued transactions.
 261  *
 262  * @param dap The DAP connected to the MEM-AP.
 263  * @param address Address to be written; it must be writable by
 264  *      the currently selected MEM-AP.
 265  * @param value Word that will be written.
 266  *
 267  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
 268  */
 269 int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 270                 uint32_t value)
 271 {
 272         int retval = mem_ap_write_u32(dap, address, value);
 273
 274         if (retval != ERROR_OK)
 275                 return retval;
 276
 277         return dap_run(dap);
 278 }
 279
 280 /**
 281  * Synchronous write of a block of memory, using a specific access size.
 282  *
 283  * @param dap The DAP connected to the MEM-AP.
 284  * @param buffer The data buffer to write. No particular alignment is assumed.
 285  * @param size Which access size to use, in bytes. 1, 2 or 4.
 286  * @param count The number of writes to do (in size units, not bytes).
 287  * @param address Address to be written; it must be writable by the currently selected MEM-AP.
 288  * @param addrinc Whether the target address should be increased for each write or not. This
 289  *  should normally be true, except when writing to e.g. a FIFO.
 290  * @return ERROR_OK on success, otherwise an error code.
 291  */
 292 int mem_ap_write(struct adiv5_dap *dap, const uint8_t *buffer, uint32_t size, uint32_t count,
 293                 uint32_t address, bool addrinc)
 294 {
 295         size_t nbytes = size * count;
 296         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 297         uint32_t csw_size;
 298         uint32_t addr_xor;
 299         int retval;
 300
 301         /* TI BE-32 Quirks mode:
 302          * Writes on big-endian TMS570 behave very strangely. Observed behavior:
 303          *   size   write address   bytes written in order
 304          *   4      TAR ^ 0         (val >> 24), (val >> 16), (val >> 8), (val)
 305          *   2      TAR ^ 2         (val >> 8), (val)
 306          *   1      TAR ^ 3         (val)
 307          * For example, if you attempt to write a single byte to address 0, the processor
 308          * will actually write a byte to address 3.
 309          *
 310          * To make writes of size < 4 work as expected, we xor a value with the address before
 311          * setting the TAP, and we set the TAP after every transfer rather then relying on
 312          * address increment. */
 313
 314         if (size == 4) {
 315                 csw_size = CSW_32BIT;
 316                 addr_xor = 0;
 317         } else if (size == 2) {
 318                 csw_size = CSW_16BIT;
 319                 addr_xor = dap->ti_be_32_quirks ? 2 : 0;
 320         } else if (size == 1) {
 321                 csw_size = CSW_8BIT;
 322                 addr_xor = dap->ti_be_32_quirks ? 3 : 0;
 323         } else {
 324                 return ERROR_TARGET_UNALIGNED_ACCESS;
 325         }
 326
 327         if (dap->unaligned_access_bad && (address % size != 0))
 328                 return ERROR_TARGET_UNALIGNED_ACCESS;
 329
 330         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 331         if (retval != ERROR_OK)
 332                 return retval;
 333
 334         while (nbytes > 0) {
 335                 uint32_t this_size = size;
 336
 337                 /* Select packed transfer if possible */
 338                 if (addrinc && dap->packed_transfers && nbytes >= 4
 339                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 340                         this_size = 4;
 341                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 342                 } else {
 343                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 344                 }
 345
 346                 if (retval != ERROR_OK)
 347                         break;
 348
 349                 /* How many source bytes each transfer will consume, and their location in the DRW,
 350                  * depends on the type of transfer and alignment. See ARM document IHI0031C. */
 351                 uint32_t outvalue = 0;
 352                 if (dap->ti_be_32_quirks) {
 353                         switch (this_size) {
 354                         case 4:
 355                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 356                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 357                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 358                                 outvalue |= (uint32_t)*buffer++ << 8 * (3 ^ (address++ & 3) ^ addr_xor);
 359                                 break;
 360                         case 2:
 361                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 362                                 outvalue |= (uint32_t)*buffer++ << 8 * (1 ^ (address++ & 3) ^ addr_xor);
 363                                 break;
 364                         case 1:
 365                                 outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (address++ & 3) ^ addr_xor);
 366                                 break;
 367                         }
 368                 } else {
 369                         switch (this_size) {
 370                         case 4:
 371                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 372                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 373                         case 2:
 374                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 375                         case 1:
 376                                 outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
 377                         }
 378                 }
 379
 380                 nbytes -= this_size;
 381
 382                 retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 383                 if (retval != ERROR_OK)
 384                         break;
 385
 386                 /* Rewrite TAR if it wrapped or we're xoring addresses */
 387                 if (addrinc && (addr_xor || (address % dap->tar_autoincr_block < size && nbytes > 0))) {
 388                         retval = dap_setup_accessport_tar(dap, address ^ addr_xor);
 389                         if (retval != ERROR_OK)
 390                                 break;
 391                 }
 392         }
 393
 394         /* REVISIT: Might want to have a queued version of this function that does not run. */
 395         if (retval == ERROR_OK)
 396                 retval = dap_run(dap);
 397
 398         if (retval != ERROR_OK) {
 399                 uint32_t tar;
 400                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 401                                 && dap_run(dap) == ERROR_OK)
 402                         LOG_ERROR("Failed to write memory at 0x%08"PRIx32, tar);
 403                 else
 404                         LOG_ERROR("Failed to write memory and, additionally, failed to find out where");
 405         }
 406
 407         return retval;
 408 }
 409
 410 /**
 411  * Synchronous read of a block of memory, using a specific access size.
 412  *
 413  * @param dap The DAP connected to the MEM-AP.
 414  * @param buffer The data buffer to receive the data. No particular alignment is assumed.
 415  * @param size Which access size to use, in bytes. 1, 2 or 4.
 416  * @param count The number of reads to do (in size units, not bytes).
 417  * @param address Address to be read; it must be readable by the currently selected MEM-AP.
 418  * @param addrinc Whether the target address should be increased after each read or not. This
 419  *  should normally be true, except when reading from e.g. a FIFO.
 420  * @return ERROR_OK on success, otherwise an error code.
 421  */
 422 int mem_ap_read(struct adiv5_dap *dap, uint8_t *buffer, uint32_t size, uint32_t count,
 423                 uint32_t adr, bool addrinc)
 424 {
 425         size_t nbytes = size * count;
 426         const uint32_t csw_addrincr = addrinc ? CSW_ADDRINC_SINGLE : CSW_ADDRINC_OFF;
 427         uint32_t csw_size;
 428         uint32_t address = adr;
 429         int retval;
 430
 431         /* TI BE-32 Quirks mode:
 432          * Reads on big-endian TMS570 behave strangely differently than writes.
 433          * They read from the physical address requested, but with DRW byte-reversed.
 434          * For example, a byte read from address 0 will place the result in the high bytes of DRW.
 435          * Also, packed 8-bit and 16-bit transfers seem to sometimes return garbage in some bytes,
 436          * so avoid them. */
 437
 438         if (size == 4)
 439                 csw_size = CSW_32BIT;
 440         else if (size == 2)
 441                 csw_size = CSW_16BIT;
 442         else if (size == 1)
 443                 csw_size = CSW_8BIT;
 444         else
 445                 return ERROR_TARGET_UNALIGNED_ACCESS;
 446
 447         if (dap->unaligned_access_bad && (adr % size != 0))
 448                 return ERROR_TARGET_UNALIGNED_ACCESS;
 449
 450         /* Allocate buffer to hold the sequence of DRW reads that will be made. This is a significant
 451          * over-allocation if packed transfers are going to be used, but determining the real need at
 452          * this point would be messy. */
 453         uint32_t *read_buf = malloc(count * sizeof(uint32_t));
 454         uint32_t *read_ptr = read_buf;
 455         if (read_buf == NULL) {
 456                 LOG_ERROR("Failed to allocate read buffer");
 457                 return ERROR_FAIL;
 458         }
 459
 460         retval = dap_setup_accessport_tar(dap, address);
 461         if (retval != ERROR_OK) {
 462                 free(read_buf);
 463                 return retval;
 464         }
 465
 466         /* Queue up all reads. Each read will store the entire DRW word in the read buffer. How many
 467          * useful bytes it contains, and their location in the word, depends on the type of transfer
 468          * and alignment. */
 469         while (nbytes > 0) {
 470                 uint32_t this_size = size;
 471
 472                 /* Select packed transfer if possible */
 473                 if (addrinc && dap->packed_transfers && nbytes >= 4
 474                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 475                         this_size = 4;
 476                         retval = dap_setup_accessport_csw(dap, csw_size | CSW_ADDRINC_PACKED);
 477                 } else {
 478                         retval = dap_setup_accessport_csw(dap, csw_size | csw_addrincr);
 479                 }
 480                 if (retval != ERROR_OK)
 481                         break;
 482
 483                 retval = dap_queue_ap_read(dap, AP_REG_DRW, read_ptr++);
 484                 if (retval != ERROR_OK)
 485                         break;
 486
 487                 nbytes -= this_size;
 488                 address += this_size;
 489
 490                 /* Rewrite TAR if it wrapped */
 491                 if (addrinc && address % dap->tar_autoincr_block < size && nbytes > 0) {
 492                         retval = dap_setup_accessport_tar(dap, address);
 493                         if (retval != ERROR_OK)
 494                                 break;
 495                 }
 496         }
 497
 498         if (retval == ERROR_OK)
 499                 retval = dap_run(dap);
 500
 501         /* Restore state */
 502         address = adr;
 503         nbytes = size * count;
 504         read_ptr = read_buf;
 505
 506         /* If something failed, read TAR to find out how much data was successfully read, so we can
 507          * at least give the caller what we have. */
 508         if (retval != ERROR_OK) {
 509                 uint32_t tar;
 510                 if (dap_queue_ap_read(dap, AP_REG_TAR, &tar) == ERROR_OK
 511                                 && dap_run(dap) == ERROR_OK) {
 512                         LOG_ERROR("Failed to read memory at 0x%08"PRIx32, tar);
 513                         if (nbytes > tar - address)
 514                                 nbytes = tar - address;
 515                 } else {
 516                         LOG_ERROR("Failed to read memory and, additionally, failed to find out where");
 517                         nbytes = 0;
 518                 }
 519         }
 520
 521         /* Replay loop to populate caller's buffer from the correct word and byte lane */
 522         while (nbytes > 0) {
 523                 uint32_t this_size = size;
 524
 525                 if (addrinc && dap->packed_transfers && nbytes >= 4
 526                                 && max_tar_block_size(dap->tar_autoincr_block, address) >= 4) {
 527                         this_size = 4;
 528                 }
 529
 530                 if (dap->ti_be_32_quirks) {
 531                         switch (this_size) {
 532                         case 4:
 533                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 534                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 535                         case 2:
 536                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 537                         case 1:
 538                                 *buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
 539                         }
 540                 } else {
 541                         switch (this_size) {
 542                         case 4:
 543                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 544                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 545                         case 2:
 546                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 547                         case 1:
 548                                 *buffer++ = *read_ptr >> 8 * (address++ & 3);
 549                         }
 550                 }
 551
 552                 read_ptr++;
 553                 nbytes -= this_size;
 554         }
 555
 556         free(read_buf);
 557         return retval;
 558 }
 559
 560 /*--------------------------------------------------------------------*/
 561 /*          Wrapping function with selection of AP                    */
 562 /*--------------------------------------------------------------------*/
 563 int mem_ap_sel_read_u32(struct adiv5_dap *swjdp, uint8_t ap,
 564                 uint32_t address, uint32_t *value)
 565 {
 566         dap_ap_select(swjdp, ap);
 567         return mem_ap_read_u32(swjdp, address, value);
 568 }
 569
 570 int mem_ap_sel_write_u32(struct adiv5_dap *swjdp, uint8_t ap,
 571                 uint32_t address, uint32_t value)
 572 {
 573         dap_ap_select(swjdp, ap);
 574         return mem_ap_write_u32(swjdp, address, value);
 575 }
 576
 577 int mem_ap_sel_read_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 578                 uint32_t address, uint32_t *value)
 579 {
 580         dap_ap_select(swjdp, ap);
 581         return mem_ap_read_atomic_u32(swjdp, address, value);
 582 }
 583
 584 int mem_ap_sel_write_atomic_u32(struct adiv5_dap *swjdp, uint8_t ap,
 585                 uint32_t address, uint32_t value)
 586 {
 587         dap_ap_select(swjdp, ap);
 588         return mem_ap_write_atomic_u32(swjdp, address, value);
 589 }
 590
 591 int mem_ap_sel_read_buf(struct adiv5_dap *swjdp, uint8_t ap,
 592                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 593 {
 594         dap_ap_select(swjdp, ap);
 595         return mem_ap_read(swjdp, buffer, size, count, address, true);
 596 }
 597
 598 int mem_ap_sel_write_buf(struct adiv5_dap *swjdp, uint8_t ap,
 599                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 600 {
 601         dap_ap_select(swjdp, ap);
 602         return mem_ap_write(swjdp, buffer, size, count, address, true);
 603 }
 604
 605 int mem_ap_sel_read_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 606                 uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 607 {
 608         dap_ap_select(swjdp, ap);
 609         return mem_ap_read(swjdp, buffer, size, count, address, false);
 610 }
 611
 612 int mem_ap_sel_write_buf_noincr(struct adiv5_dap *swjdp, uint8_t ap,
 613                 const uint8_t *buffer, uint32_t size, uint32_t count, uint32_t address)
 614 {
 615         dap_ap_select(swjdp, ap);
 616         return mem_ap_write(swjdp, buffer, size, count, address, false);
 617 }
 618
 619 /*--------------------------------------------------------------------------*/
 620
 621
 622 /* FIXME don't import ... just initialize as
 623  * part of DAP transport setup
 624 */
 625 extern const struct dap_ops jtag_dp_ops;
 626
 627 /*--------------------------------------------------------------------------*/
 628
 629 /**
 630  * Initialize a DAP.  This sets up the power domains, prepares the DP
 631  * for further use, and arranges to use AP #0 for all AP operations
 632  * until dap_ap-select() changes that policy.
 633  *
 634  * @param dap The DAP being initialized.
 635  *
 636  * @todo Rename this.  We also need an initialization scheme which account
 637  * for SWD transports not just JTAG; that will need to address differences
 638  * in layering.  (JTAG is useful without any debug target; but not SWD.)
 639  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
 640  */
 641 int ahbap_debugport_init(struct adiv5_dap *dap)
 642 {
 643         uint32_t ctrlstat;
 644         int cnt = 0;
 645         int retval;
 646
 647         LOG_DEBUG(" ");
 648
 649         /* JTAG-DP or SWJ-DP, in JTAG mode
 650          * ... for SWD mode this is patched as part
 651          * of link switchover
 652          */
 653         if (!dap->ops)
 654                 dap->ops = &jtag_dp_ops;
 655
 656         /* Default MEM-AP setup.
 657          *
 658          * REVISIT AP #0 may be an inappropriate default for this.
 659          * Should we probe, or take a hint from the caller?
 660          * Presumably we can ignore the possibility of multiple APs.
 661          */
 662         dap->ap_current = !0;
 663         dap_ap_select(dap, 0);
 664
 665         /* DP initialization */
 666
 667         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 668         if (retval != ERROR_OK)
 669                 return retval;
 670
 671         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 672         if (retval != ERROR_OK)
 673                 return retval;
 674
 675         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 676         if (retval != ERROR_OK)
 677                 return retval;
 678
 679         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
 680         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 681         if (retval != ERROR_OK)
 682                 return retval;
 683
 684         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 685         if (retval != ERROR_OK)
 686                 return retval;
 687         retval = dap_run(dap);
 688         if (retval != ERROR_OK)
 689                 return retval;
 690
 691         /* Check that we have debug power domains activated */
 692         while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10)) {
 693                 LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 694                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 695                 if (retval != ERROR_OK)
 696                         return retval;
 697                 retval = dap_run(dap);
 698                 if (retval != ERROR_OK)
 699                         return retval;
 700                 alive_sleep(10);
 701         }
 702
 703         while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10)) {
 704                 LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 705                 retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 706                 if (retval != ERROR_OK)
 707                         return retval;
 708                 retval = dap_run(dap);
 709                 if (retval != ERROR_OK)
 710                         return retval;
 711                 alive_sleep(10);
 712         }
 713
 714         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 715         if (retval != ERROR_OK)
 716                 return retval;
 717         /* With debug power on we can activate OVERRUN checking */
 718         dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
 719         retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 720         if (retval != ERROR_OK)
 721                 return retval;
 722         retval = dap_queue_dp_read(dap, DP_CTRL_STAT, NULL);
 723         if (retval != ERROR_OK)
 724                 return retval;
 725
 726         /* check that we support packed transfers */
 727         uint32_t csw, cfg;
 728
 729         retval = dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, 0);
 730         if (retval != ERROR_OK)
 731                 return retval;
 732
 733         retval = dap_queue_ap_read(dap, AP_REG_CSW, &csw);
 734         if (retval != ERROR_OK)
 735                 return retval;
 736
 737         retval = dap_queue_ap_read(dap, AP_REG_CFG, &cfg);
 738         if (retval != ERROR_OK)
 739                 return retval;
 740
 741         retval = dap_run(dap);
 742         if (retval != ERROR_OK)
 743                 return retval;
 744
 745         if (csw & CSW_ADDRINC_PACKED)
 746                 dap->packed_transfers = true;
 747         else
 748                 dap->packed_transfers = false;
 749
 750         /* Packed transfers on TI BE-32 processors do not work correctly in
 751          * many cases. */
 752         if (dap->ti_be_32_quirks)
 753                 dap->packed_transfers = false;
 754
 755         LOG_DEBUG("MEM_AP Packed Transfers: %s",
 756                         dap->packed_transfers ? "enabled" : "disabled");
 757
 758         /* The ARM ADI spec leaves implementation-defined whether unaligned
 759          * memory accesses work, only work partially, or cause a sticky error.
 760          * On TI BE-32 processors, reads seem to return garbage in some bytes
 761          * and unaligned writes seem to cause a sticky error.
 762          * TODO: it would be nice to have a way to detect whether unaligned
 763          * operations are supported on other processors. */
 764         dap->unaligned_access_bad = dap->ti_be_32_quirks;
 765
 766         LOG_DEBUG("MEM_AP CFG: large data %d, long address %d, big-endian %d",
 767                         !!(cfg & 0x04), !!(cfg & 0x02), !!(cfg & 0x01));
 768
 769         return ERROR_OK;
 770 }
 771
 772 /* CID interpretation -- see ARM IHI 0029B section 3
 773  * and ARM IHI 0031A table 13-3.
 774  */
 775 static const char *class_description[16] = {
 776         "Reserved", "ROM table", "Reserved", "Reserved",
 777         "Reserved", "Reserved", "Reserved", "Reserved",
 778         "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
 779         "Reserved", "OptimoDE DESS",
 780         "Generic IP component", "PrimeCell or System component"
 781 };
 782
 783 static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 784 {
 785         return cid3 == 0xb1 && cid2 == 0x05
 786                         && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 787 }
 788
 789 /*
 790  * This function checks the ID for each access port to find the requested Access Port type
 791  */
 792 int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, uint8_t *ap_num_out)
 793 {
 794         int ap;
 795
 796         /* Maximum AP number is 255 since the SELECT register is 8 bits */
 797         for (ap = 0; ap <= 255; ap++) {
 798
 799                 /* read the IDR register of the Access Port */
 800                 uint32_t id_val = 0;
 801                 dap_ap_select(dap, ap);
 802
 803                 int retval = dap_queue_ap_read(dap, AP_REG_IDR, &id_val);
 804                 if (retval != ERROR_OK)
 805                         return retval;
 806
 807                 retval = dap_run(dap);
 808
 809                 /* IDR bits:
 810                  * 31-28 : Revision
 811                  * 27-24 : JEDEC bank (0x4 for ARM)
 812                  * 23-17 : JEDEC code (0x3B for ARM)
 813                  * 16    : Mem-AP
 814                  * 15-8  : Reserved
 815                  *  7-0  : AP Identity (1=AHB-AP 2=APB-AP 0x10=JTAG-AP)
 816                  */
 817
 818                 /* Reading register for a non-existant AP should not cause an error,
 819                  * but just to be sure, try to continue searching if an error does happen.
 820                  */
 821                 if ((retval == ERROR_OK) &&                  /* Register read success */
 822                         ((id_val & 0x0FFF0000) == 0x04770000) && /* Jedec codes match */
 823                         ((id_val & 0xFF) == type_to_find)) {     /* type matches*/
 824
 825                         LOG_DEBUG("Found %s at AP index: %d (IDR=0x%08" PRIX32 ")",
 826                                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 827                                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 828                                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown",
 829                                                 ap, id_val);
 830
 831                         *ap_num_out = ap;
 832                         return ERROR_OK;
 833                 }
 834         }
 835
 836         LOG_DEBUG("No %s found",
 837                                 (type_to_find == AP_TYPE_AHB_AP)  ? "AHB-AP"  :
 838                                 (type_to_find == AP_TYPE_APB_AP)  ? "APB-AP"  :
 839                                 (type_to_find == AP_TYPE_JTAG_AP) ? "JTAG-AP" : "Unknown");
 840         return ERROR_FAIL;
 841 }
 842
 843 int dap_get_debugbase(struct adiv5_dap *dap, int ap,
 844                         uint32_t *out_dbgbase, uint32_t *out_apid)
 845 {
 846         uint32_t ap_old;
 847         int retval;
 848         uint32_t dbgbase, apid;
 849
 850         /* AP address is in bits 31:24 of DP_SELECT */
 851         if (ap >= 256)
 852                 return ERROR_COMMAND_SYNTAX_ERROR;
 853
 854         ap_old = dap->ap_current;
 855         dap_ap_select(dap, ap);
 856
 857         retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
 858         if (retval != ERROR_OK)
 859                 return retval;
 860         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
 861         if (retval != ERROR_OK)
 862                 return retval;
 863         retval = dap_run(dap);
 864         if (retval != ERROR_OK)
 865                 return retval;
 866
 867         /* Excavate the device ID code */
 868         struct jtag_tap *tap = dap->jtag_info->tap;
 869         while (tap != NULL) {
 870                 if (tap->hasidcode)
 871                         break;
 872                 tap = tap->next_tap;
 873         }
 874         if (tap == NULL || !tap->hasidcode)
 875                 return ERROR_OK;
 876
 877         dap_ap_select(dap, ap_old);
 878
 879         /* The asignment happens only here to prevent modification of these
 880          * values before they are certain. */
 881         *out_dbgbase = dbgbase;
 882         *out_apid = apid;
 883
 884         return ERROR_OK;
 885 }
 886
 887 int dap_lookup_cs_component(struct adiv5_dap *dap, int ap,
 888                         uint32_t dbgbase, uint8_t type, uint32_t *addr)
 889 {
 890         uint32_t ap_old;
 891         uint32_t romentry, entry_offset = 0, component_base, devtype;
 892         int retval = ERROR_FAIL;
 893
 894         if (ap >= 256)
 895                 return ERROR_COMMAND_SYNTAX_ERROR;
 896
 897         ap_old = dap->ap_current;
 898         dap_ap_select(dap, ap);
 899
 900         do {
 901                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) |
 902                                                 entry_offset, &romentry);
 903                 if (retval != ERROR_OK)
 904                         return retval;
 905
 906                 component_base = (dbgbase & 0xFFFFF000)
 907                         + (romentry & 0xFFFFF000);
 908
 909                 if (romentry & 0x1) {
 910                         retval = mem_ap_read_atomic_u32(dap,
 911                                         (component_base & 0xfffff000) | 0xfcc,
 912                                         &devtype);
 913                         if (retval != ERROR_OK)
 914                                 return retval;
 915                         if ((devtype & 0xff) == type) {
 916                                 *addr = component_base;
 917                                 retval = ERROR_OK;
 918                                 break;
 919                         }
 920                 }
 921                 entry_offset += 4;
 922         } while (romentry > 0);
 923
 924         dap_ap_select(dap, ap_old);
 925
 926         return retval;
 927 }
 928
 929 static int dap_rom_display(struct command_context *cmd_ctx,
 930                                 struct adiv5_dap *dap, int ap, uint32_t dbgbase, int depth)
 931 {
 932         int retval;
 933         uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
 934         uint16_t entry_offset;
 935         char tabs[7] = "";
 936
 937         if (depth > 16) {
 938                 command_print(cmd_ctx, "\tTables too deep");
 939                 return ERROR_FAIL;
 940         }
 941
 942         if (depth)
 943                 snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
 944
 945         /* bit 16 of apid indicates a memory access port */
 946         if (dbgbase & 0x02)
 947                 command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
 948         else
 949                 command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
 950
 951         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 952         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
 953         if (retval != ERROR_OK)
 954                 return retval;
 955         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
 956         if (retval != ERROR_OK)
 957                 return retval;
 958         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 959         if (retval != ERROR_OK)
 960                 return retval;
 961         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 962         if (retval != ERROR_OK)
 963                 return retval;
 964         retval = mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
 965         if (retval != ERROR_OK)
 966                 return retval;
 967         retval = dap_run(dap);
 968         if (retval != ERROR_OK)
 969                 return retval;
 970
 971         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 972                 command_print(cmd_ctx, "\t%sCID3 0x%02x"
 973                                 ", CID2 0x%02x"
 974                                 ", CID1 0x%02x"
 975                                 ", CID0 0x%02x",
 976                                 tabs,
 977                                 (unsigned)cid3, (unsigned)cid2,
 978                                 (unsigned)cid1, (unsigned)cid0);
 979         if (memtype & 0x01)
 980                 command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
 981         else
 982                 command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
 983
 984         /* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
 985         for (entry_offset = 0; ; entry_offset += 4) {
 986                 retval = mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 987                 if (retval != ERROR_OK)
 988                         return retval;
 989                 command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
 990                                 tabs, entry_offset, romentry);
 991                 if (romentry & 0x01) {
 992                         uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
 993                         uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
 994                         uint32_t component_base;
 995                         unsigned part_num;
 996                         char *type, *full;
 997
 998                         component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
 999
1000                         /* IDs are in last 4K section */
1001                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE0, &c_pid0);
1002                         if (retval != ERROR_OK) {
1003                                 command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
1004                                               ", the corresponding core might be turned off", tabs, component_base);
1005                                 continue;
1006                         }
1007                         c_pid0 &= 0xff;
1008                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE4, &c_pid1);
1009                         if (retval != ERROR_OK)
1010                                 return retval;
1011                         c_pid1 &= 0xff;
1012                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFE8, &c_pid2);
1013                         if (retval != ERROR_OK)
1014                                 return retval;
1015                         c_pid2 &= 0xff;
1016                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFEC, &c_pid3);
1017                         if (retval != ERROR_OK)
1018                                 return retval;
1019                         c_pid3 &= 0xff;
1020                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFD0, &c_pid4);
1021                         if (retval != ERROR_OK)
1022                                 return retval;
1023                         c_pid4 &= 0xff;
1024
1025                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF0, &c_cid0);
1026                         if (retval != ERROR_OK)
1027                                 return retval;
1028                         c_cid0 &= 0xff;
1029                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF4, &c_cid1);
1030                         if (retval != ERROR_OK)
1031                                 return retval;
1032                         c_cid1 &= 0xff;
1033                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFF8, &c_cid2);
1034                         if (retval != ERROR_OK)
1035                                 return retval;
1036                         c_cid2 &= 0xff;
1037                         retval = mem_ap_read_atomic_u32(dap, component_base + 0xFFC, &c_cid3);
1038                         if (retval != ERROR_OK)
1039                                 return retval;
1040                         c_cid3 &= 0xff;
1041
1042                         command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
1043                                       "start address 0x%" PRIx32, component_base,
1044                                       /* component may take multiple 4K pages */
1045                                       (uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
1046                         command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
1047                                         (uint8_t)((c_cid1 >> 4) & 0xf),
1048                                         /* See ARM IHI 0029B Table 3-3 */
1049                                         class_description[(c_cid1 >> 4) & 0xf]);
1050
1051                         /* CoreSight component? */
1052                         if (((c_cid1 >> 4) & 0x0f) == 9) {
1053                                 uint32_t devtype;
1054                                 unsigned minor;
1055                                 char *major = "Reserved", *subtype = "Reserved";
1056
1057                                 retval = mem_ap_read_atomic_u32(dap,
1058                                                 (component_base & 0xfffff000) | 0xfcc,
1059                                                 &devtype);
1060                                 if (retval != ERROR_OK)
1061                                         return retval;
1062                                 minor = (devtype >> 4) & 0x0f;
1063                                 switch (devtype & 0x0f) {
1064                                 case 0:
1065                                         major = "Miscellaneous";
1066                                         switch (minor) {
1067                                         case 0:
1068                                                 subtype = "other";
1069                                                 break;
1070                                         case 4:
1071                                                 subtype = "Validation component";
1072                                                 break;
1073                                         }
1074                                         break;
1075                                 case 1:
1076                                         major = "Trace Sink";
1077                                         switch (minor) {
1078                                         case 0:
1079                                                 subtype = "other";
1080                                                 break;
1081                                         case 1:
1082                                                 subtype = "Port";
1083                                                 break;
1084                                         case 2:
1085                                                 subtype = "Buffer";
1086                                                 break;
1087                                         }
1088                                         break;
1089                                 case 2:
1090                                         major = "Trace Link";
1091                                         switch (minor) {
1092                                         case 0:
1093                                                 subtype = "other";
1094                                                 break;
1095                                         case 1:
1096                                                 subtype = "Funnel, router";
1097                                                 break;
1098                                         case 2:
1099                                                 subtype = "Filter";
1100                                                 break;
1101                                         case 3:
1102                                                 subtype = "FIFO, buffer";
1103                                                 break;
1104                                         }
1105                                         break;
1106                                 case 3:
1107                                         major = "Trace Source";
1108                                         switch (minor) {
1109                                         case 0:
1110                                                 subtype = "other";
1111                                                 break;
1112                                         case 1:
1113                                                 subtype = "Processor";
1114                                                 break;
1115                                         case 2:
1116                                                 subtype = "DSP";
1117                                                 break;
1118                                         case 3:
1119                                                 subtype = "Engine/Coprocessor";
1120                                                 break;
1121                                         case 4:
1122                                                 subtype = "Bus";
1123                                                 break;
1124                                         }
1125                                         break;
1126                                 case 4:
1127                                         major = "Debug Control";
1128                                         switch (minor) {
1129                                         case 0:
1130                                                 subtype = "other";
1131                                                 break;
1132                                         case 1:
1133                                                 subtype = "Trigger Matrix";
1134                                                 break;
1135                                         case 2:
1136                                                 subtype = "Debug Auth";
1137                                                 break;
1138                                         }
1139                                         break;
1140                                 case 5:
1141                                         major = "Debug Logic";
1142                                         switch (minor) {
1143                                         case 0:
1144                                                 subtype = "other";
1145                                                 break;
1146                                         case 1:
1147                                                 subtype = "Processor";
1148                                                 break;
1149                                         case 2:
1150                                                 subtype = "DSP";
1151                                                 break;
1152                                         case 3:
1153                                                 subtype = "Engine/Coprocessor";
1154                                                 break;
1155                                         }
1156                                         break;
1157                                 }
1158                                 command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
1159                                                 (uint8_t)(devtype & 0xff),
1160                                                 major, subtype);
1161                                 /* REVISIT also show 0xfc8 DevId */
1162                         }
1163
1164                         if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
1165                                 command_print(cmd_ctx,
1166                                                 "\t\tCID3 0%02x"
1167                                                 ", CID2 0%02x"
1168                                                 ", CID1 0%02x"
1169                                                 ", CID0 0%02x",
1170                                                 (int)c_cid3,
1171                                                 (int)c_cid2,
1172                                                 (int)c_cid1,
1173                                                 (int)c_cid0);
1174                         command_print(cmd_ctx,
1175                                 "\t\tPeripheral ID[4..0] = hex "
1176                                 "%02x %02x %02x %02x %02x",
1177                                 (int)c_pid4, (int)c_pid3, (int)c_pid2,
1178                                 (int)c_pid1, (int)c_pid0);
1179
1180                         /* Part number interpretations are from Cortex
1181                          * core specs, the CoreSight components TRM
1182                          * (ARM DDI 0314H), CoreSight System Design
1183                          * Guide (ARM DGI 0012D) and ETM specs; also
1184                          * from chip observation (e.g. TI SDTI).
1185                          */
1186                         part_num = (c_pid0 & 0xff);
1187                         part_num |= (c_pid1 & 0x0f) << 8;
1188                         switch (part_num) {
1189                         case 0x000:
1190                                 type = "Cortex-M3 NVIC";
1191                                 full = "(Interrupt Controller)";
1192                                 break;
1193                         case 0x001:
1194                                 type = "Cortex-M3 ITM";
1195                                 full = "(Instrumentation Trace Module)";
1196                                 break;
1197                         case 0x002:
1198                                 type = "Cortex-M3 DWT";
1199                                 full = "(Data Watchpoint and Trace)";
1200                                 break;
1201                         case 0x003:
1202                                 type = "Cortex-M3 FBP";
1203                                 full = "(Flash Patch and Breakpoint)";
1204                                 break;
1205                         case 0x00c:
1206                                 type = "Cortex-M4 SCS";
1207                                 full = "(System Control Space)";
1208                                 break;
1209                         case 0x00d:
1210                                 type = "CoreSight ETM11";
1211                                 full = "(Embedded Trace)";
1212                                 break;
1213                         /* case 0x113: what? */
1214                         case 0x120:             /* from OMAP3 memmap */
1215                                 type = "TI SDTI";
1216                                 full = "(System Debug Trace Interface)";
1217                                 break;
1218                         case 0x343:             /* from OMAP3 memmap */
1219                                 type = "TI DAPCTL";
1220                                 full = "";
1221                                 break;
1222                         case 0x906:
1223                                 type = "Coresight CTI";
1224                                 full = "(Cross Trigger)";
1225                                 break;
1226                         case 0x907:
1227                                 type = "Coresight ETB";
1228                                 full = "(Trace Buffer)";
1229                                 break;
1230                         case 0x908:
1231                                 type = "Coresight CSTF";
1232                                 full = "(Trace Funnel)";
1233                                 break;
1234                         case 0x910:
1235                                 type = "CoreSight ETM9";
1236                                 full = "(Embedded Trace)";
1237                                 break;
1238                         case 0x912:
1239                                 type = "Coresight TPIU";
1240                                 full = "(Trace Port Interface Unit)";
1241                                 break;
1242                         case 0x913:
1243                                 type = "Coresight ITM";
1244                                 full = "(Instrumentation Trace Macrocell)";
1245                                 break;
1246                         case 0x921:
1247                                 type = "Cortex-A8 ETM";
1248                                 full = "(Embedded Trace)";
1249                                 break;
1250                         case 0x922:
1251                                 type = "Cortex-A8 CTI";
1252                                 full = "(Cross Trigger)";
1253                                 break;
1254                         case 0x923:
1255                                 type = "Cortex-M3 TPIU";
1256                                 full = "(Trace Port Interface Unit)";
1257                                 break;
1258                         case 0x924:
1259                                 type = "Cortex-M3 ETM";
1260                                 full = "(Embedded Trace)";
1261                                 break;
1262                         case 0x925:
1263                                 type = "Cortex-M4 ETM";
1264                                 full = "(Embedded Trace)";
1265                                 break;
1266                         case 0x930:
1267                                 type = "Cortex-R4 ETM";
1268                                 full = "(Embedded Trace)";
1269                                 break;
1270                         case 0x950:
1271                                 type = "CoreSight Component";
1272                                 full = "(unidentified Cortex-A9 component)";
1273                                 break;
1274                         case 0x9a0:
1275                                 type = "CoreSight PMU";
1276                                 full = "(Performance Monitoring Unit)";
1277                                 break;
1278                         case 0x9a1:
1279                                 type = "Cortex-M4 TPUI";
1280                                 full = "(Trace Port Interface Unit)";
1281                                 break;
1282                         case 0xc08:
1283                                 type = "Cortex-A8 Debug";
1284                                 full = "(Debug Unit)";
1285                                 break;
1286                         case 0xc09:
1287                                 type = "Cortex-A9 Debug";
1288                                 full = "(Debug Unit)";
1289                                 break;
1290                         default:
1291                                 type = "-*- unrecognized -*-";
1292                                 full = "";
1293                                 break;
1294                         }
1295                         command_print(cmd_ctx, "\t\tPart is %s %s",
1296                                         type, full);
1297
1298                         /* ROM Table? */
1299                         if (((c_cid1 >> 4) & 0x0f) == 1) {
1300                                 retval = dap_rom_display(cmd_ctx, dap, ap, component_base, depth + 1);
1301                                 if (retval != ERROR_OK)
1302                                         return retval;
1303                         }
1304                 } else {
1305                         if (romentry)
1306                                 command_print(cmd_ctx, "\t\tComponent not present");
1307                         else
1308                                 break;
1309                 }
1310         }
1311         command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
1312         return ERROR_OK;
1313 }
1314
1315 static int dap_info_command(struct command_context *cmd_ctx,
1316                 struct adiv5_dap *dap, int ap)
1317 {
1318         int retval;
1319         uint32_t dbgbase = 0, apid = 0; /* Silence gcc by initializing */
1320         int romtable_present = 0;
1321         uint8_t mem_ap;
1322         uint32_t ap_old;
1323
1324         retval = dap_get_debugbase(dap, ap, &dbgbase, &apid);
1325         if (retval != ERROR_OK)
1326                 return retval;
1327
1328         ap_old = dap->ap_current;
1329         dap_ap_select(dap, ap);
1330
1331         /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
1332         mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
1333         command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
1334         if (apid) {
1335                 switch (apid&0x0F) {
1336                         case 0:
1337                                 command_print(cmd_ctx, "\tType is JTAG-AP");
1338                                 break;
1339                         case 1:
1340                                 command_print(cmd_ctx, "\tType is MEM-AP AHB");
1341                                 break;
1342                         case 2:
1343                                 command_print(cmd_ctx, "\tType is MEM-AP APB");
1344                                 break;
1345                         default:
1346                                 command_print(cmd_ctx, "\tUnknown AP type");
1347                                 break;
1348                 }
1349
1350                 /* NOTE: a MEM-AP may have a single CoreSight component that's
1351                  * not a ROM table ... or have no such components at all.
1352                  */
1353                 if (mem_ap)
1354                         command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32, dbgbase);
1355         } else
1356                 command_print(cmd_ctx, "No AP found at this ap 0x%x", ap);
1357
1358         romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
1359         if (romtable_present) {
1360                 dap_rom_display(cmd_ctx, dap, ap, dbgbase, 0);
1361         } else
1362                 command_print(cmd_ctx, "\tNo ROM table present");
1363         dap_ap_select(dap, ap_old);
1364
1365         return ERROR_OK;
1366 }
1367
1368 COMMAND_HANDLER(handle_dap_info_command)
1369 {
1370         struct target *target = get_current_target(CMD_CTX);
1371         struct arm *arm = target_to_arm(target);
1372         struct adiv5_dap *dap = arm->dap;
1373         uint32_t apsel;
1374
1375         switch (CMD_ARGC) {
1376         case 0:
1377                 apsel = dap->apsel;
1378                 break;
1379         case 1:
1380                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1381                 break;
1382         default:
1383                 return ERROR_COMMAND_SYNTAX_ERROR;
1384         }
1385
1386         return dap_info_command(CMD_CTX, dap, apsel);
1387 }
1388
1389 COMMAND_HANDLER(dap_baseaddr_command)
1390 {
1391         struct target *target = get_current_target(CMD_CTX);
1392         struct arm *arm = target_to_arm(target);
1393         struct adiv5_dap *dap = arm->dap;
1394
1395         uint32_t apsel, baseaddr;
1396         int retval;
1397
1398         switch (CMD_ARGC) {
1399         case 0:
1400                 apsel = dap->apsel;
1401                 break;
1402         case 1:
1403                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1404                 /* AP address is in bits 31:24 of DP_SELECT */
1405                 if (apsel >= 256)
1406                         return ERROR_COMMAND_SYNTAX_ERROR;
1407                 break;
1408         default:
1409                 return ERROR_COMMAND_SYNTAX_ERROR;
1410         }
1411
1412         dap_ap_select(dap, apsel);
1413
1414         /* NOTE:  assumes we're talking to a MEM-AP, which
1415          * has a base address.  There are other kinds of AP,
1416          * though they're not common for now.  This should
1417          * use the ID register to verify it's a MEM-AP.
1418          */
1419         retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
1420         if (retval != ERROR_OK)
1421                 return retval;
1422         retval = dap_run(dap);
1423         if (retval != ERROR_OK)
1424                 return retval;
1425
1426         command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
1427
1428         return retval;
1429 }
1430
1431 COMMAND_HANDLER(dap_memaccess_command)
1432 {
1433         struct target *target = get_current_target(CMD_CTX);
1434         struct arm *arm = target_to_arm(target);
1435         struct adiv5_dap *dap = arm->dap;
1436
1437         uint32_t memaccess_tck;
1438
1439         switch (CMD_ARGC) {
1440         case 0:
1441                 memaccess_tck = dap->memaccess_tck;
1442                 break;
1443         case 1:
1444                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
1445                 break;
1446         default:
1447                 return ERROR_COMMAND_SYNTAX_ERROR;
1448         }
1449         dap->memaccess_tck = memaccess_tck;
1450
1451         command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
1452                         dap->memaccess_tck);
1453
1454         return ERROR_OK;
1455 }
1456
1457 COMMAND_HANDLER(dap_apsel_command)
1458 {
1459         struct target *target = get_current_target(CMD_CTX);
1460         struct arm *arm = target_to_arm(target);
1461         struct adiv5_dap *dap = arm->dap;
1462
1463         uint32_t apsel, apid;
1464         int retval;
1465
1466         switch (CMD_ARGC) {
1467         case 0:
1468                 apsel = 0;
1469                 break;
1470         case 1:
1471                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1472                 /* AP address is in bits 31:24 of DP_SELECT */
1473                 if (apsel >= 256)
1474                         return ERROR_COMMAND_SYNTAX_ERROR;
1475                 break;
1476         default:
1477                 return ERROR_COMMAND_SYNTAX_ERROR;
1478         }
1479
1480         dap->apsel = apsel;
1481         dap_ap_select(dap, apsel);
1482
1483         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1484         if (retval != ERROR_OK)
1485                 return retval;
1486         retval = dap_run(dap);
1487         if (retval != ERROR_OK)
1488                 return retval;
1489
1490         command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
1491                         apsel, apid);
1492
1493         return retval;
1494 }
1495
1496 COMMAND_HANDLER(dap_apcsw_command)
1497 {
1498         struct target *target = get_current_target(CMD_CTX);
1499         struct arm *arm = target_to_arm(target);
1500         struct adiv5_dap *dap = arm->dap;
1501
1502         uint32_t apcsw = dap->apcsw[dap->apsel], sprot = 0;
1503
1504         switch (CMD_ARGC) {
1505         case 0:
1506                 command_print(CMD_CTX, "apsel %" PRIi32 " selected, csw 0x%8.8" PRIx32,
1507                         (dap->apsel), apcsw);
1508                 break;
1509         case 1:
1510                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], sprot);
1511                 /* AP address is in bits 31:24 of DP_SELECT */
1512                 if (sprot > 1)
1513                         return ERROR_COMMAND_SYNTAX_ERROR;
1514                 if (sprot)
1515                         apcsw |= CSW_SPROT;
1516                 else
1517                         apcsw &= ~CSW_SPROT;
1518                 break;
1519         default:
1520                 return ERROR_COMMAND_SYNTAX_ERROR;
1521         }
1522         dap->apcsw[dap->apsel] = apcsw;
1523
1524         return 0;
1525 }
1526
1527
1528
1529 COMMAND_HANDLER(dap_apid_command)
1530 {
1531         struct target *target = get_current_target(CMD_CTX);
1532         struct arm *arm = target_to_arm(target);
1533         struct adiv5_dap *dap = arm->dap;
1534
1535         uint32_t apsel, apid;
1536         int retval;
1537
1538         switch (CMD_ARGC) {
1539         case 0:
1540                 apsel = dap->apsel;
1541                 break;
1542         case 1:
1543                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
1544                 /* AP address is in bits 31:24 of DP_SELECT */
1545                 if (apsel >= 256)
1546                         return ERROR_COMMAND_SYNTAX_ERROR;
1547                 break;
1548         default:
1549                 return ERROR_COMMAND_SYNTAX_ERROR;
1550         }
1551
1552         dap_ap_select(dap, apsel);
1553
1554         retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
1555         if (retval != ERROR_OK)
1556                 return retval;
1557         retval = dap_run(dap);
1558         if (retval != ERROR_OK)
1559                 return retval;
1560
1561         command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
1562
1563         return retval;
1564 }
1565
1566 COMMAND_HANDLER(dap_ti_be_32_quirks_command)
1567 {
1568         struct target *target = get_current_target(CMD_CTX);
1569         struct arm *arm = target_to_arm(target);
1570         struct adiv5_dap *dap = arm->dap;
1571
1572         uint32_t enable = dap->ti_be_32_quirks;
1573
1574         switch (CMD_ARGC) {
1575         case 0:
1576                 break;
1577         case 1:
1578                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], enable);
1579                 if (enable > 1)
1580                         return ERROR_COMMAND_SYNTAX_ERROR;
1581                 break;
1582         default:
1583                 return ERROR_COMMAND_SYNTAX_ERROR;
1584         }
1585         dap->ti_be_32_quirks = enable;
1586         command_print(CMD_CTX, "TI BE-32 quirks mode %s",
1587                 enable ? "enabled" : "disabled");
1588
1589         return 0;
1590 }
1591
1592 static const struct command_registration dap_commands[] = {
1593         {
1594                 .name = "info",
1595                 .handler = handle_dap_info_command,
1596                 .mode = COMMAND_EXEC,
1597                 .help = "display ROM table for MEM-AP "
1598                         "(default currently selected AP)",
1599                 .usage = "[ap_num]",
1600         },
1601         {
1602                 .name = "apsel",
1603                 .handler = dap_apsel_command,
1604                 .mode = COMMAND_EXEC,
1605                 .help = "Set the currently selected AP (default 0) "
1606                         "and display the result",
1607                 .usage = "[ap_num]",
1608         },
1609         {
1610                 .name = "apcsw",
1611                 .handler = dap_apcsw_command,
1612                 .mode = COMMAND_EXEC,
1613                 .help = "Set csw access bit ",
1614                 .usage = "[sprot]",
1615         },
1616
1617         {
1618                 .name = "apid",
1619                 .handler = dap_apid_command,
1620                 .mode = COMMAND_EXEC,
1621                 .help = "return ID register from AP "
1622                         "(default currently selected AP)",
1623                 .usage = "[ap_num]",
1624         },
1625         {
1626                 .name = "baseaddr",
1627                 .handler = dap_baseaddr_command,
1628                 .mode = COMMAND_EXEC,
1629                 .help = "return debug base address from MEM-AP "
1630                         "(default currently selected AP)",
1631                 .usage = "[ap_num]",
1632         },
1633         {
1634                 .name = "memaccess",
1635                 .handler = dap_memaccess_command,
1636                 .mode = COMMAND_EXEC,
1637                 .help = "set/get number of extra tck for MEM-AP memory "
1638                         "bus access [0-255]",
1639                 .usage = "[cycles]",
1640         },
1641         {
1642                 .name = "ti_be_32_quirks",
1643                 .handler = dap_ti_be_32_quirks_command,
1644                 .mode = COMMAND_CONFIG,
1645                 .help = "set/get quirks mode for TI TMS450/TMS570 processors",
1646                 .usage = "[enable]",
1647         },
1648         COMMAND_REGISTRATION_DONE
1649 };
1650
1651 const struct command_registration dap_command_handlers[] = {
1652         {
1653                 .name = "dap",
1654                 .mode = COMMAND_EXEC,
1655                 .help = "DAP command group",
1656                 .usage = "",
1657                 .chain = dap_commands,
1658         },
1659         COMMAND_REGISTRATION_DONE
1660 };