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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Hongtao Zheng                                   *
   9  *   hontor@126.com                                                        *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm9tdmi.h"
  31
  32 #include "arm7_9_common.h"
  33 #include "register.h"
  34 #include "target.h"
  35 #include "armv4_5.h"
  36 #include "embeddedice.h"
  37 #include "etm.h"
  38 #include "etb.h"
  39 #include "log.h"
  40 #include "jtag.h"
  41 #include "arm_jtag.h"
  42
  43 #include <stdlib.h>
  44 #include <string.h>
  45
  46 #if 0
  47 #define _DEBUG_INSTRUCTION_EXECUTION_
  48 #endif
  49
  50 /* cli handling */
  51 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52
  53 /* forward declarations */
  54 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
  55
  56 int arm9tdmi_quit(void);
  57
  58 target_type_t arm9tdmi_target =
  59 {
  60         .name = "arm9tdmi",
  61
  62         .poll = arm7_9_poll,
  63         .arch_state = armv4_5_arch_state,
  64
  65         .target_request_data = arm7_9_target_request_data,
  66
  67         .halt = arm7_9_halt,
  68         .resume = arm7_9_resume,
  69         .step = arm7_9_step,
  70
  71         .assert_reset = arm7_9_assert_reset,
  72         .deassert_reset = arm7_9_deassert_reset,
  73         .soft_reset_halt = arm7_9_soft_reset_halt,
  74
  75         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  76
  77         .read_memory = arm7_9_read_memory,
  78         .write_memory = arm7_9_write_memory,
  79         .bulk_write_memory = arm7_9_bulk_write_memory,
  80         .checksum_memory = arm7_9_checksum_memory,
  81         .blank_check_memory = arm7_9_blank_check_memory,
  82
  83         .run_algorithm = armv4_5_run_algorithm,
  84
  85         .add_breakpoint = arm7_9_add_breakpoint,
  86         .remove_breakpoint = arm7_9_remove_breakpoint,
  87         .add_watchpoint = arm7_9_add_watchpoint,
  88         .remove_watchpoint = arm7_9_remove_watchpoint,
  89
  90         .register_commands = arm9tdmi_register_commands,
  91         .target_create = arm9tdmi_target_create,
  92         .init_target = arm9tdmi_init_target,
  93         .examine = arm9tdmi_examine,
  94         .quit = arm9tdmi_quit
  95 };
  96
  97 arm9tdmi_vector_t arm9tdmi_vectors[] =
  98 {
  99         {"reset", ARM9TDMI_RESET_VECTOR},
 100         {"undef", ARM9TDMI_UNDEF_VECTOR},
 101         {"swi", ARM9TDMI_SWI_VECTOR},
 102         {"pabt", ARM9TDMI_PABT_VECTOR},
 103         {"dabt", ARM9TDMI_DABT_VECTOR},
 104         {"reserved", ARM9TDMI_RESERVED_VECTOR},
 105         {"irq", ARM9TDMI_IRQ_VECTOR},
 106         {"fiq", ARM9TDMI_FIQ_VECTOR},
 107         {0, 0},
 108 };
 109
 110 int arm9tdmi_examine_debug_reason(target_t *target)
 111 {
 112         int retval = ERROR_OK;
 113         /* get pointers to arch-specific information */
 114         armv4_5_common_t *armv4_5 = target->arch_info;
 115         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 116
 117         /* only check the debug reason if we don't know it already */
 118         if ((target->debug_reason != DBG_REASON_DBGRQ)
 119                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 120         {
 121                 scan_field_t fields[3];
 122                 u8 databus[4];
 123                 u8 instructionbus[4];
 124                 u8 debug_reason;
 125
 126                 jtag_add_end_state(TAP_DRPAUSE);
 127
 128                 fields[0].tap = arm7_9->jtag_info.tap;
 129                 fields[0].num_bits = 32;
 130                 fields[0].out_value = NULL;
 131
 132                 fields[0].in_value = databus;
 133
 134
 135                 fields[0].in_handler = NULL;
 136
 137
 138                 fields[1].tap = arm7_9->jtag_info.tap;
 139                 fields[1].num_bits = 3;
 140                 fields[1].out_value = NULL;
 141
 142                 fields[1].in_value = &debug_reason;
 143
 144
 145                 fields[1].in_handler = NULL;
 146
 147
 148                 fields[2].tap = arm7_9->jtag_info.tap;
 149                 fields[2].num_bits = 32;
 150                 fields[2].out_value = NULL;
 151
 152                 fields[2].in_value = instructionbus;
 153
 154
 155                 fields[2].in_handler = NULL;
 156
 157
 158                 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 159                 {
 160                         return retval;
 161                 }
 162                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 163
 164                 jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
 165                 if((retval = jtag_execute_queue()) != ERROR_OK)
 166                 {
 167                         return retval;
 168                 }
 169
 170                 fields[0].in_value = NULL;
 171                 fields[0].out_value = databus;
 172                 fields[1].in_value = NULL;
 173                 fields[1].out_value = &debug_reason;
 174                 fields[2].in_value = NULL;
 175                 fields[2].out_value = instructionbus;
 176
 177                 jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
 178
 179                 if (debug_reason & 0x4)
 180                         if (debug_reason & 0x2)
 181                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 182                 else
 183                         target->debug_reason = DBG_REASON_WATCHPOINT;
 184                 else
 185                         target->debug_reason = DBG_REASON_BREAKPOINT;
 186         }
 187
 188         return ERROR_OK;
 189 }
 190
 191 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 192 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 193 {
 194         int retval = ERROR_OK;
 195         scan_field_t fields[3];
 196         u8 out_buf[4];
 197         u8 instr_buf[4];
 198         u8 sysspeed_buf = 0x0;
 199
 200         /* prepare buffer */
 201         buf_set_u32(out_buf, 0, 32, out);
 202
 203         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 204
 205         if (sysspeed)
 206                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 207
 208         jtag_add_end_state(TAP_DRPAUSE);
 209         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 210         {
 211                 return retval;
 212         }
 213
 214         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 215
 216         fields[0].tap = jtag_info->tap;
 217         fields[0].num_bits = 32;
 218         fields[0].out_value = out_buf;
 219         fields[0].in_value = NULL;
 220         fields[0].in_handler = NULL;
 221
 222         fields[1].tap = jtag_info->tap;
 223         fields[1].num_bits = 3;
 224         fields[1].out_value = &sysspeed_buf;
 225         fields[1].in_value = NULL;
 226         fields[1].in_handler = NULL;
 227
 228
 229         fields[2].tap = jtag_info->tap;
 230         fields[2].num_bits = 32;
 231         fields[2].out_value = instr_buf;
 232         fields[2].in_value = NULL;
 233         fields[2].in_handler = NULL;
 234
 235         if (in)
 236         {
 237                 u8 tmp[4];
 238                 fields[0].in_value=tmp;
 239                 jtag_add_dr_scan_now(3, fields, TAP_INVALID);
 240
 241                 *in=flip_u32(le_to_h_u32(tmp), 32);
 242         }
 243         else
 244         {
 245                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 246         }
 247
 248         jtag_add_runtest(0, TAP_INVALID);
 249
 250 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 251         {
 252                 if((retval = jtag_execute_queue()) != ERROR_OK)
 253                 {
 254                         return retval;
 255                 }
 256
 257                 if (in)
 258                 {
 259                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 260                 }
 261                 else
 262                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 263         }
 264 #endif
 265
 266         return ERROR_OK;
 267 }
 268
 269 /* just read data (instruction and data-out = don't care) */
 270 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 271 {
 272         int retval = ERROR_OK;;
 273         scan_field_t fields[3];
 274
 275         jtag_add_end_state(TAP_DRPAUSE);
 276         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 277         {
 278                 return retval;
 279         }
 280
 281         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 282
 283         fields[0].tap = jtag_info->tap;
 284         fields[0].num_bits = 32;
 285         fields[0].out_value = NULL;
 286
 287         fields[0].in_value = NULL;
 288         fields[0].in_handler = arm_jtag_buf_to_u32; /* deprecated! invoke this from user code! */
 289         fields[0].in_handler_priv = in;
 290
 291
 292
 293         fields[1].tap = jtag_info->tap;
 294         fields[1].num_bits = 3;
 295         fields[1].out_value = NULL;
 296
 297         fields[1].in_value = NULL;
 298         fields[1].in_handler = NULL;
 299
 300
 301
 302
 303         fields[2].tap = jtag_info->tap;
 304         fields[2].num_bits = 32;
 305         fields[2].out_value = NULL;
 306
 307         fields[2].in_value = NULL;
 308
 309
 310         fields[2].in_handler = NULL;
 311
 312
 313         jtag_add_dr_scan(3, fields, TAP_INVALID);
 314
 315         jtag_add_runtest(0, TAP_INVALID);
 316
 317 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 318         {
 319                 if((retval = jtag_execute_queue()) != ERROR_OK)
 320                 {
 321                         return retval;
 322                 }
 323
 324                 if (in)
 325                 {
 326                         LOG_DEBUG("in: 0x%8.8x", *in);
 327                 }
 328                 else
 329                 {
 330                         LOG_ERROR("BUG: called with in == NULL");
 331                 }
 332         }
 333 #endif
 334
 335         return ERROR_OK;
 336 }
 337
 338 /* clock the target, and read the databus
 339  * the *in pointer points to a buffer where elements of 'size' bytes
 340  * are stored in big (be==1) or little (be==0) endianness
 341  */
 342 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 343 {
 344         int retval = ERROR_OK;
 345         scan_field_t fields[3];
 346
 347         jtag_add_end_state(TAP_DRPAUSE);
 348         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 349         {
 350                 return retval;
 351         }
 352
 353         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 354
 355         fields[0].tap = jtag_info->tap;
 356         fields[0].num_bits = 32;
 357         fields[0].out_value = NULL;
 358
 359         fields[0].in_value = NULL;
 360         switch (size)
 361         {
 362                 case 4:
 363                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32; /* deprecated! invoke this from user code! */
 364                         break;
 365                 case 2:
 366                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16; /* deprecated! invoke this from user code! */
 367                         break;
 368                 case 1:
 369                         fields[0].in_handler = arm_jtag_buf_to_8; /* deprecated! invoke this from user code! */
 370                         break;
 371         }
 372         fields[0].in_handler_priv = in;
 373
 374
 375
 376         fields[1].tap = jtag_info->tap;
 377         fields[1].num_bits = 3;
 378         fields[1].out_value = NULL;
 379
 380         fields[1].in_value = NULL;
 381         fields[1].in_handler = NULL;
 382
 383
 384
 385
 386         fields[2].tap = jtag_info->tap;
 387         fields[2].num_bits = 32;
 388         fields[2].out_value = NULL;
 389
 390         fields[2].in_value = NULL;
 391
 392
 393         fields[2].in_handler = NULL;
 394
 395
 396         jtag_add_dr_scan(3, fields, TAP_INVALID);
 397
 398         jtag_add_runtest(0, TAP_INVALID);
 399
 400 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 401         {
 402                 if((retval = jtag_execute_queue()) != ERROR_OK)
 403                 {
 404                         return retval;
 405                 }
 406
 407                 if (in)
 408                 {
 409                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 410                 }
 411                 else
 412                 {
 413                         LOG_ERROR("BUG: called with in == NULL");
 414                 }
 415         }
 416 #endif
 417
 418         return ERROR_OK;
 419 }
 420
 421 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 422 {
 423         int retval = ERROR_OK;
 424         /* get pointers to arch-specific information */
 425         armv4_5_common_t *armv4_5 = target->arch_info;
 426         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 427         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 428
 429         /* save r0 before using it and put system in ARM state
 430          * to allow common handling of ARM and THUMB debugging */
 431
 432         /* fetch STR r0, [r0] */
 433         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 434         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 435         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 436         /* STR r0, [r0] in Memory */
 437         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 438
 439         /* MOV r0, r15 fetched, STR in Decode */
 440         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 441         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 442         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 443         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 444         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 445         /* nothing fetched, STR r0, [r0] in Memory */
 446         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 447
 448         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 449         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 450         /* LDR in Decode */
 451         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 452         /* LDR in Execute */
 453         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 454         /* LDR in Memory (to account for interlock) */
 455         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 456
 457         /* fetch BX */
 458         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 459         /* NOP fetched, BX in Decode, MOV in Execute */
 460         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 461         /* NOP fetched, BX in Execute (1) */
 462         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 463
 464         if((retval = jtag_execute_queue()) != ERROR_OK)
 465         {
 466                 return;
 467         }
 468
 469         /* fix program counter:
 470          * MOV r0, r15 was the 5th instruction (+8)
 471          * reading PC in Thumb state gives address of instruction + 4
 472          */
 473         *pc -= 0xc;
 474 }
 475
 476 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 477 {
 478         int i;
 479         /* get pointers to arch-specific information */
 480         armv4_5_common_t *armv4_5 = target->arch_info;
 481         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 482         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 483
 484         /* STMIA r0-15, [r0] at debug speed
 485          * register values will start to appear on 4th DCLK
 486          */
 487         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 488
 489         /* fetch NOP, STM in DECODE stage */
 490         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 491         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 492         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 493
 494         for (i = 0; i <= 15; i++)
 495         {
 496                 if (mask & (1 << i))
 497                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 498                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 499         }
 500 }
 501
 502 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 503 {
 504         int i;
 505         /* get pointers to arch-specific information */
 506         armv4_5_common_t *armv4_5 = target->arch_info;
 507         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 508         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 509         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 510         u32 *buf_u32 = buffer;
 511         u16 *buf_u16 = buffer;
 512         u8 *buf_u8 = buffer;
 513
 514         /* STMIA r0-15, [r0] at debug speed
 515          * register values will start to appear on 4th DCLK
 516          */
 517         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 518
 519         /* fetch NOP, STM in DECODE stage */
 520         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 521         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 522         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 523
 524         for (i = 0; i <= 15; i++)
 525         {
 526                 if (mask & (1 << i))
 527                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 528                         switch (size)
 529                         {
 530                                 case 4:
 531                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 532                                         break;
 533                                 case 2:
 534                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 535                                         break;
 536                                 case 1:
 537                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 538                                         break;
 539                         }
 540         }
 541 }
 542
 543 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 544 {
 545         /* get pointers to arch-specific information */
 546         armv4_5_common_t *armv4_5 = target->arch_info;
 547         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 548         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 549
 550         /* MRS r0, cpsr */
 551         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 552         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 553         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 554         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 555         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 556
 557         /* STR r0, [r15] */
 558         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 559         /* fetch NOP, STR in DECODE stage */
 560         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 561         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 562         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 563         /* nothing fetched, STR in MEMORY */
 564         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 565 }
 566
 567 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 568 {
 569         /* get pointers to arch-specific information */
 570         armv4_5_common_t *armv4_5 = target->arch_info;
 571         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 572         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 573
 574         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 575
 576         /* MSR1 fetched */
 577         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 578         /* MSR2 fetched, MSR1 in DECODE */
 579         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 580         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 581         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 582         /* nothing fetched, MSR1 in EXECUTE (2) */
 583         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 584         /* nothing fetched, MSR1 in EXECUTE (3) */
 585         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 586         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 587         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 588         /* nothing fetched, MSR2 in EXECUTE (2) */
 589         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 590         /* nothing fetched, MSR2 in EXECUTE (3) */
 591         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 592         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 593         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 594         /* nothing fetched, MSR3 in EXECUTE (2) */
 595         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 596         /* nothing fetched, MSR3 in EXECUTE (3) */
 597         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 598         /* NOP fetched, MSR4 in EXECUTE (1) */
 599         /* last MSR writes flags, which takes only one cycle */
 600         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 601 }
 602
 603 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 604 {
 605         /* get pointers to arch-specific information */
 606         armv4_5_common_t *armv4_5 = target->arch_info;
 607         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 608         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 609
 610         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 611
 612         /* MSR fetched */
 613         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 614         /* NOP fetched, MSR in DECODE */
 615         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 616         /* NOP fetched, MSR in EXECUTE (1) */
 617         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 618
 619         /* rot == 4 writes flags, which takes only one cycle */
 620         if (rot != 4)
 621         {
 622                 /* nothing fetched, MSR in EXECUTE (2) */
 623                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 624                 /* nothing fetched, MSR in EXECUTE (3) */
 625                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 626         }
 627 }
 628
 629 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 630 {
 631         int i;
 632         /* get pointers to arch-specific information */
 633         armv4_5_common_t *armv4_5 = target->arch_info;
 634         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 635         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 636
 637         /* LDMIA r0-15, [r0] at debug speed
 638         * register values will start to appear on 4th DCLK
 639         */
 640         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 641
 642         /* fetch NOP, LDM in DECODE stage */
 643         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 644         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 645         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 646
 647         for (i = 0; i <= 15; i++)
 648         {
 649                 if (mask & (1 << i))
 650                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 651                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 652         }
 653         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 654 }
 655
 656 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 657 {
 658         /* get pointers to arch-specific information */
 659         armv4_5_common_t *armv4_5 = target->arch_info;
 660         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 661         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 662
 663         /* put system-speed load-multiple into the pipeline */
 664         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 665         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 666 }
 667
 668 void arm9tdmi_load_hword_reg(target_t *target, int num)
 669 {
 670         /* get pointers to arch-specific information */
 671         armv4_5_common_t *armv4_5 = target->arch_info;
 672         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 673         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 674
 675         /* put system-speed load half-word into the pipeline */
 676         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 677         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 678 }
 679
 680 void arm9tdmi_load_byte_reg(target_t *target, int num)
 681 {
 682         /* get pointers to arch-specific information */
 683         armv4_5_common_t *armv4_5 = target->arch_info;
 684         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 685         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 686
 687         /* put system-speed load byte into the pipeline */
 688         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 689         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 690 }
 691
 692 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 693 {
 694         /* get pointers to arch-specific information */
 695         armv4_5_common_t *armv4_5 = target->arch_info;
 696         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 697         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 698
 699         /* put system-speed store-multiple into the pipeline */
 700         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 701         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 702 }
 703
 704 void arm9tdmi_store_hword_reg(target_t *target, int num)
 705 {
 706         /* get pointers to arch-specific information */
 707         armv4_5_common_t *armv4_5 = target->arch_info;
 708         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 709         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 710
 711         /* put system-speed store half-word into the pipeline */
 712         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 713         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 714 }
 715
 716 void arm9tdmi_store_byte_reg(target_t *target, int num)
 717 {
 718         /* get pointers to arch-specific information */
 719         armv4_5_common_t *armv4_5 = target->arch_info;
 720         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 721         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 722
 723         /* put system-speed store byte into the pipeline */
 724         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 725         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 726 }
 727
 728 void arm9tdmi_write_pc(target_t *target, u32 pc)
 729 {
 730         /* get pointers to arch-specific information */
 731         armv4_5_common_t *armv4_5 = target->arch_info;
 732         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 733         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 734
 735         /* LDMIA r0-15, [r0] at debug speed
 736          * register values will start to appear on 4th DCLK
 737          */
 738         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 739
 740         /* fetch NOP, LDM in DECODE stage */
 741         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 742         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 743         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 744         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 745         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 746         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 747         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 748         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 749         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 750         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 751         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 752 }
 753
 754 void arm9tdmi_branch_resume(target_t *target)
 755 {
 756         /* get pointers to arch-specific information */
 757         armv4_5_common_t *armv4_5 = target->arch_info;
 758         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 759         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 760
 761         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 762         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 763 }
 764
 765 void arm9tdmi_branch_resume_thumb(target_t *target)
 766 {
 767         LOG_DEBUG("-");
 768
 769         /* get pointers to arch-specific information */
 770         armv4_5_common_t *armv4_5 = target->arch_info;
 771         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 772         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 773         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 774
 775         /* LDMIA r0-15, [r0] at debug speed
 776         * register values will start to appear on 4th DCLK
 777         */
 778         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 779
 780         /* fetch NOP, LDM in DECODE stage */
 781         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 782         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 783         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 784         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 785         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 786         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 787         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 788
 789         /* Branch and eXchange */
 790         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 791
 792         embeddedice_read_reg(dbg_stat);
 793
 794         /* fetch NOP, BX in DECODE stage */
 795         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 796
 797         embeddedice_read_reg(dbg_stat);
 798
 799         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 800         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 801
 802         /* target is now in Thumb state */
 803         embeddedice_read_reg(dbg_stat);
 804
 805         /* load r0 value, MOV_IM in Decode*/
 806         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 807         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 808         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 809         /* fetch NOP, LDR in Execute */
 810         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 811         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 812         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 813         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 814         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 815
 816         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 817         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 818
 819         embeddedice_read_reg(dbg_stat);
 820
 821         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 822         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 823 }
 824
 825 void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
 826 {
 827         /* get pointers to arch-specific information */
 828         armv4_5_common_t *armv4_5 = target->arch_info;
 829         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 830
 831         if (arm7_9->has_single_step)
 832         {
 833                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 834                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 835         }
 836         else
 837         {
 838                 arm7_9_enable_eice_step(target, next_pc);
 839         }
 840 }
 841
 842 void arm9tdmi_disable_single_step(target_t *target)
 843 {
 844         /* get pointers to arch-specific information */
 845         armv4_5_common_t *armv4_5 = target->arch_info;
 846         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 847
 848         if (arm7_9->has_single_step)
 849         {
 850                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 851                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 852         }
 853         else
 854         {
 855                 arm7_9_disable_eice_step(target);
 856         }
 857 }
 858
 859 void arm9tdmi_build_reg_cache(target_t *target)
 860 {
 861         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 862         /* get pointers to arch-specific information */
 863         armv4_5_common_t *armv4_5 = target->arch_info;
 864
 865         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 866         armv4_5->core_cache = (*cache_p);
 867 }
 868
 869 int arm9tdmi_examine(struct target_s *target)
 870 {
 871         /* get pointers to arch-specific information */
 872         int retval;
 873         armv4_5_common_t *armv4_5 = target->arch_info;
 874         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 875         if (!target->type->examined)
 876         {
 877                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 878                 reg_cache_t *t;
 879                 /* one extra register (vector catch) */
 880                 t=embeddedice_build_reg_cache(target, arm7_9);
 881                 if (t==NULL)
 882                         return ERROR_FAIL;
 883                 (*cache_p) = t;
 884                 arm7_9->eice_cache = (*cache_p);
 885
 886                 if (arm7_9->etm_ctx)
 887                 {
 888                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 889                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 890                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 891                 }
 892                 target->type->examined = 1;
 893         }
 894         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 895                 return retval;
 896         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 897                 return retval;
 898         if (arm7_9->etm_ctx)
 899         {
 900                 if ((retval=etm_setup(target))!=ERROR_OK)
 901                         return retval;
 902         }
 903         return ERROR_OK;
 904 }
 905
 906 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 907 {
 908
 909         arm9tdmi_build_reg_cache(target);
 910
 911         return ERROR_OK;
 912 }
 913
 914 int arm9tdmi_quit(void)
 915 {
 916         return ERROR_OK;
 917 }
 918
 919 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
 920 {
 921         armv4_5_common_t *armv4_5;
 922         arm7_9_common_t *arm7_9;
 923
 924         arm7_9 = &arm9tdmi->arm7_9_common;
 925         armv4_5 = &arm7_9->armv4_5_common;
 926
 927         /* prepare JTAG information for the new target */
 928         arm7_9->jtag_info.tap = tap;
 929         arm7_9->jtag_info.scann_size = 5;
 930
 931         /* register arch-specific functions */
 932         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 933         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 934         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 935         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 936         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 937
 938         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 939         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 940         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 941
 942         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 943         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 944         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 945
 946         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 947         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 948         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 949
 950         arm7_9->write_pc = arm9tdmi_write_pc;
 951         arm7_9->branch_resume = arm9tdmi_branch_resume;
 952         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 953
 954         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 955         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 956
 957         arm7_9->pre_debug_entry = NULL;
 958         arm7_9->post_debug_entry = NULL;
 959
 960         arm7_9->pre_restore_context = NULL;
 961         arm7_9->post_restore_context = NULL;
 962
 963         /* initialize arch-specific breakpoint handling */
 964         arm7_9->arm_bkpt = 0xdeeedeee;
 965         arm7_9->thumb_bkpt = 0xdeee;
 966
 967         arm7_9->dbgreq_adjust_pc = 3;
 968         arm7_9->arch_info = arm9tdmi;
 969
 970         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 971         arm9tdmi->arch_info = NULL;
 972
 973         arm7_9_init_arch_info(target, arm7_9);
 974
 975         /* override use of DBGRQ, this is safe on ARM9TDMI */
 976         arm7_9->use_dbgrq = 1;
 977
 978         /* all ARM9s have the vector catch register */
 979         arm7_9->has_vector_catch = 1;
 980
 981         return ERROR_OK;
 982 }
 983
 984 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
 985 {
 986         armv4_5_common_t *armv4_5 = target->arch_info;
 987         arm7_9_common_t *arm7_9;
 988         arm9tdmi_common_t *arm9tdmi;
 989
 990         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 991         {
 992                 return -1;
 993         }
 994
 995         arm7_9 = armv4_5->arch_info;
 996         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 997         {
 998                 return -1;
 999         }
1000
1001         arm9tdmi = arm7_9->arch_info;
1002         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
1003         {
1004                 return -1;
1005         }
1006
1007         *armv4_5_p = armv4_5;
1008         *arm7_9_p = arm7_9;
1009         *arm9tdmi_p = arm9tdmi;
1010
1011         return ERROR_OK;
1012 }
1013
1014 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
1015 {
1016         arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
1017
1018         arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
1019
1020         return ERROR_OK;
1021 }
1022
1023 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1024 {
1025         int retval;
1026         command_t *arm9tdmi_cmd;
1027
1028         retval = arm7_9_register_commands(cmd_ctx);
1029         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1030         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1031
1032         return retval;
1033 }
1034
1035 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1036 {
1037         target_t *target = get_current_target(cmd_ctx);
1038         armv4_5_common_t *armv4_5;
1039         arm7_9_common_t *arm7_9;
1040         arm9tdmi_common_t *arm9tdmi;
1041         reg_t *vector_catch;
1042         u32 vector_catch_value;
1043         int i, j;
1044
1045         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1046         {
1047                 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1048                 return ERROR_OK;
1049         }
1050
1051         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1052
1053         /* read the vector catch register if necessary */
1054         if (!vector_catch->valid)
1055                 embeddedice_read_reg(vector_catch);
1056
1057         /* get the current setting */
1058         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1059
1060         if (argc > 0)
1061         {
1062                 vector_catch_value = 0x0;
1063                 if (strcmp(args[0], "all") == 0)
1064                 {
1065                         vector_catch_value = 0xdf;
1066                 }
1067                 else if (strcmp(args[0], "none") == 0)
1068                 {
1069                         /* do nothing */
1070                 }
1071                 else
1072                 {
1073                         for (i = 0; i < argc; i++)
1074                         {
1075                                 /* go through list of vectors */
1076                                 for(j = 0; arm9tdmi_vectors[j].name; j++)
1077                                 {
1078                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1079                                         {
1080                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1081                                                 break;
1082                                         }
1083                                 }
1084
1085                                 /* complain if vector wasn't found */
1086                                 if (!arm9tdmi_vectors[j].name)
1087                                 {
1088                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1089
1090                                         /* reread current setting */
1091                                         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1092
1093                                         break;
1094                                 }
1095                         }
1096                 }
1097
1098                 /* store new settings */
1099                 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1100                 embeddedice_store_reg(vector_catch);
1101         }
1102
1103         /* output current settings (skip RESERVED vector) */
1104         for (i = 0; i < 8; i++)
1105         {
1106                 if (i != 5)
1107                 {
1108                         command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1109                                 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1110                 }
1111         }
1112
1113         return ERROR_OK;
1114 }