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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Hongtao Zheng                                   *
   9  *   hontor@126.com                                                        *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm9tdmi.h"
  31 #include "target_type.h"
  32
  33
  34 /*
  35  * NOTE:  this holds code that's used with multiple ARM9 processors:
  36  *  - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
  37  *  - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
  38  *  - ARM9EJS (ARMv5TEJ) ... in ARM926 core
  39  *
  40  * In short, the file name is a misnomer ... it is NOT specific to
  41  * that first generation ARM9 processor, or cores using it.
  42  */
  43
  44 #if 0
  45 #define _DEBUG_INSTRUCTION_EXECUTION_
  46 #endif
  47
  48 /* forward declarations */
  49 static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp);
  50
  51 target_type_t arm9tdmi_target =
  52 {
  53         .name = "arm9tdmi",
  54
  55         .poll = arm7_9_poll,
  56         .arch_state = armv4_5_arch_state,
  57
  58         .target_request_data = arm7_9_target_request_data,
  59
  60         .halt = arm7_9_halt,
  61         .resume = arm7_9_resume,
  62         .step = arm7_9_step,
  63
  64         .assert_reset = arm7_9_assert_reset,
  65         .deassert_reset = arm7_9_deassert_reset,
  66         .soft_reset_halt = arm7_9_soft_reset_halt,
  67
  68         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  69
  70         .read_memory = arm7_9_read_memory,
  71         .write_memory = arm7_9_write_memory,
  72         .bulk_write_memory = arm7_9_bulk_write_memory,
  73         .checksum_memory = arm7_9_checksum_memory,
  74         .blank_check_memory = arm7_9_blank_check_memory,
  75
  76         .run_algorithm = armv4_5_run_algorithm,
  77
  78         .add_breakpoint = arm7_9_add_breakpoint,
  79         .remove_breakpoint = arm7_9_remove_breakpoint,
  80         .add_watchpoint = arm7_9_add_watchpoint,
  81         .remove_watchpoint = arm7_9_remove_watchpoint,
  82
  83         .register_commands = arm9tdmi_register_commands,
  84         .target_create = arm9tdmi_target_create,
  85         .init_target = arm9tdmi_init_target,
  86         .examine = arm9tdmi_examine,
  87 };
  88
  89 static arm9tdmi_vector_t arm9tdmi_vectors[] =
  90 {
  91         {"reset", ARM9TDMI_RESET_VECTOR},
  92         {"undef", ARM9TDMI_UNDEF_VECTOR},
  93         {"swi", ARM9TDMI_SWI_VECTOR},
  94         {"pabt", ARM9TDMI_PABT_VECTOR},
  95         {"dabt", ARM9TDMI_DABT_VECTOR},
  96         {"irq", ARM9TDMI_IRQ_VECTOR},
  97         {"fiq", ARM9TDMI_FIQ_VECTOR},
  98         {0, 0},
  99 };
 100
 101 int arm9tdmi_examine_debug_reason(target_t *target)
 102 {
 103         int retval = ERROR_OK;
 104         /* get pointers to arch-specific information */
 105         armv4_5_common_t *armv4_5 = target->arch_info;
 106         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 107
 108         /* only check the debug reason if we don't know it already */
 109         if ((target->debug_reason != DBG_REASON_DBGRQ)
 110                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 111         {
 112                 scan_field_t fields[3];
 113                 uint8_t databus[4];
 114                 uint8_t instructionbus[4];
 115                 uint8_t debug_reason;
 116
 117                 jtag_set_end_state(TAP_DRPAUSE);
 118
 119                 fields[0].tap = arm7_9->jtag_info.tap;
 120                 fields[0].num_bits = 32;
 121                 fields[0].out_value = NULL;
 122                 fields[0].in_value = databus;
 123
 124                 fields[1].tap = arm7_9->jtag_info.tap;
 125                 fields[1].num_bits = 3;
 126                 fields[1].out_value = NULL;
 127                 fields[1].in_value = &debug_reason;
 128
 129                 fields[2].tap = arm7_9->jtag_info.tap;
 130                 fields[2].num_bits = 32;
 131                 fields[2].out_value = NULL;
 132                 fields[2].in_value = instructionbus;
 133
 134                 if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 135                 {
 136                         return retval;
 137                 }
 138                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 139
 140                 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
 141                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 142                 {
 143                         return retval;
 144                 }
 145
 146                 fields[0].in_value = NULL;
 147                 fields[0].out_value = databus;
 148                 fields[1].in_value = NULL;
 149                 fields[1].out_value = &debug_reason;
 150                 fields[2].in_value = NULL;
 151                 fields[2].out_value = instructionbus;
 152
 153                 jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
 154
 155                 if (debug_reason & 0x4)
 156                         if (debug_reason & 0x2)
 157                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 158                 else
 159                         target->debug_reason = DBG_REASON_WATCHPOINT;
 160                 else
 161                         target->debug_reason = DBG_REASON_BREAKPOINT;
 162         }
 163
 164         return ERROR_OK;
 165 }
 166
 167 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 168 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, uint32_t instr, uint32_t out, uint32_t *in, int sysspeed)
 169 {
 170         int retval = ERROR_OK;
 171         scan_field_t fields[3];
 172         uint8_t out_buf[4];
 173         uint8_t instr_buf[4];
 174         uint8_t sysspeed_buf = 0x0;
 175
 176         /* prepare buffer */
 177         buf_set_u32(out_buf, 0, 32, out);
 178
 179         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 180
 181         if (sysspeed)
 182                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 183
 184         jtag_set_end_state(TAP_DRPAUSE);
 185         if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 186         {
 187                 return retval;
 188         }
 189
 190         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 191
 192         fields[0].tap = jtag_info->tap;
 193         fields[0].num_bits = 32;
 194         fields[0].out_value = out_buf;
 195         fields[0].in_value = NULL;
 196
 197         fields[1].tap = jtag_info->tap;
 198         fields[1].num_bits = 3;
 199         fields[1].out_value = &sysspeed_buf;
 200         fields[1].in_value = NULL;
 201
 202         fields[2].tap = jtag_info->tap;
 203         fields[2].num_bits = 32;
 204         fields[2].out_value = instr_buf;
 205         fields[2].in_value = NULL;
 206
 207         if (in)
 208         {
 209                 fields[0].in_value = (uint8_t *)in;
 210                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 211
 212                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
 213         }
 214         else
 215         {
 216                 jtag_add_dr_scan(3, fields, jtag_get_end_state());
 217         }
 218
 219         jtag_add_runtest(0, jtag_get_end_state());
 220
 221 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 222         {
 223                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 224                 {
 225                         return retval;
 226                 }
 227
 228                 if (in)
 229                 {
 230                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 231                 }
 232                 else
 233                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 234         }
 235 #endif
 236
 237         return ERROR_OK;
 238 }
 239
 240 /* just read data (instruction and data-out = don't care) */
 241 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, uint32_t *in)
 242 {
 243         int retval = ERROR_OK;;
 244         scan_field_t fields[3];
 245
 246         jtag_set_end_state(TAP_DRPAUSE);
 247         if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 248         {
 249                 return retval;
 250         }
 251
 252         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 253
 254         fields[0].tap = jtag_info->tap;
 255         fields[0].num_bits = 32;
 256         fields[0].out_value = NULL;
 257         fields[0].in_value = (uint8_t *)in;
 258
 259         fields[1].tap = jtag_info->tap;
 260         fields[1].num_bits = 3;
 261         fields[1].out_value = NULL;
 262         fields[1].in_value = NULL;
 263
 264         fields[2].tap = jtag_info->tap;
 265         fields[2].num_bits = 32;
 266         fields[2].out_value = NULL;
 267         fields[2].in_value = NULL;
 268
 269         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 270
 271         jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
 272
 273         jtag_add_runtest(0, jtag_get_end_state());
 274
 275 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 276         {
 277                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 278                 {
 279                         return retval;
 280                 }
 281
 282                 if (in)
 283                 {
 284                         LOG_DEBUG("in: 0x%8.8x", *in);
 285                 }
 286                 else
 287                 {
 288                         LOG_ERROR("BUG: called with in == NULL");
 289                 }
 290         }
 291 #endif
 292
 293         return ERROR_OK;
 294 }
 295
 296 extern void arm_endianness(uint8_t *tmp, void *in, int size, int be, int flip);
 297
 298 static int arm9endianness(jtag_callback_data_t arg, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t captured)
 299 {
 300   uint8_t *in = (uint8_t *)arg;
 301         arm_endianness((uint8_t *)captured, in, (int)size, (int)be, 0);
 302         return ERROR_OK;
 303 }
 304
 305 /* clock the target, and read the databus
 306  * the *in pointer points to a buffer where elements of 'size' bytes
 307  * are stored in big (be == 1) or little (be == 0) endianness
 308  */
 309 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 310 {
 311         int retval = ERROR_OK;
 312         scan_field_t fields[3];
 313
 314         jtag_set_end_state(TAP_DRPAUSE);
 315         if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 316         {
 317                 return retval;
 318         }
 319
 320         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 321
 322         fields[0].tap = jtag_info->tap;
 323         fields[0].num_bits = 32;
 324         fields[0].out_value = NULL;
 325         jtag_alloc_in_value32(&fields[0]);
 326
 327         fields[1].tap = jtag_info->tap;
 328         fields[1].num_bits = 3;
 329         fields[1].out_value = NULL;
 330         fields[1].in_value = NULL;
 331
 332         fields[2].tap = jtag_info->tap;
 333         fields[2].num_bits = 32;
 334         fields[2].out_value = NULL;
 335         fields[2].in_value = NULL;
 336
 337         jtag_add_dr_scan(3, fields, jtag_get_end_state());
 338
 339         jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
 340
 341         jtag_add_runtest(0, jtag_get_end_state());
 342
 343 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 344         {
 345                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 346                 {
 347                         return retval;
 348                 }
 349
 350                 if (in)
 351                 {
 352                         LOG_DEBUG("in: 0x%8.8x", *(uint32_t*)in);
 353                 }
 354                 else
 355                 {
 356                         LOG_ERROR("BUG: called with in == NULL");
 357                 }
 358         }
 359 #endif
 360
 361         return ERROR_OK;
 362 }
 363
 364 static void arm9tdmi_change_to_arm(target_t *target,
 365                 uint32_t *r0, uint32_t *pc)
 366 {
 367         int retval = ERROR_OK;
 368         /* get pointers to arch-specific information */
 369         armv4_5_common_t *armv4_5 = target->arch_info;
 370         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 371         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 372
 373         /* save r0 before using it and put system in ARM state
 374          * to allow common handling of ARM and THUMB debugging */
 375
 376         /* fetch STR r0, [r0] */
 377         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 378         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 379         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 380         /* STR r0, [r0] in Memory */
 381         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 382
 383         /* MOV r0, r15 fetched, STR in Decode */
 384         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 385         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 386         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 387         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 388         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 389         /* nothing fetched, STR r0, [r0] in Memory */
 390         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 391
 392         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 393         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 394         /* LDR in Decode */
 395         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 396         /* LDR in Execute */
 397         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 398         /* LDR in Memory (to account for interlock) */
 399         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 400
 401         /* fetch BX */
 402         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 403         /* NOP fetched, BX in Decode, MOV in Execute */
 404         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 405         /* NOP fetched, BX in Execute (1) */
 406         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 407
 408         if ((retval = jtag_execute_queue()) != ERROR_OK)
 409         {
 410                 return;
 411         }
 412
 413         /* fix program counter:
 414          * MOV r0, r15 was the 5th instruction (+8)
 415          * reading PC in Thumb state gives address of instruction + 4
 416          */
 417         *pc -= 0xc;
 418 }
 419
 420 void arm9tdmi_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
 421 {
 422         int i;
 423         /* get pointers to arch-specific information */
 424         armv4_5_common_t *armv4_5 = target->arch_info;
 425         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 426         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 427
 428         /* STMIA r0-15, [r0] at debug speed
 429          * register values will start to appear on 4th DCLK
 430          */
 431         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 432
 433         /* fetch NOP, STM in DECODE stage */
 434         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 435         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 436         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 437
 438         for (i = 0; i <= 15; i++)
 439         {
 440                 if (mask & (1 << i))
 441                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 442                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 443         }
 444 }
 445
 446 static void arm9tdmi_read_core_regs_target_buffer(target_t *target,
 447                 uint32_t mask, void* buffer, int size)
 448 {
 449         int i;
 450         /* get pointers to arch-specific information */
 451         armv4_5_common_t *armv4_5 = target->arch_info;
 452         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 453         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 454         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 455         uint32_t *buf_u32 = buffer;
 456         uint16_t *buf_u16 = buffer;
 457         uint8_t *buf_u8 = buffer;
 458
 459         /* STMIA r0-15, [r0] at debug speed
 460          * register values will start to appear on 4th DCLK
 461          */
 462         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 463
 464         /* fetch NOP, STM in DECODE stage */
 465         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 466         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 467         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 468
 469         for (i = 0; i <= 15; i++)
 470         {
 471                 if (mask & (1 << i))
 472                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 473                         switch (size)
 474                         {
 475                                 case 4:
 476                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 477                                         break;
 478                                 case 2:
 479                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 480                                         break;
 481                                 case 1:
 482                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 483                                         break;
 484                         }
 485         }
 486 }
 487
 488 static void arm9tdmi_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
 489 {
 490         /* get pointers to arch-specific information */
 491         armv4_5_common_t *armv4_5 = target->arch_info;
 492         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 493         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 494
 495         /* MRS r0, cpsr */
 496         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 497         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 498         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 499         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 500         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 501
 502         /* STR r0, [r15] */
 503         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 504         /* fetch NOP, STR in DECODE stage */
 505         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 506         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 507         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 508         /* nothing fetched, STR in MEMORY */
 509         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 510 }
 511
 512 static void arm9tdmi_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
 513 {
 514         /* get pointers to arch-specific information */
 515         armv4_5_common_t *armv4_5 = target->arch_info;
 516         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 517         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 518
 519         LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 520
 521         /* MSR1 fetched */
 522         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 523         /* MSR2 fetched, MSR1 in DECODE */
 524         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 525         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 526         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 527         /* nothing fetched, MSR1 in EXECUTE (2) */
 528         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 529         /* nothing fetched, MSR1 in EXECUTE (3) */
 530         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 531         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 532         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 533         /* nothing fetched, MSR2 in EXECUTE (2) */
 534         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 535         /* nothing fetched, MSR2 in EXECUTE (3) */
 536         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 537         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 538         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 539         /* nothing fetched, MSR3 in EXECUTE (2) */
 540         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 541         /* nothing fetched, MSR3 in EXECUTE (3) */
 542         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 543         /* NOP fetched, MSR4 in EXECUTE (1) */
 544         /* last MSR writes flags, which takes only one cycle */
 545         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 546 }
 547
 548 static void arm9tdmi_write_xpsr_im8(target_t *target,
 549                 uint8_t xpsr_im, int rot, int spsr)
 550 {
 551         /* get pointers to arch-specific information */
 552         armv4_5_common_t *armv4_5 = target->arch_info;
 553         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 554         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 555
 556         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 557
 558         /* MSR fetched */
 559         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 560         /* NOP fetched, MSR in DECODE */
 561         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 562         /* NOP fetched, MSR in EXECUTE (1) */
 563         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 564
 565         /* rot == 4 writes flags, which takes only one cycle */
 566         if (rot != 4)
 567         {
 568                 /* nothing fetched, MSR in EXECUTE (2) */
 569                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 570                 /* nothing fetched, MSR in EXECUTE (3) */
 571                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 572         }
 573 }
 574
 575 void arm9tdmi_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
 576 {
 577         int i;
 578         /* get pointers to arch-specific information */
 579         armv4_5_common_t *armv4_5 = target->arch_info;
 580         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 581         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 582
 583         /* LDMIA r0-15, [r0] at debug speed
 584         * register values will start to appear on 4th DCLK
 585         */
 586         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 587
 588         /* fetch NOP, LDM in DECODE stage */
 589         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 590         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 591         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 592
 593         for (i = 0; i <= 15; i++)
 594         {
 595                 if (mask & (1 << i))
 596                         /* nothing fetched, LDM still in EXECUTE (1 + i cycle) */
 597                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 598         }
 599         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 600 }
 601
 602 void arm9tdmi_load_word_regs(target_t *target, uint32_t mask)
 603 {
 604         /* get pointers to arch-specific information */
 605         armv4_5_common_t *armv4_5 = target->arch_info;
 606         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 607         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 608
 609         /* put system-speed load-multiple into the pipeline */
 610         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 611         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 612 }
 613
 614 void arm9tdmi_load_hword_reg(target_t *target, int num)
 615 {
 616         /* get pointers to arch-specific information */
 617         armv4_5_common_t *armv4_5 = target->arch_info;
 618         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 619         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 620
 621         /* put system-speed load half-word into the pipeline */
 622         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 623         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 624 }
 625
 626 void arm9tdmi_load_byte_reg(target_t *target, int num)
 627 {
 628         /* get pointers to arch-specific information */
 629         armv4_5_common_t *armv4_5 = target->arch_info;
 630         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 631         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 632
 633         /* put system-speed load byte into the pipeline */
 634         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 635         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 636 }
 637
 638 void arm9tdmi_store_word_regs(target_t *target, uint32_t mask)
 639 {
 640         /* get pointers to arch-specific information */
 641         armv4_5_common_t *armv4_5 = target->arch_info;
 642         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 643         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 644
 645         /* put system-speed store-multiple into the pipeline */
 646         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 647         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 648 }
 649
 650 void arm9tdmi_store_hword_reg(target_t *target, int num)
 651 {
 652         /* get pointers to arch-specific information */
 653         armv4_5_common_t *armv4_5 = target->arch_info;
 654         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 655         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 656
 657         /* put system-speed store half-word into the pipeline */
 658         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 659         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 660 }
 661
 662 void arm9tdmi_store_byte_reg(target_t *target, int num)
 663 {
 664         /* get pointers to arch-specific information */
 665         armv4_5_common_t *armv4_5 = target->arch_info;
 666         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 667         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 668
 669         /* put system-speed store byte into the pipeline */
 670         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 671         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 672 }
 673
 674 static void arm9tdmi_write_pc(target_t *target, uint32_t pc)
 675 {
 676         /* get pointers to arch-specific information */
 677         armv4_5_common_t *armv4_5 = target->arch_info;
 678         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 679         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 680
 681         /* LDMIA r0-15, [r0] at debug speed
 682          * register values will start to appear on 4th DCLK
 683          */
 684         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 685
 686         /* fetch NOP, LDM in DECODE stage */
 687         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 688         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 689         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 690         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 691         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 692         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 693         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 694         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 695         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 696         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 697         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 698 }
 699
 700 void arm9tdmi_branch_resume(target_t *target)
 701 {
 702         /* get pointers to arch-specific information */
 703         armv4_5_common_t *armv4_5 = target->arch_info;
 704         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 705         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 706
 707         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 708         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 709 }
 710
 711 static void arm9tdmi_branch_resume_thumb(target_t *target)
 712 {
 713         LOG_DEBUG("-");
 714
 715         /* get pointers to arch-specific information */
 716         armv4_5_common_t *armv4_5 = target->arch_info;
 717         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 718         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 719         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 720
 721         /* LDMIA r0-15, [r0] at debug speed
 722         * register values will start to appear on 4th DCLK
 723         */
 724         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 725
 726         /* fetch NOP, LDM in DECODE stage */
 727         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 728         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 729         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 730         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 731         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 732         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 733         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 734
 735         /* Branch and eXchange */
 736         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 737
 738         embeddedice_read_reg(dbg_stat);
 739
 740         /* fetch NOP, BX in DECODE stage */
 741         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 742
 743         embeddedice_read_reg(dbg_stat);
 744
 745         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 746         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 747
 748         /* target is now in Thumb state */
 749         embeddedice_read_reg(dbg_stat);
 750
 751         /* load r0 value, MOV_IM in Decode*/
 752         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 753         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 754         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 755         /* fetch NOP, LDR in Execute */
 756         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 757         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 758         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 759         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 760         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 761
 762         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 763         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 764
 765         embeddedice_read_reg(dbg_stat);
 766
 767         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 768         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 769 }
 770
 771 void arm9tdmi_enable_single_step(target_t *target, uint32_t next_pc)
 772 {
 773         /* get pointers to arch-specific information */
 774         armv4_5_common_t *armv4_5 = target->arch_info;
 775         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 776
 777         if (arm7_9->has_single_step)
 778         {
 779                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 780                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 781         }
 782         else
 783         {
 784                 arm7_9_enable_eice_step(target, next_pc);
 785         }
 786 }
 787
 788 void arm9tdmi_disable_single_step(target_t *target)
 789 {
 790         /* get pointers to arch-specific information */
 791         armv4_5_common_t *armv4_5 = target->arch_info;
 792         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 793
 794         if (arm7_9->has_single_step)
 795         {
 796                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 797                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 798         }
 799         else
 800         {
 801                 arm7_9_disable_eice_step(target);
 802         }
 803 }
 804
 805 static void arm9tdmi_build_reg_cache(target_t *target)
 806 {
 807         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 808         /* get pointers to arch-specific information */
 809         armv4_5_common_t *armv4_5 = target->arch_info;
 810
 811         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 812         armv4_5->core_cache = (*cache_p);
 813 }
 814
 815 int arm9tdmi_examine(struct target_s *target)
 816 {
 817         /* get pointers to arch-specific information */
 818         int retval;
 819         armv4_5_common_t *armv4_5 = target->arch_info;
 820         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 821         if (!target_was_examined(target))
 822         {
 823                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 824                 reg_cache_t *t;
 825                 /* one extra register (vector catch) */
 826                 t = embeddedice_build_reg_cache(target, arm7_9);
 827                 if (t == NULL)
 828                         return ERROR_FAIL;
 829                 (*cache_p) = t;
 830                 arm7_9->eice_cache = (*cache_p);
 831
 832                 if (arm7_9->etm_ctx)
 833                 {
 834                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 835                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 836                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 837                 }
 838                 target_set_examined(target);
 839         }
 840         if ((retval = embeddedice_setup(target)) != ERROR_OK)
 841                 return retval;
 842         if ((retval = arm7_9_setup(target)) != ERROR_OK)
 843                 return retval;
 844         if (arm7_9->etm_ctx)
 845         {
 846                 if ((retval = etm_setup(target)) != ERROR_OK)
 847                         return retval;
 848         }
 849         return ERROR_OK;
 850 }
 851
 852 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 853 {
 854
 855         arm9tdmi_build_reg_cache(target);
 856
 857         return ERROR_OK;
 858 }
 859
 860 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
 861 {
 862         armv4_5_common_t *armv4_5;
 863         arm7_9_common_t *arm7_9;
 864
 865         arm7_9 = &arm9tdmi->arm7_9_common;
 866         armv4_5 = &arm7_9->armv4_5_common;
 867
 868         /* prepare JTAG information for the new target */
 869         arm7_9->jtag_info.tap = tap;
 870         arm7_9->jtag_info.scann_size = 5;
 871
 872         /* register arch-specific functions */
 873         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 874         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 875         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 876         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 877         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 878
 879         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 880         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 881         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 882
 883         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 884         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 885         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 886
 887         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 888         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 889         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 890
 891         arm7_9->write_pc = arm9tdmi_write_pc;
 892         arm7_9->branch_resume = arm9tdmi_branch_resume;
 893         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 894
 895         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 896         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 897
 898         arm7_9->post_debug_entry = NULL;
 899
 900         arm7_9->pre_restore_context = NULL;
 901         arm7_9->post_restore_context = NULL;
 902
 903         /* initialize arch-specific breakpoint handling */
 904         arm7_9->arm_bkpt = 0xdeeedeee;
 905         arm7_9->thumb_bkpt = 0xdeee;
 906
 907         arm7_9->dbgreq_adjust_pc = 3;
 908         arm7_9->arch_info = arm9tdmi;
 909
 910         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 911         arm9tdmi->arch_info = NULL;
 912
 913         arm7_9_init_arch_info(target, arm7_9);
 914
 915         /* override use of DBGRQ, this is safe on ARM9TDMI */
 916         arm7_9->use_dbgrq = 1;
 917
 918         /* all ARM9s have the vector catch register */
 919         arm7_9->has_vector_catch = 1;
 920
 921         return ERROR_OK;
 922 }
 923
 924 static int arm9tdmi_get_arch_pointers(target_t *target,
 925                 armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p,
 926                 arm9tdmi_common_t **arm9tdmi_p)
 927 {
 928         armv4_5_common_t *armv4_5 = target->arch_info;
 929         arm7_9_common_t *arm7_9;
 930         arm9tdmi_common_t *arm9tdmi;
 931
 932         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 933         {
 934                 return -1;
 935         }
 936
 937         arm7_9 = armv4_5->arch_info;
 938         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 939         {
 940                 return -1;
 941         }
 942
 943         arm9tdmi = arm7_9->arch_info;
 944         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 945         {
 946                 return -1;
 947         }
 948
 949         *armv4_5_p = armv4_5;
 950         *arm7_9_p = arm7_9;
 951         *arm9tdmi_p = arm9tdmi;
 952
 953         return ERROR_OK;
 954 }
 955
 956 static int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
 957 {
 958         arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
 959
 960         arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
 961         arm9tdmi->arm7_9_common.armv4_5_common.is_armv4 = true;
 962
 963         return ERROR_OK;
 964 }
 965
 966 static int handle_arm9tdmi_catch_vectors_command(
 967         struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 968 {
 969         target_t *target = get_current_target(cmd_ctx);
 970         armv4_5_common_t *armv4_5;
 971         arm7_9_common_t *arm7_9;
 972         arm9tdmi_common_t *arm9tdmi;
 973         reg_t *vector_catch;
 974         uint32_t vector_catch_value;
 975         int i, j;
 976
 977         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
 978         {
 979                 command_print(cmd_ctx, "current target isn't an ARM9 based target");
 980                 return ERROR_OK;
 981         }
 982
 983         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
 984
 985         /* read the vector catch register if necessary */
 986         if (!vector_catch->valid)
 987                 embeddedice_read_reg(vector_catch);
 988
 989         /* get the current setting */
 990         vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
 991
 992         if (argc > 0)
 993         {
 994                 vector_catch_value = 0x0;
 995                 if (strcmp(args[0], "all") == 0)
 996                 {
 997                         vector_catch_value = 0xdf;
 998                 }
 999                 else if (strcmp(args[0], "none") == 0)
1000                 {
1001                         /* do nothing */
1002                 }
1003                 else
1004                 {
1005                         for (i = 0; i < argc; i++)
1006                         {
1007                                 /* go through list of vectors */
1008                                 for (j = 0; arm9tdmi_vectors[j].name; j++)
1009                                 {
1010                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1011                                         {
1012                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1013                                                 break;
1014                                         }
1015                                 }
1016
1017                                 /* complain if vector wasn't found */
1018                                 if (!arm9tdmi_vectors[j].name)
1019                                 {
1020                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1021
1022                                         /* reread current setting */
1023                                         vector_catch_value = buf_get_u32(
1024                                                         vector_catch->value,
1025                                                         0, 8);
1026
1027                                         break;
1028                                 }
1029                         }
1030                 }
1031
1032                 /* store new settings */
1033                 buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
1034                 embeddedice_store_reg(vector_catch);
1035         }
1036
1037         /* output current settings */
1038         for (i = 0; arm9tdmi_vectors[i].name; i++) {
1039                 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1040                         (vector_catch_value & arm9tdmi_vectors[i].value)
1041                                 ? "catch" : "don't catch");
1042         }
1043
1044         return ERROR_OK;
1045 }
1046
1047 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1048 {
1049         int retval;
1050         command_t *arm9tdmi_cmd;
1051
1052         retval = arm7_9_register_commands(cmd_ctx);
1053         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9",
1054                         NULL, COMMAND_ANY,
1055                         "arm9 specific commands");
1056         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
1057                         handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
1058                         "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ...");
1059
1060         return retval;
1061 }
1062