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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2008 by Hongtao Zheng                                   *
   9  *   hontor@126.com                                                        *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm9tdmi.h"
  31
  32
  33 #if 0
  34 #define _DEBUG_INSTRUCTION_EXECUTION_
  35 #endif
  36
  37 /* cli handling */
  38 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39
  40 /* forward declarations */
  41 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
  42
  43 int arm9tdmi_quit(void);
  44
  45 target_type_t arm9tdmi_target =
  46 {
  47         .name = "arm9tdmi",
  48
  49         .poll = arm7_9_poll,
  50         .arch_state = armv4_5_arch_state,
  51
  52         .target_request_data = arm7_9_target_request_data,
  53
  54         .halt = arm7_9_halt,
  55         .resume = arm7_9_resume,
  56         .step = arm7_9_step,
  57
  58         .assert_reset = arm7_9_assert_reset,
  59         .deassert_reset = arm7_9_deassert_reset,
  60         .soft_reset_halt = arm7_9_soft_reset_halt,
  61
  62         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  63
  64         .read_memory = arm7_9_read_memory,
  65         .write_memory = arm7_9_write_memory,
  66         .bulk_write_memory = arm7_9_bulk_write_memory,
  67         .checksum_memory = arm7_9_checksum_memory,
  68         .blank_check_memory = arm7_9_blank_check_memory,
  69
  70         .run_algorithm = armv4_5_run_algorithm,
  71
  72         .add_breakpoint = arm7_9_add_breakpoint,
  73         .remove_breakpoint = arm7_9_remove_breakpoint,
  74         .add_watchpoint = arm7_9_add_watchpoint,
  75         .remove_watchpoint = arm7_9_remove_watchpoint,
  76
  77         .register_commands = arm9tdmi_register_commands,
  78         .target_create = arm9tdmi_target_create,
  79         .init_target = arm9tdmi_init_target,
  80         .examine = arm9tdmi_examine,
  81         .quit = arm9tdmi_quit
  82 };
  83
  84 arm9tdmi_vector_t arm9tdmi_vectors[] =
  85 {
  86         {"reset", ARM9TDMI_RESET_VECTOR},
  87         {"undef", ARM9TDMI_UNDEF_VECTOR},
  88         {"swi", ARM9TDMI_SWI_VECTOR},
  89         {"pabt", ARM9TDMI_PABT_VECTOR},
  90         {"dabt", ARM9TDMI_DABT_VECTOR},
  91         {"reserved", ARM9TDMI_RESERVED_VECTOR},
  92         {"irq", ARM9TDMI_IRQ_VECTOR},
  93         {"fiq", ARM9TDMI_FIQ_VECTOR},
  94         {0, 0},
  95 };
  96
  97 int arm9tdmi_examine_debug_reason(target_t *target)
  98 {
  99         int retval = ERROR_OK;
 100         /* get pointers to arch-specific information */
 101         armv4_5_common_t *armv4_5 = target->arch_info;
 102         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 103
 104         /* only check the debug reason if we don't know it already */
 105         if ((target->debug_reason != DBG_REASON_DBGRQ)
 106                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 107         {
 108                 scan_field_t fields[3];
 109                 u8 databus[4];
 110                 u8 instructionbus[4];
 111                 u8 debug_reason;
 112
 113                 jtag_add_end_state(TAP_DRPAUSE);
 114
 115                 fields[0].tap = arm7_9->jtag_info.tap;
 116                 fields[0].num_bits = 32;
 117                 fields[0].out_value = NULL;
 118                 fields[0].in_value = databus;
 119
 120                 fields[1].tap = arm7_9->jtag_info.tap;
 121                 fields[1].num_bits = 3;
 122                 fields[1].out_value = NULL;
 123                 fields[1].in_value = &debug_reason;
 124
 125                 fields[2].tap = arm7_9->jtag_info.tap;
 126                 fields[2].num_bits = 32;
 127                 fields[2].out_value = NULL;
 128                 fields[2].in_value = instructionbus;
 129
 130                 if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 131                 {
 132                         return retval;
 133                 }
 134                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 135
 136                 jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
 137                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 138                 {
 139                         return retval;
 140                 }
 141
 142                 fields[0].in_value = NULL;
 143                 fields[0].out_value = databus;
 144                 fields[1].in_value = NULL;
 145                 fields[1].out_value = &debug_reason;
 146                 fields[2].in_value = NULL;
 147                 fields[2].out_value = instructionbus;
 148
 149                 jtag_add_dr_scan(3, fields, TAP_DRPAUSE);
 150
 151                 if (debug_reason & 0x4)
 152                         if (debug_reason & 0x2)
 153                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 154                 else
 155                         target->debug_reason = DBG_REASON_WATCHPOINT;
 156                 else
 157                         target->debug_reason = DBG_REASON_BREAKPOINT;
 158         }
 159
 160         return ERROR_OK;
 161 }
 162
 163 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 164 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 165 {
 166         int retval = ERROR_OK;
 167         scan_field_t fields[3];
 168         u8 out_buf[4];
 169         u8 instr_buf[4];
 170         u8 sysspeed_buf = 0x0;
 171
 172         /* prepare buffer */
 173         buf_set_u32(out_buf, 0, 32, out);
 174
 175         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 176
 177         if (sysspeed)
 178                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 179
 180         jtag_add_end_state(TAP_DRPAUSE);
 181         if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 182         {
 183                 return retval;
 184         }
 185
 186         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 187
 188         fields[0].tap = jtag_info->tap;
 189         fields[0].num_bits = 32;
 190         fields[0].out_value = out_buf;
 191         fields[0].in_value = NULL;
 192
 193         fields[1].tap = jtag_info->tap;
 194         fields[1].num_bits = 3;
 195         fields[1].out_value = &sysspeed_buf;
 196         fields[1].in_value = NULL;
 197
 198         fields[2].tap = jtag_info->tap;
 199         fields[2].num_bits = 32;
 200         fields[2].out_value = instr_buf;
 201         fields[2].in_value = NULL;
 202
 203         if (in)
 204         {
 205                 fields[0].in_value=(u8 *)in;
 206                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 207
 208                 jtag_add_callback(arm_le_to_h_u32, (u8 *)in);
 209         }
 210         else
 211         {
 212                 jtag_add_dr_scan(3, fields, TAP_INVALID);
 213         }
 214
 215         jtag_add_runtest(0, TAP_INVALID);
 216
 217 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 218         {
 219                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 220                 {
 221                         return retval;
 222                 }
 223
 224                 if (in)
 225                 {
 226                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 227                 }
 228                 else
 229                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 230         }
 231 #endif
 232
 233         return ERROR_OK;
 234 }
 235
 236 /* just read data (instruction and data-out = don't care) */
 237 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 238 {
 239         int retval = ERROR_OK;;
 240         scan_field_t fields[3];
 241
 242         jtag_add_end_state(TAP_DRPAUSE);
 243         if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 244         {
 245                 return retval;
 246         }
 247
 248         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 249
 250         fields[0].tap = jtag_info->tap;
 251         fields[0].num_bits = 32;
 252         fields[0].out_value = NULL;
 253         fields[0].in_value = (u8 *)in;
 254
 255         fields[1].tap = jtag_info->tap;
 256         fields[1].num_bits = 3;
 257         fields[1].out_value = NULL;
 258         fields[1].in_value = NULL;
 259
 260         fields[2].tap = jtag_info->tap;
 261         fields[2].num_bits = 32;
 262         fields[2].out_value = NULL;
 263         fields[2].in_value = NULL;
 264
 265         jtag_add_dr_scan(3, fields, TAP_INVALID);
 266
 267         jtag_add_callback(arm_le_to_h_u32, (u8 *)in);
 268
 269         jtag_add_runtest(0, TAP_INVALID);
 270
 271 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 272         {
 273                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 274                 {
 275                         return retval;
 276                 }
 277
 278                 if (in)
 279                 {
 280                         LOG_DEBUG("in: 0x%8.8x", *in);
 281                 }
 282                 else
 283                 {
 284                         LOG_ERROR("BUG: called with in == NULL");
 285                 }
 286         }
 287 #endif
 288
 289         return ERROR_OK;
 290 }
 291
 292 extern void arm_endianness(u8 *tmp, void *in, int size, int be, int flip);
 293
 294 static int arm9endianness(u8 *in, jtag_callback_data_t size, jtag_callback_data_t be, jtag_callback_data_t dummy)
 295 {
 296         arm_endianness(in, in, (int)size, (int)be, 0);
 297         return ERROR_OK;
 298 }
 299
 300 /* clock the target, and read the databus
 301  * the *in pointer points to a buffer where elements of 'size' bytes
 302  * are stored in big (be==1) or little (be==0) endianness
 303  */
 304 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 305 {
 306         int retval = ERROR_OK;
 307         scan_field_t fields[3];
 308
 309         jtag_add_end_state(TAP_DRPAUSE);
 310         if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 311         {
 312                 return retval;
 313         }
 314
 315         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 316
 317         fields[0].tap = jtag_info->tap;
 318         fields[0].num_bits = 32;
 319         fields[0].out_value = NULL;
 320         fields[0].in_value = (u8 *)in;
 321
 322         fields[1].tap = jtag_info->tap;
 323         fields[1].num_bits = 3;
 324         fields[1].out_value = NULL;
 325         fields[1].in_value = NULL;
 326
 327         fields[2].tap = jtag_info->tap;
 328         fields[2].num_bits = 32;
 329         fields[2].out_value = NULL;
 330         fields[2].in_value = NULL;
 331
 332         jtag_add_dr_scan(3, fields, TAP_INVALID);
 333
 334         jtag_add_callback4(arm9endianness, in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, 0);
 335
 336         jtag_add_runtest(0, TAP_INVALID);
 337
 338 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 339         {
 340                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 341                 {
 342                         return retval;
 343                 }
 344
 345                 if (in)
 346                 {
 347                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 348                 }
 349                 else
 350                 {
 351                         LOG_ERROR("BUG: called with in == NULL");
 352                 }
 353         }
 354 #endif
 355
 356         return ERROR_OK;
 357 }
 358
 359 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 360 {
 361         int retval = ERROR_OK;
 362         /* get pointers to arch-specific information */
 363         armv4_5_common_t *armv4_5 = target->arch_info;
 364         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 365         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 366
 367         /* save r0 before using it and put system in ARM state
 368          * to allow common handling of ARM and THUMB debugging */
 369
 370         /* fetch STR r0, [r0] */
 371         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 372         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 373         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 374         /* STR r0, [r0] in Memory */
 375         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 376
 377         /* MOV r0, r15 fetched, STR in Decode */
 378         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 379         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 380         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 381         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 382         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 383         /* nothing fetched, STR r0, [r0] in Memory */
 384         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 385
 386         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 387         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 388         /* LDR in Decode */
 389         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 390         /* LDR in Execute */
 391         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 392         /* LDR in Memory (to account for interlock) */
 393         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 394
 395         /* fetch BX */
 396         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 397         /* NOP fetched, BX in Decode, MOV in Execute */
 398         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 399         /* NOP fetched, BX in Execute (1) */
 400         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 401
 402         if ((retval = jtag_execute_queue()) != ERROR_OK)
 403         {
 404                 return;
 405         }
 406
 407         /* fix program counter:
 408          * MOV r0, r15 was the 5th instruction (+8)
 409          * reading PC in Thumb state gives address of instruction + 4
 410          */
 411         *pc -= 0xc;
 412 }
 413
 414 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 415 {
 416         int i;
 417         /* get pointers to arch-specific information */
 418         armv4_5_common_t *armv4_5 = target->arch_info;
 419         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 420         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 421
 422         /* STMIA r0-15, [r0] at debug speed
 423          * register values will start to appear on 4th DCLK
 424          */
 425         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 426
 427         /* fetch NOP, STM in DECODE stage */
 428         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 429         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 430         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 431
 432         for (i = 0; i <= 15; i++)
 433         {
 434                 if (mask & (1 << i))
 435                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 436                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 437         }
 438 }
 439
 440 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 441 {
 442         int i;
 443         /* get pointers to arch-specific information */
 444         armv4_5_common_t *armv4_5 = target->arch_info;
 445         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 446         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 447         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 448         u32 *buf_u32 = buffer;
 449         u16 *buf_u16 = buffer;
 450         u8 *buf_u8 = buffer;
 451
 452         /* STMIA r0-15, [r0] at debug speed
 453          * register values will start to appear on 4th DCLK
 454          */
 455         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 456
 457         /* fetch NOP, STM in DECODE stage */
 458         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 459         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 460         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 461
 462         for (i = 0; i <= 15; i++)
 463         {
 464                 if (mask & (1 << i))
 465                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 466                         switch (size)
 467                         {
 468                                 case 4:
 469                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 470                                         break;
 471                                 case 2:
 472                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 473                                         break;
 474                                 case 1:
 475                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 476                                         break;
 477                         }
 478         }
 479 }
 480
 481 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 482 {
 483         /* get pointers to arch-specific information */
 484         armv4_5_common_t *armv4_5 = target->arch_info;
 485         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 486         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 487
 488         /* MRS r0, cpsr */
 489         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 490         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 491         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 492         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 493         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 494
 495         /* STR r0, [r15] */
 496         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 497         /* fetch NOP, STR in DECODE stage */
 498         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 499         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 500         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 501         /* nothing fetched, STR in MEMORY */
 502         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 503 }
 504
 505 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 506 {
 507         /* get pointers to arch-specific information */
 508         armv4_5_common_t *armv4_5 = target->arch_info;
 509         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 510         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 511
 512         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 513
 514         /* MSR1 fetched */
 515         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 516         /* MSR2 fetched, MSR1 in DECODE */
 517         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 518         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 519         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 520         /* nothing fetched, MSR1 in EXECUTE (2) */
 521         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 522         /* nothing fetched, MSR1 in EXECUTE (3) */
 523         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 524         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 525         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 526         /* nothing fetched, MSR2 in EXECUTE (2) */
 527         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 528         /* nothing fetched, MSR2 in EXECUTE (3) */
 529         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 530         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 531         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 532         /* nothing fetched, MSR3 in EXECUTE (2) */
 533         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 534         /* nothing fetched, MSR3 in EXECUTE (3) */
 535         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 536         /* NOP fetched, MSR4 in EXECUTE (1) */
 537         /* last MSR writes flags, which takes only one cycle */
 538         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 539 }
 540
 541 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 542 {
 543         /* get pointers to arch-specific information */
 544         armv4_5_common_t *armv4_5 = target->arch_info;
 545         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 546         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 547
 548         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 549
 550         /* MSR fetched */
 551         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 552         /* NOP fetched, MSR in DECODE */
 553         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 554         /* NOP fetched, MSR in EXECUTE (1) */
 555         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 556
 557         /* rot == 4 writes flags, which takes only one cycle */
 558         if (rot != 4)
 559         {
 560                 /* nothing fetched, MSR in EXECUTE (2) */
 561                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 562                 /* nothing fetched, MSR in EXECUTE (3) */
 563                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 564         }
 565 }
 566
 567 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 568 {
 569         int i;
 570         /* get pointers to arch-specific information */
 571         armv4_5_common_t *armv4_5 = target->arch_info;
 572         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 573         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 574
 575         /* LDMIA r0-15, [r0] at debug speed
 576         * register values will start to appear on 4th DCLK
 577         */
 578         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 579
 580         /* fetch NOP, LDM in DECODE stage */
 581         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 582         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 583         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 584
 585         for (i = 0; i <= 15; i++)
 586         {
 587                 if (mask & (1 << i))
 588                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 589                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 590         }
 591         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 592 }
 593
 594 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 595 {
 596         /* get pointers to arch-specific information */
 597         armv4_5_common_t *armv4_5 = target->arch_info;
 598         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 599         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 600
 601         /* put system-speed load-multiple into the pipeline */
 602         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 603         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 604 }
 605
 606 void arm9tdmi_load_hword_reg(target_t *target, int num)
 607 {
 608         /* get pointers to arch-specific information */
 609         armv4_5_common_t *armv4_5 = target->arch_info;
 610         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 611         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 612
 613         /* put system-speed load half-word into the pipeline */
 614         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 615         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 616 }
 617
 618 void arm9tdmi_load_byte_reg(target_t *target, int num)
 619 {
 620         /* get pointers to arch-specific information */
 621         armv4_5_common_t *armv4_5 = target->arch_info;
 622         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 623         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 624
 625         /* put system-speed load byte into the pipeline */
 626         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 627         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 628 }
 629
 630 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 631 {
 632         /* get pointers to arch-specific information */
 633         armv4_5_common_t *armv4_5 = target->arch_info;
 634         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 635         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 636
 637         /* put system-speed store-multiple into the pipeline */
 638         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 639         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 640 }
 641
 642 void arm9tdmi_store_hword_reg(target_t *target, int num)
 643 {
 644         /* get pointers to arch-specific information */
 645         armv4_5_common_t *armv4_5 = target->arch_info;
 646         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 647         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 648
 649         /* put system-speed store half-word into the pipeline */
 650         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 651         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 652 }
 653
 654 void arm9tdmi_store_byte_reg(target_t *target, int num)
 655 {
 656         /* get pointers to arch-specific information */
 657         armv4_5_common_t *armv4_5 = target->arch_info;
 658         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 659         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 660
 661         /* put system-speed store byte into the pipeline */
 662         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 663         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 664 }
 665
 666 void arm9tdmi_write_pc(target_t *target, u32 pc)
 667 {
 668         /* get pointers to arch-specific information */
 669         armv4_5_common_t *armv4_5 = target->arch_info;
 670         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 671         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 672
 673         /* LDMIA r0-15, [r0] at debug speed
 674          * register values will start to appear on 4th DCLK
 675          */
 676         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 677
 678         /* fetch NOP, LDM in DECODE stage */
 679         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 680         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 681         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 682         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 683         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 684         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 685         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 686         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 687         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 688         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 689         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 690 }
 691
 692 void arm9tdmi_branch_resume(target_t *target)
 693 {
 694         /* get pointers to arch-specific information */
 695         armv4_5_common_t *armv4_5 = target->arch_info;
 696         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 697         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 698
 699         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 700         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 701 }
 702
 703 void arm9tdmi_branch_resume_thumb(target_t *target)
 704 {
 705         LOG_DEBUG("-");
 706
 707         /* get pointers to arch-specific information */
 708         armv4_5_common_t *armv4_5 = target->arch_info;
 709         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 710         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 711         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 712
 713         /* LDMIA r0-15, [r0] at debug speed
 714         * register values will start to appear on 4th DCLK
 715         */
 716         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 717
 718         /* fetch NOP, LDM in DECODE stage */
 719         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 720         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 721         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 722         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 723         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 724         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 725         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 726
 727         /* Branch and eXchange */
 728         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 729
 730         embeddedice_read_reg(dbg_stat);
 731
 732         /* fetch NOP, BX in DECODE stage */
 733         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 734
 735         embeddedice_read_reg(dbg_stat);
 736
 737         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 738         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 739
 740         /* target is now in Thumb state */
 741         embeddedice_read_reg(dbg_stat);
 742
 743         /* load r0 value, MOV_IM in Decode*/
 744         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 745         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 746         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 747         /* fetch NOP, LDR in Execute */
 748         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 749         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 750         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 751         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 752         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 753
 754         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 755         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 756
 757         embeddedice_read_reg(dbg_stat);
 758
 759         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 760         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 761 }
 762
 763 void arm9tdmi_enable_single_step(target_t *target, u32 next_pc)
 764 {
 765         /* get pointers to arch-specific information */
 766         armv4_5_common_t *armv4_5 = target->arch_info;
 767         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 768
 769         if (arm7_9->has_single_step)
 770         {
 771                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 772                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 773         }
 774         else
 775         {
 776                 arm7_9_enable_eice_step(target, next_pc);
 777         }
 778 }
 779
 780 void arm9tdmi_disable_single_step(target_t *target)
 781 {
 782         /* get pointers to arch-specific information */
 783         armv4_5_common_t *armv4_5 = target->arch_info;
 784         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 785
 786         if (arm7_9->has_single_step)
 787         {
 788                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 789                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 790         }
 791         else
 792         {
 793                 arm7_9_disable_eice_step(target);
 794         }
 795 }
 796
 797 void arm9tdmi_build_reg_cache(target_t *target)
 798 {
 799         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 800         /* get pointers to arch-specific information */
 801         armv4_5_common_t *armv4_5 = target->arch_info;
 802
 803         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 804         armv4_5->core_cache = (*cache_p);
 805 }
 806
 807 int arm9tdmi_examine(struct target_s *target)
 808 {
 809         /* get pointers to arch-specific information */
 810         int retval;
 811         armv4_5_common_t *armv4_5 = target->arch_info;
 812         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 813         if (!target->type->examined)
 814         {
 815                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 816                 reg_cache_t *t;
 817                 /* one extra register (vector catch) */
 818                 t=embeddedice_build_reg_cache(target, arm7_9);
 819                 if (t==NULL)
 820                         return ERROR_FAIL;
 821                 (*cache_p) = t;
 822                 arm7_9->eice_cache = (*cache_p);
 823
 824                 if (arm7_9->etm_ctx)
 825                 {
 826                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 827                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 828                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 829                 }
 830                 target->type->examined = 1;
 831         }
 832         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 833                 return retval;
 834         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 835                 return retval;
 836         if (arm7_9->etm_ctx)
 837         {
 838                 if ((retval=etm_setup(target))!=ERROR_OK)
 839                         return retval;
 840         }
 841         return ERROR_OK;
 842 }
 843
 844 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 845 {
 846
 847         arm9tdmi_build_reg_cache(target);
 848
 849         return ERROR_OK;
 850 }
 851
 852 int arm9tdmi_quit(void)
 853 {
 854         return ERROR_OK;
 855 }
 856
 857 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_tap_t *tap)
 858 {
 859         armv4_5_common_t *armv4_5;
 860         arm7_9_common_t *arm7_9;
 861
 862         arm7_9 = &arm9tdmi->arm7_9_common;
 863         armv4_5 = &arm7_9->armv4_5_common;
 864
 865         /* prepare JTAG information for the new target */
 866         arm7_9->jtag_info.tap = tap;
 867         arm7_9->jtag_info.scann_size = 5;
 868
 869         /* register arch-specific functions */
 870         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 871         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 872         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 873         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 874         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 875
 876         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 877         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 878         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 879
 880         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 881         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 882         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 883
 884         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 885         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 886         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 887
 888         arm7_9->write_pc = arm9tdmi_write_pc;
 889         arm7_9->branch_resume = arm9tdmi_branch_resume;
 890         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 891
 892         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 893         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 894
 895         arm7_9->pre_debug_entry = NULL;
 896         arm7_9->post_debug_entry = NULL;
 897
 898         arm7_9->pre_restore_context = NULL;
 899         arm7_9->post_restore_context = NULL;
 900
 901         /* initialize arch-specific breakpoint handling */
 902         arm7_9->arm_bkpt = 0xdeeedeee;
 903         arm7_9->thumb_bkpt = 0xdeee;
 904
 905         arm7_9->dbgreq_adjust_pc = 3;
 906         arm7_9->arch_info = arm9tdmi;
 907
 908         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 909         arm9tdmi->arch_info = NULL;
 910
 911         arm7_9_init_arch_info(target, arm7_9);
 912
 913         /* override use of DBGRQ, this is safe on ARM9TDMI */
 914         arm7_9->use_dbgrq = 1;
 915
 916         /* all ARM9s have the vector catch register */
 917         arm7_9->has_vector_catch = 1;
 918
 919         return ERROR_OK;
 920 }
 921
 922 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
 923 {
 924         armv4_5_common_t *armv4_5 = target->arch_info;
 925         arm7_9_common_t *arm7_9;
 926         arm9tdmi_common_t *arm9tdmi;
 927
 928         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 929         {
 930                 return -1;
 931         }
 932
 933         arm7_9 = armv4_5->arch_info;
 934         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 935         {
 936                 return -1;
 937         }
 938
 939         arm9tdmi = arm7_9->arch_info;
 940         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 941         {
 942                 return -1;
 943         }
 944
 945         *armv4_5_p = armv4_5;
 946         *arm7_9_p = arm7_9;
 947         *arm9tdmi_p = arm9tdmi;
 948
 949         return ERROR_OK;
 950 }
 951
 952 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
 953 {
 954         arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
 955
 956         arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
 957
 958         return ERROR_OK;
 959 }
 960
 961 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
 962 {
 963         int retval;
 964         command_t *arm9tdmi_cmd;
 965
 966         retval = arm7_9_register_commands(cmd_ctx);
 967         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
 968         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
 969
 970         return retval;
 971 }
 972
 973 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 974 {
 975         target_t *target = get_current_target(cmd_ctx);
 976         armv4_5_common_t *armv4_5;
 977         arm7_9_common_t *arm7_9;
 978         arm9tdmi_common_t *arm9tdmi;
 979         reg_t *vector_catch;
 980         u32 vector_catch_value;
 981         int i, j;
 982
 983         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
 984         {
 985                 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
 986                 return ERROR_OK;
 987         }
 988
 989         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
 990
 991         /* read the vector catch register if necessary */
 992         if (!vector_catch->valid)
 993                 embeddedice_read_reg(vector_catch);
 994
 995         /* get the current setting */
 996         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
 997
 998         if (argc > 0)
 999         {
1000                 vector_catch_value = 0x0;
1001                 if (strcmp(args[0], "all") == 0)
1002                 {
1003                         vector_catch_value = 0xdf;
1004                 }
1005                 else if (strcmp(args[0], "none") == 0)
1006                 {
1007                         /* do nothing */
1008                 }
1009                 else
1010                 {
1011                         for (i = 0; i < argc; i++)
1012                         {
1013                                 /* go through list of vectors */
1014                                 for (j = 0; arm9tdmi_vectors[j].name; j++)
1015                                 {
1016                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1017                                         {
1018                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1019                                                 break;
1020                                         }
1021                                 }
1022
1023                                 /* complain if vector wasn't found */
1024                                 if (!arm9tdmi_vectors[j].name)
1025                                 {
1026                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1027
1028                                         /* reread current setting */
1029                                         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1030
1031                                         break;
1032                                 }
1033                         }
1034                 }
1035
1036                 /* store new settings */
1037                 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1038                 embeddedice_store_reg(vector_catch);
1039         }
1040
1041         /* output current settings (skip RESERVED vector) */
1042         for (i = 0; i < 8; i++)
1043         {
1044                 if (i != 5)
1045                 {
1046                         command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1047                                 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1048                 }
1049         }
1050
1051         return ERROR_OK;
1052 }