1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
39 #define _DEBUG_INSTRUCTION_EXECUTION_
43 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
45 /* forward declarations */
46 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
47 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
50 target_type_t arm9tdmi_target =
55 .arch_state = armv4_5_arch_state,
58 .resume = arm7_9_resume,
61 .assert_reset = arm7_9_assert_reset,
62 .deassert_reset = arm7_9_deassert_reset,
63 .soft_reset_halt = arm7_9_soft_reset_halt,
65 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
67 .read_memory = arm7_9_read_memory,
68 .write_memory = arm7_9_write_memory,
69 .bulk_write_memory = arm7_9_bulk_write_memory,
71 .run_algorithm = armv4_5_run_algorithm,
73 .add_breakpoint = arm7_9_add_breakpoint,
74 .remove_breakpoint = arm7_9_remove_breakpoint,
75 .add_watchpoint = arm7_9_add_watchpoint,
76 .remove_watchpoint = arm7_9_remove_watchpoint,
78 .register_commands = arm9tdmi_register_commands,
79 .target_command = arm9tdmi_target_command,
80 .init_target = arm9tdmi_init_target,
84 int arm9tdmi_examine_debug_reason(target_t *target)
86 /* get pointers to arch-specific information */
87 armv4_5_common_t *armv4_5 = target->arch_info;
88 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
90 /* only check the debug reason if we don't know it already */
91 if ((target->debug_reason != DBG_REASON_DBGRQ)
92 && (target->debug_reason != DBG_REASON_SINGLESTEP))
94 scan_field_t fields[3];
99 jtag_add_end_state(TAP_PD);
101 fields[0].device = arm7_9->jtag_info.chain_pos;
102 fields[0].num_bits = 32;
103 fields[0].out_value = NULL;
104 fields[0].out_mask = NULL;
105 fields[0].in_value = databus;
106 fields[0].in_check_value = NULL;
107 fields[0].in_check_mask = NULL;
108 fields[0].in_handler = NULL;
109 fields[0].in_handler_priv = NULL;
111 fields[1].device = arm7_9->jtag_info.chain_pos;
112 fields[1].num_bits = 3;
113 fields[1].out_value = NULL;
114 fields[1].out_mask = NULL;
115 fields[1].in_value = &debug_reason;
116 fields[1].in_check_value = NULL;
117 fields[1].in_check_mask = NULL;
118 fields[1].in_handler = NULL;
119 fields[1].in_handler_priv = NULL;
121 fields[2].device = arm7_9->jtag_info.chain_pos;
122 fields[2].num_bits = 32;
123 fields[2].out_value = NULL;
124 fields[2].out_mask = NULL;
125 fields[2].in_value = instructionbus;
126 fields[2].in_check_value = NULL;
127 fields[2].in_check_mask = NULL;
128 fields[2].in_handler = NULL;
129 fields[2].in_handler_priv = NULL;
131 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
132 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
134 jtag_add_dr_scan(3, fields, TAP_PD);
135 jtag_execute_queue();
137 fields[0].in_value = NULL;
138 fields[0].out_value = databus;
139 fields[1].in_value = NULL;
140 fields[1].out_value = &debug_reason;
141 fields[2].in_value = NULL;
142 fields[2].out_value = instructionbus;
144 jtag_add_dr_scan(3, fields, TAP_PD);
146 if (debug_reason & 0x4)
147 if (debug_reason & 0x2)
148 target->debug_reason = DBG_REASON_WPTANDBKPT;
150 target->debug_reason = DBG_REASON_WATCHPOINT;
152 target->debug_reason = DBG_REASON_BREAKPOINT;
158 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
159 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
161 scan_field_t fields[3];
164 u8 sysspeed_buf = 0x0;
167 buf_set_u32(out_buf, 0, 32, out);
169 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
172 buf_set_u32(&sysspeed_buf, 2, 1, 1);
174 jtag_add_end_state(TAP_PD);
175 arm_jtag_scann(jtag_info, 0x1);
176 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
178 fields[0].device = jtag_info->chain_pos;
179 fields[0].num_bits = 32;
180 fields[0].out_value = out_buf;
181 fields[0].out_mask = NULL;
182 fields[0].in_value = NULL;
185 fields[0].in_handler = arm_jtag_buf_to_u32;
186 fields[0].in_handler_priv = in;
190 fields[0].in_handler = NULL;
191 fields[0].in_handler_priv = NULL;
193 fields[0].in_check_value = NULL;
194 fields[0].in_check_mask = NULL;
196 fields[1].device = jtag_info->chain_pos;
197 fields[1].num_bits = 3;
198 fields[1].out_value = &sysspeed_buf;
199 fields[1].out_mask = NULL;
200 fields[1].in_value = NULL;
201 fields[1].in_check_value = NULL;
202 fields[1].in_check_mask = NULL;
203 fields[1].in_handler = NULL;
204 fields[1].in_handler_priv = NULL;
206 fields[2].device = jtag_info->chain_pos;
207 fields[2].num_bits = 32;
208 fields[2].out_value = instr_buf;
209 fields[2].out_mask = NULL;
210 fields[2].in_value = NULL;
211 fields[2].in_check_value = NULL;
212 fields[2].in_check_mask = NULL;
213 fields[2].in_handler = NULL;
214 fields[2].in_handler_priv = NULL;
216 jtag_add_dr_scan(3, fields, -1);
218 jtag_add_runtest(0, -1);
220 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
222 jtag_execute_queue();
226 DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
229 DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
236 /* just read data (instruction and data-out = don't care) */
237 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
239 scan_field_t fields[3];
241 jtag_add_end_state(TAP_PD);
242 arm_jtag_scann(jtag_info, 0x1);
243 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
245 fields[0].device = jtag_info->chain_pos;
246 fields[0].num_bits = 32;
247 fields[0].out_value = NULL;
248 fields[0].out_mask = NULL;
249 fields[0].in_value = NULL;
250 fields[0].in_handler = arm_jtag_buf_to_u32;
251 fields[0].in_handler_priv = in;
252 fields[0].in_check_value = NULL;
253 fields[0].in_check_mask = NULL;
255 fields[1].device = jtag_info->chain_pos;
256 fields[1].num_bits = 3;
257 fields[1].out_value = NULL;
258 fields[1].out_mask = NULL;
259 fields[1].in_value = NULL;
260 fields[1].in_handler = NULL;
261 fields[1].in_handler_priv = NULL;
262 fields[1].in_check_value = NULL;
263 fields[1].in_check_mask = NULL;
265 fields[2].device = jtag_info->chain_pos;
266 fields[2].num_bits = 32;
267 fields[2].out_value = NULL;
268 fields[2].out_mask = NULL;
269 fields[2].in_value = NULL;
270 fields[2].in_check_value = NULL;
271 fields[2].in_check_mask = NULL;
272 fields[2].in_handler = NULL;
273 fields[2].in_handler_priv = NULL;
275 jtag_add_dr_scan(3, fields, -1);
277 jtag_add_runtest(0, -1);
279 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
281 jtag_execute_queue();
285 DEBUG("in: 0x%8.8x", *in);
289 ERROR("BUG: called with in == NULL");
297 /* clock the target, and read the databus
298 * the *in pointer points to a buffer where elements of 'size' bytes
299 * are stored in big (be==1) or little (be==0) endianness
301 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
303 scan_field_t fields[3];
305 jtag_add_end_state(TAP_PD);
306 arm_jtag_scann(jtag_info, 0x1);
307 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
309 fields[0].device = jtag_info->chain_pos;
310 fields[0].num_bits = 32;
311 fields[0].out_value = NULL;
312 fields[0].out_mask = NULL;
313 fields[0].in_value = NULL;
317 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
320 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
323 fields[0].in_handler = arm_jtag_buf_to_8;
326 fields[0].in_handler_priv = in;
327 fields[0].in_check_value = NULL;
328 fields[0].in_check_mask = NULL;
330 fields[1].device = jtag_info->chain_pos;
331 fields[1].num_bits = 3;
332 fields[1].out_value = NULL;
333 fields[1].out_mask = NULL;
334 fields[1].in_value = NULL;
335 fields[1].in_handler = NULL;
336 fields[1].in_handler_priv = NULL;
337 fields[1].in_check_value = NULL;
338 fields[1].in_check_mask = NULL;
340 fields[2].device = jtag_info->chain_pos;
341 fields[2].num_bits = 32;
342 fields[2].out_value = NULL;
343 fields[2].out_mask = NULL;
344 fields[2].in_value = NULL;
345 fields[2].in_check_value = NULL;
346 fields[2].in_check_mask = NULL;
347 fields[2].in_handler = NULL;
348 fields[2].in_handler_priv = NULL;
350 jtag_add_dr_scan(3, fields, -1);
352 jtag_add_runtest(0, -1);
354 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
356 jtag_execute_queue();
360 DEBUG("in: 0x%8.8x", *in);
364 ERROR("BUG: called with in == NULL");
372 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
374 /* get pointers to arch-specific information */
375 armv4_5_common_t *armv4_5 = target->arch_info;
376 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
377 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
379 /* save r0 before using it and put system in ARM state
380 * to allow common handling of ARM and THUMB debugging */
382 /* fetch STR r0, [r0] */
383 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
384 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
385 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
386 /* STR r0, [r0] in Memory */
387 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
389 /* MOV r0, r15 fetched, STR in Decode */
390 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
391 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
392 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
393 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
394 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
395 /* nothing fetched, STR r0, [r0] in Memory */
396 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
398 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
399 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
401 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
403 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
404 /* LDR in Memory (to account for interlock) */
405 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
408 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
409 /* NOP fetched, BX in Decode, MOV in Execute */
410 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
411 /* NOP fetched, BX in Execute (1) */
412 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
414 jtag_execute_queue();
416 /* fix program counter:
417 * MOV r0, r15 was the 5th instruction (+8)
418 * reading PC in Thumb state gives address of instruction + 4
423 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
426 /* get pointers to arch-specific information */
427 armv4_5_common_t *armv4_5 = target->arch_info;
428 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
429 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
431 /* STMIA r0-15, [r0] at debug speed
432 * register values will start to appear on 4th DCLK
434 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
436 /* fetch NOP, STM in DECODE stage */
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
438 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
439 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
441 for (i = 0; i <= 15; i++)
444 /* nothing fetched, STM in MEMORY (i'th cycle) */
445 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
450 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
453 /* get pointers to arch-specific information */
454 armv4_5_common_t *armv4_5 = target->arch_info;
455 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
456 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
457 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
458 u32 *buf_u32 = buffer;
459 u16 *buf_u16 = buffer;
462 /* STMIA r0-15, [r0] at debug speed
463 * register values will start to appear on 4th DCLK
465 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
467 /* fetch NOP, STM in DECODE stage */
468 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
469 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
470 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
472 for (i = 0; i <= 15; i++)
475 /* nothing fetched, STM in MEMORY (i'th cycle) */
479 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
482 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
485 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
492 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
494 /* get pointers to arch-specific information */
495 armv4_5_common_t *armv4_5 = target->arch_info;
496 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
497 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
500 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
501 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
502 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
503 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
504 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
507 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
508 /* fetch NOP, STR in DECODE stage */
509 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
510 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
511 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
512 /* nothing fetched, STR in MEMORY */
513 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
517 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
519 /* get pointers to arch-specific information */
520 armv4_5_common_t *armv4_5 = target->arch_info;
521 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
522 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
524 DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
528 /* MSR2 fetched, MSR1 in DECODE */
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
530 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
531 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
532 /* nothing fetched, MSR1 in EXECUTE (2) */
533 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
534 /* nothing fetched, MSR1 in EXECUTE (3) */
535 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
536 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
537 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
538 /* nothing fetched, MSR2 in EXECUTE (2) */
539 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
540 /* nothing fetched, MSR2 in EXECUTE (3) */
541 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
542 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
543 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
544 /* nothing fetched, MSR3 in EXECUTE (2) */
545 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
546 /* nothing fetched, MSR3 in EXECUTE (3) */
547 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
548 /* NOP fetched, MSR4 in EXECUTE (1) */
549 /* last MSR writes flags, which takes only one cycle */
550 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
553 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
555 /* get pointers to arch-specific information */
556 armv4_5_common_t *armv4_5 = target->arch_info;
557 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
558 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
560 DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
563 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
564 /* NOP fetched, MSR in DECODE */
565 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
566 /* NOP fetched, MSR in EXECUTE (1) */
567 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
569 /* rot == 4 writes flags, which takes only one cycle */
572 /* nothing fetched, MSR in EXECUTE (2) */
573 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
574 /* nothing fetched, MSR in EXECUTE (3) */
575 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
579 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
582 /* get pointers to arch-specific information */
583 armv4_5_common_t *armv4_5 = target->arch_info;
584 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
585 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
587 /* LDMIA r0-15, [r0] at debug speed
588 * register values will start to appear on 4th DCLK
590 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
592 /* fetch NOP, LDM in DECODE stage */
593 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
594 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
595 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
597 for (i = 0; i <= 15; i++)
600 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
601 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
603 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
607 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
609 /* get pointers to arch-specific information */
610 armv4_5_common_t *armv4_5 = target->arch_info;
611 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
612 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
614 /* put system-speed load-multiple into the pipeline */
615 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
616 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
620 void arm9tdmi_load_hword_reg(target_t *target, int num)
622 /* get pointers to arch-specific information */
623 armv4_5_common_t *armv4_5 = target->arch_info;
624 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
625 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
627 /* put system-speed load half-word into the pipeline */
628 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
629 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
632 void arm9tdmi_load_byte_reg(target_t *target, int num)
634 /* get pointers to arch-specific information */
635 armv4_5_common_t *armv4_5 = target->arch_info;
636 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
637 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
639 /* put system-speed load byte into the pipeline */
640 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
641 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
645 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
647 /* get pointers to arch-specific information */
648 armv4_5_common_t *armv4_5 = target->arch_info;
649 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
650 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
652 /* put system-speed store-multiple into the pipeline */
653 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
654 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
658 void arm9tdmi_store_hword_reg(target_t *target, int num)
660 /* get pointers to arch-specific information */
661 armv4_5_common_t *armv4_5 = target->arch_info;
662 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
663 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
665 /* put system-speed store half-word into the pipeline */
666 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
667 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
671 void arm9tdmi_store_byte_reg(target_t *target, int num)
673 /* get pointers to arch-specific information */
674 armv4_5_common_t *armv4_5 = target->arch_info;
675 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
676 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
678 /* put system-speed store byte into the pipeline */
679 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
680 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
684 void arm9tdmi_write_pc(target_t *target, u32 pc)
686 /* get pointers to arch-specific information */
687 armv4_5_common_t *armv4_5 = target->arch_info;
688 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
689 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
691 /* LDMIA r0-15, [r0] at debug speed
692 * register values will start to appear on 4th DCLK
694 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
696 /* fetch NOP, LDM in DECODE stage */
697 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
698 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
699 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
700 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
701 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
702 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
703 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
704 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
705 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
706 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
707 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
711 void arm9tdmi_branch_resume(target_t *target)
713 /* get pointers to arch-specific information */
714 armv4_5_common_t *armv4_5 = target->arch_info;
715 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
716 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
718 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
719 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
723 void arm9tdmi_branch_resume_thumb(target_t *target)
727 /* get pointers to arch-specific information */
728 armv4_5_common_t *armv4_5 = target->arch_info;
729 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
730 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
731 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
733 /* LDMIA r0-15, [r0] at debug speed
734 * register values will start to appear on 4th DCLK
736 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
738 /* fetch NOP, LDM in DECODE stage */
739 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
740 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
741 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
742 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
743 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
744 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
745 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
747 /* Branch and eXchange */
748 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
750 embeddedice_read_reg(dbg_stat);
752 /* fetch NOP, BX in DECODE stage */
753 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
755 embeddedice_read_reg(dbg_stat);
757 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
758 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
760 /* target is now in Thumb state */
761 embeddedice_read_reg(dbg_stat);
763 /* load r0 value, MOV_IM in Decode*/
764 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
765 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
767 /* fetch NOP, LDR in Execute */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
769 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
771 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
772 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
774 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
775 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
777 embeddedice_read_reg(dbg_stat);
779 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
780 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
784 void arm9tdmi_enable_single_step(target_t *target)
786 /* get pointers to arch-specific information */
787 armv4_5_common_t *armv4_5 = target->arch_info;
788 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
789 arm9tdmi_common_t *arm9 = arm7_9->arch_info;
791 if (arm7_9->has_single_step)
793 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
794 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
798 arm7_9_enable_eice_step(target);
802 void arm9tdmi_disable_single_step(target_t *target)
804 /* get pointers to arch-specific information */
805 armv4_5_common_t *armv4_5 = target->arch_info;
806 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
807 arm9tdmi_common_t *arm9 = arm7_9->arch_info;
809 if (arm7_9->has_single_step)
811 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
812 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
816 arm7_9_disable_eice_step(target);
820 void arm9tdmi_build_reg_cache(target_t *target)
822 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
823 /* get pointers to arch-specific information */
824 armv4_5_common_t *armv4_5 = target->arch_info;
825 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
826 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
827 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
829 embeddedice_reg_t *vec_catch_arch_info;
831 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
832 armv4_5->core_cache = (*cache_p);
834 /* one extra register (vector catch) */
835 (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
836 arm7_9->eice_cache = (*cache_p)->next;
839 (*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
840 (*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
841 (*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
842 (*cache_p)->next->reg_list[EICE_VEC_CATCH].bitfield_desc = NULL;
843 (*cache_p)->next->reg_list[EICE_VEC_CATCH].num_bitfields = 0;
844 (*cache_p)->next->reg_list[EICE_VEC_CATCH].size = 8;
845 (*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
846 vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
847 vec_catch_arch_info->addr = 0x2;
851 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
854 arm9tdmi_build_reg_cache(target);
866 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
868 armv4_5_common_t *armv4_5;
869 arm7_9_common_t *arm7_9;
871 arm7_9 = &arm9tdmi->arm7_9_common;
872 armv4_5 = &arm7_9->armv4_5_common;
874 /* prepare JTAG information for the new target */
875 arm7_9->jtag_info.chain_pos = chain_pos;
876 arm7_9->jtag_info.scann_size = 5;
878 /* register arch-specific functions */
879 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
880 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
881 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
882 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
883 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
885 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
886 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
887 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
889 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
890 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
891 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
893 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
894 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
895 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
897 arm7_9->write_pc = arm9tdmi_write_pc;
898 arm7_9->branch_resume = arm9tdmi_branch_resume;
899 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
901 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
902 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
904 arm7_9->pre_debug_entry = NULL;
905 arm7_9->post_debug_entry = NULL;
907 arm7_9->pre_restore_context = NULL;
908 arm7_9->post_restore_context = NULL;
910 /* initialize arch-specific breakpoint handling */
911 buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
912 buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
914 arm7_9->sw_bkpts_use_wp = 1;
915 arm7_9->sw_bkpts_enabled = 0;
916 arm7_9->dbgreq_adjust_pc = 3;
917 arm7_9->arch_info = arm9tdmi;
919 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
920 arm9tdmi->arch_info = NULL;
924 arm9tdmi->variant = strdup(variant);
928 arm9tdmi->variant = strdup("");
931 arm7_9_init_arch_info(target, arm7_9);
933 /* override use of DBGRQ, this is safe on ARM9TDMI */
934 arm7_9->use_dbgrq = 1;
936 /* all ARM9s have the vector catch register */
937 arm7_9->has_vector_catch = 1;
942 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
943 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
946 char *variant = NULL;
947 arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
951 ERROR("'target arm9tdmi' requires at least one additional argument");
955 chain_pos = strtoul(args[3], NULL, 0);
960 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
965 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
969 retval = arm7_9_register_commands(cmd_ctx);