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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm9tdmi.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "log.h"
  32 #include "jtag.h"
  33 #include "arm_jtag.h"
  34
  35 #include <stdlib.h>
  36 #include <string.h>
  37
  38 #if 0
  39 #define _DEBUG_INSTRUCTION_EXECUTION_
  40 #endif
  41
  42 /* cli handling */
  43 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
  44
  45 /* forward declarations */
  46 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  47 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  48 int arm9tdmi_quit();
  49
  50 target_type_t arm9tdmi_target =
  51 {
  52         .name = "arm9tdmi",
  53
  54         .poll = arm7_9_poll,
  55         .arch_state = armv4_5_arch_state,
  56
  57         .halt = arm7_9_halt,
  58         .resume = arm7_9_resume,
  59         .step = arm7_9_step,
  60
  61         .assert_reset = arm7_9_assert_reset,
  62         .deassert_reset = arm7_9_deassert_reset,
  63         .soft_reset_halt = arm7_9_soft_reset_halt,
  64
  65         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  66
  67         .read_memory = arm7_9_read_memory,
  68         .write_memory = arm7_9_write_memory,
  69         .bulk_write_memory = arm7_9_bulk_write_memory,
  70
  71         .add_breakpoint = arm7_9_add_breakpoint,
  72         .remove_breakpoint = arm7_9_remove_breakpoint,
  73         .add_watchpoint = arm7_9_add_watchpoint,
  74         .remove_watchpoint = arm7_9_remove_watchpoint,
  75
  76         .register_commands = arm9tdmi_register_commands,
  77         .target_command = arm9tdmi_target_command,
  78         .init_target = arm9tdmi_init_target,
  79         .quit = arm9tdmi_quit
  80 };
  81
  82 int arm9tdmi_examine_debug_reason(target_t *target)
  83 {
  84         /* get pointers to arch-specific information */
  85         armv4_5_common_t *armv4_5 = target->arch_info;
  86         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
  87
  88         /* only check the debug reason if we don't know it already */
  89         if ((target->debug_reason != DBG_REASON_DBGRQ)
  90                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
  91         {
  92                 scan_field_t fields[3];
  93                 u8 databus[4];
  94                 u8 instructionbus[4];
  95                 u8 debug_reason;
  96
  97                 jtag_add_end_state(TAP_PD);
  98
  99                 fields[0].device = arm7_9->jtag_info.chain_pos;
 100                 fields[0].num_bits = 32;
 101                 fields[0].out_value = NULL;
 102                 fields[0].out_mask = NULL;
 103                 fields[0].in_value = databus;
 104                 fields[0].in_check_value = NULL;
 105                 fields[0].in_check_mask = NULL;
 106                 fields[0].in_handler = NULL;
 107                 fields[0].in_handler_priv = NULL;
 108
 109                 fields[1].device = arm7_9->jtag_info.chain_pos;
 110                 fields[1].num_bits = 3;
 111                 fields[1].out_value = NULL;
 112                 fields[1].out_mask = NULL;
 113                 fields[1].in_value = &debug_reason;
 114                 fields[1].in_check_value = NULL;
 115                 fields[1].in_check_mask = NULL;
 116                 fields[1].in_handler = NULL;
 117                 fields[1].in_handler_priv = NULL;
 118
 119                 fields[2].device = arm7_9->jtag_info.chain_pos;
 120                 fields[2].num_bits = 32;
 121                 fields[2].out_value = NULL;
 122                 fields[2].out_mask = NULL;
 123                 fields[2].in_value = instructionbus;
 124                 fields[2].in_check_value = NULL;
 125                 fields[2].in_check_mask = NULL;
 126                 fields[2].in_handler = NULL;
 127                 fields[2].in_handler_priv = NULL;
 128
 129                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
 131
 132                 jtag_add_dr_scan(3, fields, TAP_PD);
 133                 jtag_execute_queue();
 134
 135                 fields[0].in_value = NULL;
 136                 fields[0].out_value = databus;
 137                 fields[1].in_value = NULL;
 138                 fields[1].out_value = &debug_reason;
 139                 fields[2].in_value = NULL;
 140                 fields[2].out_value = instructionbus;
 141
 142                 jtag_add_dr_scan(3, fields, TAP_PD);
 143
 144                 if (debug_reason & 0x4)
 145                         if (debug_reason & 0x2)
 146                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 147                 else
 148                         target->debug_reason = DBG_REASON_WATCHPOINT;
 149                 else
 150                         target->debug_reason = DBG_REASON_BREAKPOINT;
 151         }
 152
 153         return ERROR_OK;
 154 }
 155
 156 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 157 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 158 {
 159         scan_field_t fields[3];
 160         u8 out_buf[4];
 161         u8 instr_buf[4];
 162         u8 sysspeed_buf = 0x0;
 163
 164         /* prepare buffer */
 165         buf_set_u32(out_buf, 0, 32, out);
 166
 167         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 168
 169         if (sysspeed)
 170                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 171
 172         jtag_add_end_state(TAP_PD);
 173         arm_jtag_scann(jtag_info, 0x1);
 174         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 175
 176         fields[0].device = jtag_info->chain_pos;
 177         fields[0].num_bits = 32;
 178         fields[0].out_value = out_buf;
 179         fields[0].out_mask = NULL;
 180         fields[0].in_value = NULL;
 181         if (in)
 182         {
 183                 fields[0].in_handler = arm_jtag_buf_to_u32;
 184                 fields[0].in_handler_priv = in;
 185         }
 186         else
 187         {
 188                 fields[0].in_handler = NULL;
 189                 fields[0].in_handler_priv = NULL;
 190         }
 191         fields[0].in_check_value = NULL;
 192         fields[0].in_check_mask = NULL;
 193
 194         fields[1].device = jtag_info->chain_pos;
 195         fields[1].num_bits = 3;
 196         fields[1].out_value = &sysspeed_buf;
 197         fields[1].out_mask = NULL;
 198         fields[1].in_value = NULL;
 199         fields[1].in_check_value = NULL;
 200         fields[1].in_check_mask = NULL;
 201         fields[1].in_handler = NULL;
 202         fields[1].in_handler_priv = NULL;
 203
 204         fields[2].device = jtag_info->chain_pos;
 205         fields[2].num_bits = 32;
 206         fields[2].out_value = instr_buf;
 207         fields[2].out_mask = NULL;
 208         fields[2].in_value = NULL;
 209         fields[2].in_check_value = NULL;
 210         fields[2].in_check_mask = NULL;
 211         fields[2].in_handler = NULL;
 212         fields[2].in_handler_priv = NULL;
 213
 214         jtag_add_dr_scan(3, fields, -1);
 215
 216         jtag_add_runtest(0, -1);
 217
 218 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 219         {
 220                 jtag_execute_queue();
 221
 222                 if (in)
 223                 {
 224                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 225                 }
 226                 else
 227                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 228         }
 229 #endif
 230
 231         return ERROR_OK;
 232 }
 233
 234 /* just read data (instruction and data-out = don't care) */
 235 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 236 {
 237         scan_field_t fields[3];
 238
 239         jtag_add_end_state(TAP_PD);
 240         arm_jtag_scann(jtag_info, 0x1);
 241         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 242
 243         fields[0].device = jtag_info->chain_pos;
 244         fields[0].num_bits = 32;
 245         fields[0].out_value = NULL;
 246         fields[0].out_mask = NULL;
 247         fields[0].in_value = NULL;
 248         fields[0].in_handler = arm_jtag_buf_to_u32;
 249         fields[0].in_handler_priv = in;
 250         fields[0].in_check_value = NULL;
 251         fields[0].in_check_mask = NULL;
 252
 253         fields[1].device = jtag_info->chain_pos;
 254         fields[1].num_bits = 3;
 255         fields[1].out_value = NULL;
 256         fields[1].out_mask = NULL;
 257         fields[1].in_value = NULL;
 258         fields[1].in_handler = NULL;
 259         fields[1].in_handler_priv = NULL;
 260         fields[1].in_check_value = NULL;
 261         fields[1].in_check_mask = NULL;
 262
 263         fields[2].device = jtag_info->chain_pos;
 264         fields[2].num_bits = 32;
 265         fields[2].out_value = NULL;
 266         fields[2].out_mask = NULL;
 267         fields[2].in_value = NULL;
 268         fields[2].in_check_value = NULL;
 269         fields[2].in_check_mask = NULL;
 270         fields[2].in_handler = NULL;
 271         fields[2].in_handler_priv = NULL;
 272
 273         jtag_add_dr_scan(3, fields, -1);
 274
 275         jtag_add_runtest(0, -1);
 276
 277 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 278         {
 279                 jtag_execute_queue();
 280
 281                 if (in)
 282                 {
 283                         DEBUG("in: 0x%8.8x", *in);
 284                 }
 285                 else
 286                 {
 287                         ERROR("BUG: called with in == NULL");
 288                 }
 289         }
 290 #endif
 291
 292         return ERROR_OK;
 293 }
 294
 295 /* clock the target, and read the databus
 296  * the *in pointer points to a buffer where elements of 'size' bytes
 297  * are stored in big (be==1) or little (be==0) endianness
 298  */
 299 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 300 {
 301         scan_field_t fields[3];
 302
 303         jtag_add_end_state(TAP_PD);
 304         arm_jtag_scann(jtag_info, 0x1);
 305         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 306
 307         fields[0].device = jtag_info->chain_pos;
 308         fields[0].num_bits = 32;
 309         fields[0].out_value = NULL;
 310         fields[0].out_mask = NULL;
 311         fields[0].in_value = NULL;
 312         switch (size)
 313         {
 314                 case 4:
 315                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
 316                         break;
 317                 case 2:
 318                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
 319                         break;
 320                 case 1:
 321                         fields[0].in_handler = arm_jtag_buf_to_8;
 322                         break;
 323         }
 324         fields[0].in_handler_priv = in;
 325         fields[0].in_check_value = NULL;
 326         fields[0].in_check_mask = NULL;
 327
 328         fields[1].device = jtag_info->chain_pos;
 329         fields[1].num_bits = 3;
 330         fields[1].out_value = NULL;
 331         fields[1].out_mask = NULL;
 332         fields[1].in_value = NULL;
 333         fields[1].in_handler = NULL;
 334         fields[1].in_handler_priv = NULL;
 335         fields[1].in_check_value = NULL;
 336         fields[1].in_check_mask = NULL;
 337
 338         fields[2].device = jtag_info->chain_pos;
 339         fields[2].num_bits = 32;
 340         fields[2].out_value = NULL;
 341         fields[2].out_mask = NULL;
 342         fields[2].in_value = NULL;
 343         fields[2].in_check_value = NULL;
 344         fields[2].in_check_mask = NULL;
 345         fields[2].in_handler = NULL;
 346         fields[2].in_handler_priv = NULL;
 347
 348         jtag_add_dr_scan(3, fields, -1);
 349
 350         jtag_add_runtest(0, -1);
 351
 352 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 353         {
 354                 jtag_execute_queue();
 355
 356                 if (in)
 357                 {
 358                         DEBUG("in: 0x%8.8x", *in);
 359                 }
 360                 else
 361                 {
 362                         ERROR("BUG: called with in == NULL");
 363                 }
 364         }
 365 #endif
 366
 367         return ERROR_OK;
 368 }
 369
 370 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 371 {
 372         /* get pointers to arch-specific information */
 373         armv4_5_common_t *armv4_5 = target->arch_info;
 374         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 375         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 376
 377         /* save r0 before using it and put system in ARM state
 378          * to allow common handling of ARM and THUMB debugging */
 379
 380         /* fetch STR r0, [r0] */
 381         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 382         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 383         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 384         /* STR r0, [r0] in Memory */
 385         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 386
 387         /* MOV r0, r15 fetched, STR in Decode */
 388         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 389         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 390         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 391         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 392         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 393         /* nothing fetched, STR r0, [r0] in Memory */
 394         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 395
 396         /* fetch MOV */
 397         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), 0, NULL, 0);
 398         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 399         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 400
 401         /* fetch BX */
 402         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 403         /* NOP fetched, BX in Decode, MOV in Execute */
 404         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 405         /* NOP fetched, BX in Execute (1) */
 406         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 407
 408         jtag_execute_queue();
 409
 410         /* fix program counter:
 411          * MOV r0, r15 was the 5th instruction (+8)
 412          * reading PC in Thumb state gives address of instruction + 4
 413          */
 414         *pc -= 0xc;
 415 }
 416
 417 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 418 {
 419         int i;
 420         /* get pointers to arch-specific information */
 421         armv4_5_common_t *armv4_5 = target->arch_info;
 422         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 423         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 424
 425         /* STMIA r0-15, [r0] at debug speed
 426          * register values will start to appear on 4th DCLK
 427          */
 428         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 429
 430         /* fetch NOP, STM in DECODE stage */
 431         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 432         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 433         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 434
 435         for (i = 0; i <= 15; i++)
 436         {
 437                 if (mask & (1 << i))
 438                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 439                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 440         }
 441
 442 }
 443
 444 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 445 {
 446         int i;
 447         /* get pointers to arch-specific information */
 448         armv4_5_common_t *armv4_5 = target->arch_info;
 449         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 450         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 451         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 452         u32 *buf_u32 = buffer;
 453         u16 *buf_u16 = buffer;
 454         u8 *buf_u8 = buffer;
 455
 456         /* STMIA r0-15, [r0] at debug speed
 457          * register values will start to appear on 4th DCLK
 458          */
 459         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 460
 461         /* fetch NOP, STM in DECODE stage */
 462         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 463         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 464         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 465
 466         for (i = 0; i <= 15; i++)
 467         {
 468                 if (mask & (1 << i))
 469                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 470                         switch (size)
 471                         {
 472                                 case 4:
 473                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 474                                         break;
 475                                 case 2:
 476                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 477                                         break;
 478                                 case 1:
 479                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 480                                         break;
 481                         }
 482         }
 483
 484 }
 485
 486 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 487 {
 488         /* get pointers to arch-specific information */
 489         armv4_5_common_t *armv4_5 = target->arch_info;
 490         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 491         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 492
 493         /* MRS r0, cpsr */
 494         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 495         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 496         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 497         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 498         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 499
 500         /* STR r0, [r15] */
 501         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 502         /* fetch NOP, STR in DECODE stage */
 503         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 504         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 505         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 506         /* nothing fetched, STR in MEMORY */
 507         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 508
 509 }
 510
 511 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 512 {
 513         /* get pointers to arch-specific information */
 514         armv4_5_common_t *armv4_5 = target->arch_info;
 515         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 516         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 517
 518         DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 519
 520         /* MSR1 fetched */
 521         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 522         /* MSR2 fetched, MSR1 in DECODE */
 523         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 524         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 525         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 526         /* nothing fetched, MSR1 in EXECUTE (2) */
 527         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 528         /* nothing fetched, MSR1 in EXECUTE (3) */
 529         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 530         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 531         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 532         /* nothing fetched, MSR2 in EXECUTE (2) */
 533         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 534         /* nothing fetched, MSR2 in EXECUTE (3) */
 535         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 536         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 537         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 538         /* nothing fetched, MSR3 in EXECUTE (2) */
 539         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 540         /* nothing fetched, MSR3 in EXECUTE (3) */
 541         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 542         /* NOP fetched, MSR4 in EXECUTE (1) */
 543         /* last MSR writes flags, which takes only one cycle */
 544         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 545 }
 546
 547 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 548 {
 549         /* get pointers to arch-specific information */
 550         armv4_5_common_t *armv4_5 = target->arch_info;
 551         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 552         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 553
 554         DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 555
 556         /* MSR fetched */
 557         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 558         /* NOP fetched, MSR in DECODE */
 559         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 560         /* NOP fetched, MSR in EXECUTE (1) */
 561         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 562
 563         /* rot == 4 writes flags, which takes only one cycle */
 564         if (rot != 4)
 565         {
 566                 /* nothing fetched, MSR in EXECUTE (2) */
 567                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 568                 /* nothing fetched, MSR in EXECUTE (3) */
 569                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 570         }
 571 }
 572
 573 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 574 {
 575         int i;
 576         /* get pointers to arch-specific information */
 577         armv4_5_common_t *armv4_5 = target->arch_info;
 578         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 579         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 580
 581         /* LDMIA r0-15, [r0] at debug speed
 582         * register values will start to appear on 4th DCLK
 583         */
 584         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 585
 586         /* fetch NOP, LDM in DECODE stage */
 587         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 588         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 589         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 590
 591         for (i = 0; i <= 15; i++)
 592         {
 593                 if (mask & (1 << i))
 594                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 595                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 596         }
 597         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 598
 599 }
 600
 601 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 602 {
 603         /* get pointers to arch-specific information */
 604         armv4_5_common_t *armv4_5 = target->arch_info;
 605         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 606         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 607
 608         /* put system-speed load-multiple into the pipeline */
 609         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 610         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 611
 612 }
 613
 614 void arm9tdmi_load_hword_reg(target_t *target, int num)
 615 {
 616         /* get pointers to arch-specific information */
 617         armv4_5_common_t *armv4_5 = target->arch_info;
 618         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 619         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 620
 621         /* put system-speed load half-word into the pipeline */
 622         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 623         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 624 }
 625
 626 void arm9tdmi_load_byte_reg(target_t *target, int num)
 627 {
 628         /* get pointers to arch-specific information */
 629         armv4_5_common_t *armv4_5 = target->arch_info;
 630         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 631         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 632
 633         /* put system-speed load byte into the pipeline */
 634         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 635         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 636
 637 }
 638
 639 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 640 {
 641         /* get pointers to arch-specific information */
 642         armv4_5_common_t *armv4_5 = target->arch_info;
 643         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 644         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 645
 646         /* put system-speed store-multiple into the pipeline */
 647         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 648         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 649
 650 }
 651
 652 void arm9tdmi_store_hword_reg(target_t *target, int num)
 653 {
 654         /* get pointers to arch-specific information */
 655         armv4_5_common_t *armv4_5 = target->arch_info;
 656         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 657         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 658
 659         /* put system-speed store half-word into the pipeline */
 660         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 661         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 662
 663 }
 664
 665 void arm9tdmi_store_byte_reg(target_t *target, int num)
 666 {
 667         /* get pointers to arch-specific information */
 668         armv4_5_common_t *armv4_5 = target->arch_info;
 669         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 670         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 671
 672         /* put system-speed store byte into the pipeline */
 673         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 674         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 675
 676 }
 677
 678 void arm9tdmi_write_pc(target_t *target, u32 pc)
 679 {
 680         /* get pointers to arch-specific information */
 681         armv4_5_common_t *armv4_5 = target->arch_info;
 682         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 683         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 684
 685         /* LDMIA r0-15, [r0] at debug speed
 686          * register values will start to appear on 4th DCLK
 687          */
 688         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 689
 690         /* fetch NOP, LDM in DECODE stage */
 691         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 692         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 693         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 694         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 695         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 696         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 697         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 698         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 699         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 700         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 701         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 702
 703 }
 704
 705 void arm9tdmi_branch_resume(target_t *target)
 706 {
 707         /* get pointers to arch-specific information */
 708         armv4_5_common_t *armv4_5 = target->arch_info;
 709         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 710         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 711
 712         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 713         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 714
 715 }
 716
 717 void arm9tdmi_branch_resume_thumb(target_t *target)
 718 {
 719         DEBUG("");
 720
 721         /* get pointers to arch-specific information */
 722         armv4_5_common_t *armv4_5 = target->arch_info;
 723         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 724         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 725         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 726
 727         /* LDMIA r0-15, [r0] at debug speed
 728         * register values will start to appear on 4th DCLK
 729         */
 730         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 731
 732         /* fetch NOP, LDM in DECODE stage */
 733         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 734         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 735         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 736         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 737         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 738         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 739         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 740
 741         /* Branch and eXchange */
 742         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 743
 744         embeddedice_read_reg(dbg_stat);
 745
 746         /* fetch NOP, BX in DECODE stage */
 747         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 748
 749         embeddedice_read_reg(dbg_stat);
 750
 751         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 752         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 753
 754         /* target is now in Thumb state */
 755         embeddedice_read_reg(dbg_stat);
 756
 757         /* clean r0 bits to avoid alignment problems */
 758         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV_IM(0, 0x0), 0, NULL, 0);
 759         /* load r0 value, MOV_IM in Decode*/
 760         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR(0, 0), 0, NULL, 0);
 761         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 762         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 763         /* fetch NOP, LDR in Execute */
 764         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 765         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 766         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 767         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 768         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 769
 770         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 771         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 772
 773         embeddedice_read_reg(dbg_stat);
 774
 775         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f6), 0, NULL, 1);
 776         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 777
 778 }
 779
 780 void arm9tdmi_enable_single_step(target_t *target)
 781 {
 782         /* get pointers to arch-specific information */
 783         armv4_5_common_t *armv4_5 = target->arch_info;
 784         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 785         arm9tdmi_common_t *arm9 = arm7_9->arch_info;
 786
 787         if (arm9->has_single_step)
 788         {
 789                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 790                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 791         }
 792         else
 793         {
 794                 arm7_9_enable_eice_step(target);
 795         }
 796 }
 797
 798 void arm9tdmi_disable_single_step(target_t *target)
 799 {
 800         /* get pointers to arch-specific information */
 801         armv4_5_common_t *armv4_5 = target->arch_info;
 802         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 803         arm9tdmi_common_t *arm9 = arm7_9->arch_info;
 804
 805         if (arm9->has_single_step)
 806         {
 807                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 808                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 809         }
 810         else
 811         {
 812                 arm7_9_disable_eice_step(target);
 813         }
 814 }
 815
 816 void arm9tdmi_build_reg_cache(target_t *target)
 817 {
 818         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 819         /* get pointers to arch-specific information */
 820         armv4_5_common_t *armv4_5 = target->arch_info;
 821         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 822         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 823         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 824
 825         embeddedice_reg_t *vec_catch_arch_info;
 826
 827         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 828         armv4_5->core_cache = (*cache_p);
 829
 830         /* one extra register (vector catch) */
 831         (*cache_p)->next = embeddedice_build_reg_cache(target, jtag_info, 1);
 832         arm7_9->eice_cache = (*cache_p)->next;
 833
 834         if (arm9tdmi->has_monitor_mode)
 835                 (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 6;
 836         else
 837                 (*cache_p)->next->reg_list[EICE_DBG_CTRL].size = 4;
 838
 839         (*cache_p)->next->reg_list[EICE_DBG_STAT].size = 5;
 840
 841         (*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
 842         (*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
 843         (*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
 844         (*cache_p)->next->reg_list[EICE_VEC_CATCH].bitfield_desc = NULL;
 845         (*cache_p)->next->reg_list[EICE_VEC_CATCH].num_bitfields = 0;
 846         (*cache_p)->next->reg_list[EICE_VEC_CATCH].size = 8;
 847         (*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
 848         vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
 849         vec_catch_arch_info->addr = 0x2;
 850
 851 }
 852
 853 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 854 {
 855
 856         arm9tdmi_build_reg_cache(target);
 857
 858         return ERROR_OK;
 859
 860 }
 861
 862 int arm9tdmi_quit()
 863 {
 864
 865         return ERROR_OK;
 866 }
 867
 868 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
 869 {
 870         armv4_5_common_t *armv4_5;
 871         arm7_9_common_t *arm7_9;
 872
 873         arm7_9 = &arm9tdmi->arm7_9_common;
 874         armv4_5 = &arm7_9->armv4_5_common;
 875
 876         /* prepare JTAG information for the new target */
 877         arm7_9->jtag_info.chain_pos = chain_pos;
 878         arm7_9->jtag_info.scann_size = 5;
 879
 880         /* register arch-specific functions */
 881         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 882         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 883         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 884         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 885         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 886
 887         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 888         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 889         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 890
 891         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 892         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 893         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 894
 895         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 896         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 897         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 898
 899         arm7_9->write_pc = arm9tdmi_write_pc;
 900         arm7_9->branch_resume = arm9tdmi_branch_resume;
 901         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 902
 903         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 904         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 905
 906         arm7_9->pre_debug_entry = NULL;
 907         arm7_9->post_debug_entry = NULL;
 908
 909         arm7_9->pre_restore_context = NULL;
 910         arm7_9->post_restore_context = NULL;
 911
 912         /* initialize arch-specific breakpoint handling */
 913         buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
 914         buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
 915
 916         arm7_9->sw_bkpts_use_wp = 1;
 917         arm7_9->sw_bkpts_enabled = 0;
 918         arm7_9->dbgreq_adjust_pc = 3;
 919         arm7_9->arch_info = arm9tdmi;
 920
 921         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 922         arm9tdmi->has_monitor_mode = 0;
 923         arm9tdmi->has_single_step = 0;
 924         arm9tdmi->arch_info = NULL;
 925
 926         if (variant)
 927         {
 928                 if (strcmp(variant, "arm920t") == 0)
 929                         arm9tdmi->has_single_step = 1;
 930                 else if (strcmp(variant, "arm922t") == 0)
 931                         arm9tdmi->has_single_step = 1;
 932                 else if (strcmp(variant, "arm940t") == 0)
 933                         arm9tdmi->has_single_step = 1;
 934                 arm9tdmi->variant = strdup(variant);
 935         }
 936         else
 937                 arm9tdmi->variant = strdup("");
 938
 939         arm7_9_init_arch_info(target, arm7_9);
 940
 941         /* override use of DBGRQ, this is safe on ARM9TDMI */
 942         arm7_9->use_dbgrq = 1;
 943
 944         return ERROR_OK;
 945 }
 946
 947 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
 948 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 949 {
 950         int chain_pos;
 951         char *variant = NULL;
 952         arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
 953
 954         if (argc < 4)
 955         {
 956                 ERROR("'target arm9tdmi' requires at least one additional argument");
 957                 exit(-1);
 958         }
 959
 960         chain_pos = strtoul(args[3], NULL, 0);
 961
 962         if (argc >= 5)
 963                 variant = args[4];
 964
 965         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 966
 967         return ERROR_OK;
 968 }
 969
 970 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
 971 {
 972         int retval;
 973
 974         retval = arm7_9_register_commands(cmd_ctx);
 975
 976         return ERROR_OK;
 977
 978 }
 979