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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm9tdmi.h"
  25
  26 #include "arm7_9_common.h"
  27 #include "register.h"
  28 #include "target.h"
  29 #include "armv4_5.h"
  30 #include "embeddedice.h"
  31 #include "etm.h"
  32 #include "etb.h"
  33 #include "log.h"
  34 #include "jtag.h"
  35 #include "arm_jtag.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39
  40 #if 0
  41 #define _DEBUG_INSTRUCTION_EXECUTION_
  42 #endif
  43
  44 /* cli handling */
  45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
  46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm9tdmi_quit();
  52
  53 target_type_t arm9tdmi_target =
  54 {
  55         .name = "arm9tdmi",
  56
  57         .poll = arm7_9_poll,
  58         .arch_state = armv4_5_arch_state,
  59
  60         .halt = arm7_9_halt,
  61         .resume = arm7_9_resume,
  62         .step = arm7_9_step,
  63
  64         .assert_reset = arm7_9_assert_reset,
  65         .deassert_reset = arm7_9_deassert_reset,
  66         .soft_reset_halt = arm7_9_soft_reset_halt,
  67         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  68
  69         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  70
  71         .read_memory = arm7_9_read_memory,
  72         .write_memory = arm7_9_write_memory,
  73         .bulk_write_memory = arm7_9_bulk_write_memory,
  74
  75         .run_algorithm = armv4_5_run_algorithm,
  76
  77         .add_breakpoint = arm7_9_add_breakpoint,
  78         .remove_breakpoint = arm7_9_remove_breakpoint,
  79         .add_watchpoint = arm7_9_add_watchpoint,
  80         .remove_watchpoint = arm7_9_remove_watchpoint,
  81
  82         .register_commands = arm9tdmi_register_commands,
  83         .target_command = arm9tdmi_target_command,
  84         .init_target = arm9tdmi_init_target,
  85         .quit = arm9tdmi_quit
  86 };
  87
  88 arm9tdmi_vector_t arm9tdmi_vectors[] =
  89 {
  90         {"reset", ARM9TDMI_RESET_VECTOR},
  91         {"undef", ARM9TDMI_UNDEF_VECTOR},
  92         {"swi", ARM9TDMI_SWI_VECTOR},
  93         {"pabt", ARM9TDMI_PABT_VECTOR},
  94         {"dabt", ARM9TDMI_DABT_VECTOR},
  95         {"reserved", ARM9TDMI_RESERVED_VECTOR},
  96         {"irq", ARM9TDMI_IRQ_VECTOR},
  97         {"fiq", ARM9TDMI_FIQ_VECTOR},
  98         {0, 0},
  99 };
 100
 101 int arm9tdmi_examine_debug_reason(target_t *target)
 102 {
 103         /* get pointers to arch-specific information */
 104         armv4_5_common_t *armv4_5 = target->arch_info;
 105         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 106
 107         /* only check the debug reason if we don't know it already */
 108         if ((target->debug_reason != DBG_REASON_DBGRQ)
 109                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 110         {
 111                 scan_field_t fields[3];
 112                 u8 databus[4];
 113                 u8 instructionbus[4];
 114                 u8 debug_reason;
 115
 116                 jtag_add_end_state(TAP_PD);
 117
 118                 fields[0].device = arm7_9->jtag_info.chain_pos;
 119                 fields[0].num_bits = 32;
 120                 fields[0].out_value = NULL;
 121                 fields[0].out_mask = NULL;
 122                 fields[0].in_value = databus;
 123                 fields[0].in_check_value = NULL;
 124                 fields[0].in_check_mask = NULL;
 125                 fields[0].in_handler = NULL;
 126                 fields[0].in_handler_priv = NULL;
 127
 128                 fields[1].device = arm7_9->jtag_info.chain_pos;
 129                 fields[1].num_bits = 3;
 130                 fields[1].out_value = NULL;
 131                 fields[1].out_mask = NULL;
 132                 fields[1].in_value = &debug_reason;
 133                 fields[1].in_check_value = NULL;
 134                 fields[1].in_check_mask = NULL;
 135                 fields[1].in_handler = NULL;
 136                 fields[1].in_handler_priv = NULL;
 137
 138                 fields[2].device = arm7_9->jtag_info.chain_pos;
 139                 fields[2].num_bits = 32;
 140                 fields[2].out_value = NULL;
 141                 fields[2].out_mask = NULL;
 142                 fields[2].in_value = instructionbus;
 143                 fields[2].in_check_value = NULL;
 144                 fields[2].in_check_mask = NULL;
 145                 fields[2].in_handler = NULL;
 146                 fields[2].in_handler_priv = NULL;
 147
 148                 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
 149                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
 150
 151                 jtag_add_dr_scan(3, fields, TAP_PD);
 152                 jtag_execute_queue();
 153
 154                 fields[0].in_value = NULL;
 155                 fields[0].out_value = databus;
 156                 fields[1].in_value = NULL;
 157                 fields[1].out_value = &debug_reason;
 158                 fields[2].in_value = NULL;
 159                 fields[2].out_value = instructionbus;
 160
 161                 jtag_add_dr_scan(3, fields, TAP_PD);
 162
 163                 if (debug_reason & 0x4)
 164                         if (debug_reason & 0x2)
 165                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 166                 else
 167                         target->debug_reason = DBG_REASON_WATCHPOINT;
 168                 else
 169                         target->debug_reason = DBG_REASON_BREAKPOINT;
 170         }
 171
 172         return ERROR_OK;
 173 }
 174
 175 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 176 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 177 {
 178         scan_field_t fields[3];
 179         u8 out_buf[4];
 180         u8 instr_buf[4];
 181         u8 sysspeed_buf = 0x0;
 182
 183         /* prepare buffer */
 184         buf_set_u32(out_buf, 0, 32, out);
 185
 186         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 187
 188         if (sysspeed)
 189                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 190
 191         jtag_add_end_state(TAP_PD);
 192         arm_jtag_scann(jtag_info, 0x1);
 193         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 194
 195         fields[0].device = jtag_info->chain_pos;
 196         fields[0].num_bits = 32;
 197         fields[0].out_value = out_buf;
 198         fields[0].out_mask = NULL;
 199         fields[0].in_value = NULL;
 200         if (in)
 201         {
 202                 fields[0].in_handler = arm_jtag_buf_to_u32;
 203                 fields[0].in_handler_priv = in;
 204         }
 205         else
 206         {
 207                 fields[0].in_handler = NULL;
 208                 fields[0].in_handler_priv = NULL;
 209         }
 210         fields[0].in_check_value = NULL;
 211         fields[0].in_check_mask = NULL;
 212
 213         fields[1].device = jtag_info->chain_pos;
 214         fields[1].num_bits = 3;
 215         fields[1].out_value = &sysspeed_buf;
 216         fields[1].out_mask = NULL;
 217         fields[1].in_value = NULL;
 218         fields[1].in_check_value = NULL;
 219         fields[1].in_check_mask = NULL;
 220         fields[1].in_handler = NULL;
 221         fields[1].in_handler_priv = NULL;
 222
 223         fields[2].device = jtag_info->chain_pos;
 224         fields[2].num_bits = 32;
 225         fields[2].out_value = instr_buf;
 226         fields[2].out_mask = NULL;
 227         fields[2].in_value = NULL;
 228         fields[2].in_check_value = NULL;
 229         fields[2].in_check_mask = NULL;
 230         fields[2].in_handler = NULL;
 231         fields[2].in_handler_priv = NULL;
 232
 233         jtag_add_dr_scan(3, fields, -1);
 234
 235         jtag_add_runtest(0, -1);
 236
 237 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 238         {
 239                 jtag_execute_queue();
 240
 241                 if (in)
 242                 {
 243                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 244                 }
 245                 else
 246                         DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 247         }
 248 #endif
 249
 250         return ERROR_OK;
 251 }
 252
 253 /* just read data (instruction and data-out = don't care) */
 254 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 255 {
 256         scan_field_t fields[3];
 257
 258         jtag_add_end_state(TAP_PD);
 259         arm_jtag_scann(jtag_info, 0x1);
 260         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 261
 262         fields[0].device = jtag_info->chain_pos;
 263         fields[0].num_bits = 32;
 264         fields[0].out_value = NULL;
 265         fields[0].out_mask = NULL;
 266         fields[0].in_value = NULL;
 267         fields[0].in_handler = arm_jtag_buf_to_u32;
 268         fields[0].in_handler_priv = in;
 269         fields[0].in_check_value = NULL;
 270         fields[0].in_check_mask = NULL;
 271
 272         fields[1].device = jtag_info->chain_pos;
 273         fields[1].num_bits = 3;
 274         fields[1].out_value = NULL;
 275         fields[1].out_mask = NULL;
 276         fields[1].in_value = NULL;
 277         fields[1].in_handler = NULL;
 278         fields[1].in_handler_priv = NULL;
 279         fields[1].in_check_value = NULL;
 280         fields[1].in_check_mask = NULL;
 281
 282         fields[2].device = jtag_info->chain_pos;
 283         fields[2].num_bits = 32;
 284         fields[2].out_value = NULL;
 285         fields[2].out_mask = NULL;
 286         fields[2].in_value = NULL;
 287         fields[2].in_check_value = NULL;
 288         fields[2].in_check_mask = NULL;
 289         fields[2].in_handler = NULL;
 290         fields[2].in_handler_priv = NULL;
 291
 292         jtag_add_dr_scan(3, fields, -1);
 293
 294         jtag_add_runtest(0, -1);
 295
 296 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 297         {
 298                 jtag_execute_queue();
 299
 300                 if (in)
 301                 {
 302                         DEBUG("in: 0x%8.8x", *in);
 303                 }
 304                 else
 305                 {
 306                         ERROR("BUG: called with in == NULL");
 307                 }
 308         }
 309 #endif
 310
 311         return ERROR_OK;
 312 }
 313
 314 /* clock the target, and read the databus
 315  * the *in pointer points to a buffer where elements of 'size' bytes
 316  * are stored in big (be==1) or little (be==0) endianness
 317  */
 318 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 319 {
 320         scan_field_t fields[3];
 321
 322         jtag_add_end_state(TAP_PD);
 323         arm_jtag_scann(jtag_info, 0x1);
 324         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
 325
 326         fields[0].device = jtag_info->chain_pos;
 327         fields[0].num_bits = 32;
 328         fields[0].out_value = NULL;
 329         fields[0].out_mask = NULL;
 330         fields[0].in_value = NULL;
 331         switch (size)
 332         {
 333                 case 4:
 334                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
 335                         break;
 336                 case 2:
 337                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
 338                         break;
 339                 case 1:
 340                         fields[0].in_handler = arm_jtag_buf_to_8;
 341                         break;
 342         }
 343         fields[0].in_handler_priv = in;
 344         fields[0].in_check_value = NULL;
 345         fields[0].in_check_mask = NULL;
 346
 347         fields[1].device = jtag_info->chain_pos;
 348         fields[1].num_bits = 3;
 349         fields[1].out_value = NULL;
 350         fields[1].out_mask = NULL;
 351         fields[1].in_value = NULL;
 352         fields[1].in_handler = NULL;
 353         fields[1].in_handler_priv = NULL;
 354         fields[1].in_check_value = NULL;
 355         fields[1].in_check_mask = NULL;
 356
 357         fields[2].device = jtag_info->chain_pos;
 358         fields[2].num_bits = 32;
 359         fields[2].out_value = NULL;
 360         fields[2].out_mask = NULL;
 361         fields[2].in_value = NULL;
 362         fields[2].in_check_value = NULL;
 363         fields[2].in_check_mask = NULL;
 364         fields[2].in_handler = NULL;
 365         fields[2].in_handler_priv = NULL;
 366
 367         jtag_add_dr_scan(3, fields, -1);
 368
 369         jtag_add_runtest(0, -1);
 370
 371 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 372         {
 373                 jtag_execute_queue();
 374
 375                 if (in)
 376                 {
 377                         DEBUG("in: 0x%8.8x", *in);
 378                 }
 379                 else
 380                 {
 381                         ERROR("BUG: called with in == NULL");
 382                 }
 383         }
 384 #endif
 385
 386         return ERROR_OK;
 387 }
 388
 389 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 390 {
 391         /* get pointers to arch-specific information */
 392         armv4_5_common_t *armv4_5 = target->arch_info;
 393         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 394         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 395
 396         /* save r0 before using it and put system in ARM state
 397          * to allow common handling of ARM and THUMB debugging */
 398
 399         /* fetch STR r0, [r0] */
 400         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 401         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 402         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 403         /* STR r0, [r0] in Memory */
 404         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 405
 406         /* MOV r0, r15 fetched, STR in Decode */
 407         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 408         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 409         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 410         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 411         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 412         /* nothing fetched, STR r0, [r0] in Memory */
 413         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 414
 415         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 416         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 417         /* LDR in Decode */
 418         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 419         /* LDR in Execute */
 420         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 421         /* LDR in Memory (to account for interlock) */
 422         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 423
 424         /* fetch BX */
 425         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 426         /* NOP fetched, BX in Decode, MOV in Execute */
 427         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 428         /* NOP fetched, BX in Execute (1) */
 429         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 430
 431         jtag_execute_queue();
 432
 433         /* fix program counter:
 434          * MOV r0, r15 was the 5th instruction (+8)
 435          * reading PC in Thumb state gives address of instruction + 4
 436          */
 437         *pc -= 0xc;
 438 }
 439
 440 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 441 {
 442         int i;
 443         /* get pointers to arch-specific information */
 444         armv4_5_common_t *armv4_5 = target->arch_info;
 445         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 446         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 447
 448         /* STMIA r0-15, [r0] at debug speed
 449          * register values will start to appear on 4th DCLK
 450          */
 451         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 452
 453         /* fetch NOP, STM in DECODE stage */
 454         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 455         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 456         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 457
 458         for (i = 0; i <= 15; i++)
 459         {
 460                 if (mask & (1 << i))
 461                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 462                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 463         }
 464
 465 }
 466
 467 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 468 {
 469         int i;
 470         /* get pointers to arch-specific information */
 471         armv4_5_common_t *armv4_5 = target->arch_info;
 472         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 473         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 474         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 475         u32 *buf_u32 = buffer;
 476         u16 *buf_u16 = buffer;
 477         u8 *buf_u8 = buffer;
 478
 479         /* STMIA r0-15, [r0] at debug speed
 480          * register values will start to appear on 4th DCLK
 481          */
 482         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 483
 484         /* fetch NOP, STM in DECODE stage */
 485         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 486         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 487         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 488
 489         for (i = 0; i <= 15; i++)
 490         {
 491                 if (mask & (1 << i))
 492                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 493                         switch (size)
 494                         {
 495                                 case 4:
 496                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 497                                         break;
 498                                 case 2:
 499                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 500                                         break;
 501                                 case 1:
 502                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 503                                         break;
 504                         }
 505         }
 506
 507 }
 508
 509 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 510 {
 511         /* get pointers to arch-specific information */
 512         armv4_5_common_t *armv4_5 = target->arch_info;
 513         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 514         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 515
 516         /* MRS r0, cpsr */
 517         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 518         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 519         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 520         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 521         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 522
 523         /* STR r0, [r15] */
 524         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 525         /* fetch NOP, STR in DECODE stage */
 526         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 527         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 528         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 529         /* nothing fetched, STR in MEMORY */
 530         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 531
 532 }
 533
 534 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 535 {
 536         /* get pointers to arch-specific information */
 537         armv4_5_common_t *armv4_5 = target->arch_info;
 538         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 539         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 540
 541         DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 542
 543         /* MSR1 fetched */
 544         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 545         /* MSR2 fetched, MSR1 in DECODE */
 546         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 547         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 548         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 549         /* nothing fetched, MSR1 in EXECUTE (2) */
 550         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 551         /* nothing fetched, MSR1 in EXECUTE (3) */
 552         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 553         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 554         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 555         /* nothing fetched, MSR2 in EXECUTE (2) */
 556         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 557         /* nothing fetched, MSR2 in EXECUTE (3) */
 558         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 559         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 560         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 561         /* nothing fetched, MSR3 in EXECUTE (2) */
 562         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 563         /* nothing fetched, MSR3 in EXECUTE (3) */
 564         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 565         /* NOP fetched, MSR4 in EXECUTE (1) */
 566         /* last MSR writes flags, which takes only one cycle */
 567         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 568 }
 569
 570 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 571 {
 572         /* get pointers to arch-specific information */
 573         armv4_5_common_t *armv4_5 = target->arch_info;
 574         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 575         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 576
 577         DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 578
 579         /* MSR fetched */
 580         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 581         /* NOP fetched, MSR in DECODE */
 582         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 583         /* NOP fetched, MSR in EXECUTE (1) */
 584         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 585
 586         /* rot == 4 writes flags, which takes only one cycle */
 587         if (rot != 4)
 588         {
 589                 /* nothing fetched, MSR in EXECUTE (2) */
 590                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 591                 /* nothing fetched, MSR in EXECUTE (3) */
 592                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 593         }
 594 }
 595
 596 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 597 {
 598         int i;
 599         /* get pointers to arch-specific information */
 600         armv4_5_common_t *armv4_5 = target->arch_info;
 601         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 602         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 603
 604         /* LDMIA r0-15, [r0] at debug speed
 605         * register values will start to appear on 4th DCLK
 606         */
 607         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 608
 609         /* fetch NOP, LDM in DECODE stage */
 610         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 611         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 612         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 613
 614         for (i = 0; i <= 15; i++)
 615         {
 616                 if (mask & (1 << i))
 617                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 618                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 619         }
 620         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 621
 622 }
 623
 624 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 625 {
 626         /* get pointers to arch-specific information */
 627         armv4_5_common_t *armv4_5 = target->arch_info;
 628         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 629         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 630
 631         /* put system-speed load-multiple into the pipeline */
 632         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 633         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 634
 635 }
 636
 637 void arm9tdmi_load_hword_reg(target_t *target, int num)
 638 {
 639         /* get pointers to arch-specific information */
 640         armv4_5_common_t *armv4_5 = target->arch_info;
 641         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 642         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 643
 644         /* put system-speed load half-word into the pipeline */
 645         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 646         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 647 }
 648
 649 void arm9tdmi_load_byte_reg(target_t *target, int num)
 650 {
 651         /* get pointers to arch-specific information */
 652         armv4_5_common_t *armv4_5 = target->arch_info;
 653         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 654         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 655
 656         /* put system-speed load byte into the pipeline */
 657         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 658         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 659
 660 }
 661
 662 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 663 {
 664         /* get pointers to arch-specific information */
 665         armv4_5_common_t *armv4_5 = target->arch_info;
 666         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 667         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 668
 669         /* put system-speed store-multiple into the pipeline */
 670         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 671         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 672
 673 }
 674
 675 void arm9tdmi_store_hword_reg(target_t *target, int num)
 676 {
 677         /* get pointers to arch-specific information */
 678         armv4_5_common_t *armv4_5 = target->arch_info;
 679         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 680         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 681
 682         /* put system-speed store half-word into the pipeline */
 683         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 684         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 685
 686 }
 687
 688 void arm9tdmi_store_byte_reg(target_t *target, int num)
 689 {
 690         /* get pointers to arch-specific information */
 691         armv4_5_common_t *armv4_5 = target->arch_info;
 692         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 693         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 694
 695         /* put system-speed store byte into the pipeline */
 696         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 697         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 698
 699 }
 700
 701 void arm9tdmi_write_pc(target_t *target, u32 pc)
 702 {
 703         /* get pointers to arch-specific information */
 704         armv4_5_common_t *armv4_5 = target->arch_info;
 705         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 706         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 707
 708         /* LDMIA r0-15, [r0] at debug speed
 709          * register values will start to appear on 4th DCLK
 710          */
 711         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 712
 713         /* fetch NOP, LDM in DECODE stage */
 714         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 715         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 716         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 717         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 718         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 719         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 720         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 721         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 722         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 723         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 724         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 725
 726 }
 727
 728 void arm9tdmi_branch_resume(target_t *target)
 729 {
 730         /* get pointers to arch-specific information */
 731         armv4_5_common_t *armv4_5 = target->arch_info;
 732         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 733         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 734
 735         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 736         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 737
 738 }
 739
 740 void arm9tdmi_branch_resume_thumb(target_t *target)
 741 {
 742         DEBUG("-");
 743
 744         /* get pointers to arch-specific information */
 745         armv4_5_common_t *armv4_5 = target->arch_info;
 746         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 747         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 748         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 749
 750         /* LDMIA r0-15, [r0] at debug speed
 751         * register values will start to appear on 4th DCLK
 752         */
 753         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 754
 755         /* fetch NOP, LDM in DECODE stage */
 756         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 757         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 758         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 759         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 760         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 761         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 762         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 763
 764         /* Branch and eXchange */
 765         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 766
 767         embeddedice_read_reg(dbg_stat);
 768
 769         /* fetch NOP, BX in DECODE stage */
 770         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 771
 772         embeddedice_read_reg(dbg_stat);
 773
 774         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 775         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 776
 777         /* target is now in Thumb state */
 778         embeddedice_read_reg(dbg_stat);
 779
 780         /* load r0 value, MOV_IM in Decode*/
 781         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 782         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 783         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 784         /* fetch NOP, LDR in Execute */
 785         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 786         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 787         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 788         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 789         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 790
 791         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 792         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 793
 794         embeddedice_read_reg(dbg_stat);
 795
 796         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 797         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 798
 799 }
 800
 801 void arm9tdmi_enable_single_step(target_t *target)
 802 {
 803         /* get pointers to arch-specific information */
 804         armv4_5_common_t *armv4_5 = target->arch_info;
 805         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 806
 807         if (arm7_9->has_single_step)
 808         {
 809                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 810                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 811         }
 812         else
 813         {
 814                 arm7_9_enable_eice_step(target);
 815         }
 816 }
 817
 818 void arm9tdmi_disable_single_step(target_t *target)
 819 {
 820         /* get pointers to arch-specific information */
 821         armv4_5_common_t *armv4_5 = target->arch_info;
 822         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 823
 824         if (arm7_9->has_single_step)
 825         {
 826                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 827                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 828         }
 829         else
 830         {
 831                 arm7_9_disable_eice_step(target);
 832         }
 833 }
 834
 835 void arm9tdmi_build_reg_cache(target_t *target)
 836 {
 837         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 838         /* get pointers to arch-specific information */
 839         armv4_5_common_t *armv4_5 = target->arch_info;
 840         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 841         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 842
 843         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 844         armv4_5->core_cache = (*cache_p);
 845
 846         /* one extra register (vector catch) */
 847         (*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
 848         arm7_9->eice_cache = (*cache_p)->next;
 849
 850         if (arm7_9->has_etm)
 851         {
 852                 (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
 853                 arm7_9->etm_cache = (*cache_p)->next->next;
 854         }
 855
 856         if (arm7_9->etb)
 857         {
 858                 (*cache_p)->next->next->next = etb_build_reg_cache(arm7_9->etb);
 859                 arm7_9->etb->reg_cache = (*cache_p)->next->next->next;
 860         }
 861 }
 862
 863 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 864 {
 865
 866         arm9tdmi_build_reg_cache(target);
 867
 868         return ERROR_OK;
 869
 870 }
 871
 872 int arm9tdmi_quit()
 873 {
 874
 875         return ERROR_OK;
 876 }
 877
 878 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, char *variant)
 879 {
 880         armv4_5_common_t *armv4_5;
 881         arm7_9_common_t *arm7_9;
 882
 883         arm7_9 = &arm9tdmi->arm7_9_common;
 884         armv4_5 = &arm7_9->armv4_5_common;
 885
 886         /* prepare JTAG information for the new target */
 887         arm7_9->jtag_info.chain_pos = chain_pos;
 888         arm7_9->jtag_info.scann_size = 5;
 889
 890         /* register arch-specific functions */
 891         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 892         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 893         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 894         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 895         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 896
 897         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 898         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 899         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 900
 901         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 902         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 903         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 904
 905         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 906         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 907         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 908
 909         arm7_9->write_pc = arm9tdmi_write_pc;
 910         arm7_9->branch_resume = arm9tdmi_branch_resume;
 911         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 912
 913         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 914         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 915
 916         arm7_9->pre_debug_entry = NULL;
 917         arm7_9->post_debug_entry = NULL;
 918
 919         arm7_9->pre_restore_context = NULL;
 920         arm7_9->post_restore_context = NULL;
 921
 922         /* initialize arch-specific breakpoint handling */
 923         buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
 924         buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
 925
 926         arm7_9->sw_bkpts_use_wp = 1;
 927         arm7_9->sw_bkpts_enabled = 0;
 928         arm7_9->dbgreq_adjust_pc = 3;
 929         arm7_9->arch_info = arm9tdmi;
 930
 931         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 932         arm9tdmi->arch_info = NULL;
 933
 934         if (variant)
 935         {
 936                 arm9tdmi->variant = strdup(variant);
 937         }
 938         else
 939         {
 940                 arm9tdmi->variant = strdup("");
 941         }
 942
 943         arm7_9_init_arch_info(target, arm7_9);
 944
 945         /* override use of DBGRQ, this is safe on ARM9TDMI */
 946         arm7_9->use_dbgrq = 1;
 947
 948         /* all ARM9s have the vector catch register */
 949         arm7_9->has_vector_catch = 1;
 950
 951         return ERROR_OK;
 952 }
 953
 954 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
 955 {
 956         armv4_5_common_t *armv4_5 = target->arch_info;
 957         arm7_9_common_t *arm7_9;
 958         arm9tdmi_common_t *arm9tdmi;
 959
 960         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 961         {
 962                 return -1;
 963         }
 964
 965         arm7_9 = armv4_5->arch_info;
 966         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 967         {
 968                 return -1;
 969         }
 970
 971         arm9tdmi = arm7_9->arch_info;
 972         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 973         {
 974                 return -1;
 975         }
 976
 977         *armv4_5_p = armv4_5;
 978         *arm7_9_p = arm7_9;
 979         *arm9tdmi_p = arm9tdmi;
 980
 981         return ERROR_OK;
 982 }
 983
 984
 985 /* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/
 986 int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 987 {
 988         int chain_pos;
 989         char *variant = NULL;
 990         arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t));
 991
 992         if (argc < 4)
 993         {
 994                 ERROR("'target arm9tdmi' requires at least one additional argument");
 995                 exit(-1);
 996         }
 997
 998         chain_pos = strtoul(args[3], NULL, 0);
 999
1000         if (argc >= 5)
1001                 variant = args[4];
1002
1003         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
1004
1005         return ERROR_OK;
1006 }
1007
1008 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1009 {
1010         int retval;
1011
1012         command_t *arm9tdmi_cmd;
1013
1014
1015         retval = arm7_9_register_commands(cmd_ctx);
1016
1017         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1018
1019         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1020
1021
1022         return ERROR_OK;
1023
1024 }
1025
1026 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1027 {
1028         target_t *target = get_current_target(cmd_ctx);
1029         armv4_5_common_t *armv4_5;
1030         arm7_9_common_t *arm7_9;
1031         arm9tdmi_common_t *arm9tdmi;
1032         reg_t *vector_catch;
1033         u32 vector_catch_value;
1034         int i, j;
1035
1036         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1037         {
1038                 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1039                 return ERROR_OK;
1040         }
1041
1042         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1043
1044         /* read the vector catch register if necessary */
1045         if (!vector_catch->valid)
1046                 embeddedice_read_reg(vector_catch);
1047
1048         /* get the current setting */
1049         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1050
1051         if (argc > 0)
1052         {
1053                 vector_catch_value = 0x0;
1054                 if (strcmp(args[0], "all") == 0)
1055                 {
1056                         vector_catch_value = 0xdf;
1057                 }
1058                 else if (strcmp(args[0], "none") == 0)
1059                 {
1060                         /* do nothing */
1061                 }
1062                 else
1063                 {
1064                         for (i = 0; i < argc; i++)
1065                         {
1066                                 /* go through list of vectors */
1067                                 for(j = 0; arm9tdmi_vectors[j].name; j++)
1068                                 {
1069                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1070                                         {
1071                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1072                                                 break;
1073                                         }
1074                                 }
1075
1076                                 /* complain if vector wasn't found */
1077                                 if (!arm9tdmi_vectors[j].name)
1078                                 {
1079                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1080
1081                                         /* reread current setting */
1082                                         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1083
1084                                         break;
1085                                 }
1086                         }
1087                 }
1088
1089                 /* store new settings */
1090                 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1091                 embeddedice_store_reg(vector_catch);
1092         }
1093
1094         /* output current settings (skip RESERVED vector) */
1095         for (i = 0; i < 8; i++)
1096         {
1097                 if (i != 5)
1098                 {
1099                         command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1100                                 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1101                 }
1102         }
1103
1104         return ERROR_OK;
1105 }