1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
41 #define _DEBUG_INSTRUCTION_EXECUTION_
45 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
46 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 /* forward declarations */
49 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
51 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm9tdmi_quit(void);
54 target_type_t arm9tdmi_target =
59 .arch_state = armv4_5_arch_state,
61 .target_request_data = arm7_9_target_request_data,
64 .resume = arm7_9_resume,
67 .assert_reset = arm7_9_assert_reset,
68 .deassert_reset = arm7_9_deassert_reset,
69 .soft_reset_halt = arm7_9_soft_reset_halt,
71 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
73 .read_memory = arm7_9_read_memory,
74 .write_memory = arm7_9_write_memory,
75 .bulk_write_memory = arm7_9_bulk_write_memory,
76 .checksum_memory = arm7_9_checksum_memory,
77 .blank_check_memory = arm7_9_blank_check_memory,
79 .run_algorithm = armv4_5_run_algorithm,
81 .add_breakpoint = arm7_9_add_breakpoint,
82 .remove_breakpoint = arm7_9_remove_breakpoint,
83 .add_watchpoint = arm7_9_add_watchpoint,
84 .remove_watchpoint = arm7_9_remove_watchpoint,
86 .register_commands = arm9tdmi_register_commands,
87 .target_create = arm9tdmi_target_create,
88 .init_target = arm9tdmi_init_target,
89 .examine = arm9tdmi_examine,
93 arm9tdmi_vector_t arm9tdmi_vectors[] =
95 {"reset", ARM9TDMI_RESET_VECTOR},
96 {"undef", ARM9TDMI_UNDEF_VECTOR},
97 {"swi", ARM9TDMI_SWI_VECTOR},
98 {"pabt", ARM9TDMI_PABT_VECTOR},
99 {"dabt", ARM9TDMI_DABT_VECTOR},
100 {"reserved", ARM9TDMI_RESERVED_VECTOR},
101 {"irq", ARM9TDMI_IRQ_VECTOR},
102 {"fiq", ARM9TDMI_FIQ_VECTOR},
106 int arm9tdmi_examine_debug_reason(target_t *target)
108 /* get pointers to arch-specific information */
109 armv4_5_common_t *armv4_5 = target->arch_info;
110 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
112 /* only check the debug reason if we don't know it already */
113 if ((target->debug_reason != DBG_REASON_DBGRQ)
114 && (target->debug_reason != DBG_REASON_SINGLESTEP))
116 scan_field_t fields[3];
118 u8 instructionbus[4];
121 jtag_add_end_state(TAP_PD);
123 fields[0].device = arm7_9->jtag_info.chain_pos;
124 fields[0].num_bits = 32;
125 fields[0].out_value = NULL;
126 fields[0].out_mask = NULL;
127 fields[0].in_value = databus;
128 fields[0].in_check_value = NULL;
129 fields[0].in_check_mask = NULL;
130 fields[0].in_handler = NULL;
131 fields[0].in_handler_priv = NULL;
133 fields[1].device = arm7_9->jtag_info.chain_pos;
134 fields[1].num_bits = 3;
135 fields[1].out_value = NULL;
136 fields[1].out_mask = NULL;
137 fields[1].in_value = &debug_reason;
138 fields[1].in_check_value = NULL;
139 fields[1].in_check_mask = NULL;
140 fields[1].in_handler = NULL;
141 fields[1].in_handler_priv = NULL;
143 fields[2].device = arm7_9->jtag_info.chain_pos;
144 fields[2].num_bits = 32;
145 fields[2].out_value = NULL;
146 fields[2].out_mask = NULL;
147 fields[2].in_value = instructionbus;
148 fields[2].in_check_value = NULL;
149 fields[2].in_check_mask = NULL;
150 fields[2].in_handler = NULL;
151 fields[2].in_handler_priv = NULL;
153 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
154 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
156 jtag_add_dr_scan(3, fields, TAP_PD);
157 jtag_execute_queue();
159 fields[0].in_value = NULL;
160 fields[0].out_value = databus;
161 fields[1].in_value = NULL;
162 fields[1].out_value = &debug_reason;
163 fields[2].in_value = NULL;
164 fields[2].out_value = instructionbus;
166 jtag_add_dr_scan(3, fields, TAP_PD);
168 if (debug_reason & 0x4)
169 if (debug_reason & 0x2)
170 target->debug_reason = DBG_REASON_WPTANDBKPT;
172 target->debug_reason = DBG_REASON_WATCHPOINT;
174 target->debug_reason = DBG_REASON_BREAKPOINT;
180 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
181 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
183 scan_field_t fields[3];
186 u8 sysspeed_buf = 0x0;
189 buf_set_u32(out_buf, 0, 32, out);
191 buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
194 buf_set_u32(&sysspeed_buf, 2, 1, 1);
196 jtag_add_end_state(TAP_PD);
197 arm_jtag_scann(jtag_info, 0x1);
199 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
201 fields[0].device = jtag_info->chain_pos;
202 fields[0].num_bits = 32;
203 fields[0].out_value = out_buf;
204 fields[0].out_mask = NULL;
205 fields[0].in_value = NULL;
208 fields[0].in_handler = arm_jtag_buf_to_u32;
209 fields[0].in_handler_priv = in;
213 fields[0].in_handler = NULL;
214 fields[0].in_handler_priv = NULL;
216 fields[0].in_check_value = NULL;
217 fields[0].in_check_mask = NULL;
219 fields[1].device = jtag_info->chain_pos;
220 fields[1].num_bits = 3;
221 fields[1].out_value = &sysspeed_buf;
222 fields[1].out_mask = NULL;
223 fields[1].in_value = NULL;
224 fields[1].in_check_value = NULL;
225 fields[1].in_check_mask = NULL;
226 fields[1].in_handler = NULL;
227 fields[1].in_handler_priv = NULL;
229 fields[2].device = jtag_info->chain_pos;
230 fields[2].num_bits = 32;
231 fields[2].out_value = instr_buf;
232 fields[2].out_mask = NULL;
233 fields[2].in_value = NULL;
234 fields[2].in_check_value = NULL;
235 fields[2].in_check_mask = NULL;
236 fields[2].in_handler = NULL;
237 fields[2].in_handler_priv = NULL;
239 jtag_add_dr_scan(3, fields, -1);
241 jtag_add_runtest(0, -1);
243 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
245 jtag_execute_queue();
249 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
252 LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
259 /* just read data (instruction and data-out = don't care) */
260 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
262 scan_field_t fields[3];
264 jtag_add_end_state(TAP_PD);
265 arm_jtag_scann(jtag_info, 0x1);
267 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
269 fields[0].device = jtag_info->chain_pos;
270 fields[0].num_bits = 32;
271 fields[0].out_value = NULL;
272 fields[0].out_mask = NULL;
273 fields[0].in_value = NULL;
274 fields[0].in_handler = arm_jtag_buf_to_u32;
275 fields[0].in_handler_priv = in;
276 fields[0].in_check_value = NULL;
277 fields[0].in_check_mask = NULL;
279 fields[1].device = jtag_info->chain_pos;
280 fields[1].num_bits = 3;
281 fields[1].out_value = NULL;
282 fields[1].out_mask = NULL;
283 fields[1].in_value = NULL;
284 fields[1].in_handler = NULL;
285 fields[1].in_handler_priv = NULL;
286 fields[1].in_check_value = NULL;
287 fields[1].in_check_mask = NULL;
289 fields[2].device = jtag_info->chain_pos;
290 fields[2].num_bits = 32;
291 fields[2].out_value = NULL;
292 fields[2].out_mask = NULL;
293 fields[2].in_value = NULL;
294 fields[2].in_check_value = NULL;
295 fields[2].in_check_mask = NULL;
296 fields[2].in_handler = NULL;
297 fields[2].in_handler_priv = NULL;
299 jtag_add_dr_scan(3, fields, -1);
301 jtag_add_runtest(0, -1);
303 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
305 jtag_execute_queue();
309 LOG_DEBUG("in: 0x%8.8x", *in);
313 LOG_ERROR("BUG: called with in == NULL");
321 /* clock the target, and read the databus
322 * the *in pointer points to a buffer where elements of 'size' bytes
323 * are stored in big (be==1) or little (be==0) endianness
325 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
327 scan_field_t fields[3];
329 jtag_add_end_state(TAP_PD);
330 arm_jtag_scann(jtag_info, 0x1);
332 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
334 fields[0].device = jtag_info->chain_pos;
335 fields[0].num_bits = 32;
336 fields[0].out_value = NULL;
337 fields[0].out_mask = NULL;
338 fields[0].in_value = NULL;
342 fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
345 fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
348 fields[0].in_handler = arm_jtag_buf_to_8;
351 fields[0].in_handler_priv = in;
352 fields[0].in_check_value = NULL;
353 fields[0].in_check_mask = NULL;
355 fields[1].device = jtag_info->chain_pos;
356 fields[1].num_bits = 3;
357 fields[1].out_value = NULL;
358 fields[1].out_mask = NULL;
359 fields[1].in_value = NULL;
360 fields[1].in_handler = NULL;
361 fields[1].in_handler_priv = NULL;
362 fields[1].in_check_value = NULL;
363 fields[1].in_check_mask = NULL;
365 fields[2].device = jtag_info->chain_pos;
366 fields[2].num_bits = 32;
367 fields[2].out_value = NULL;
368 fields[2].out_mask = NULL;
369 fields[2].in_value = NULL;
370 fields[2].in_check_value = NULL;
371 fields[2].in_check_mask = NULL;
372 fields[2].in_handler = NULL;
373 fields[2].in_handler_priv = NULL;
375 jtag_add_dr_scan(3, fields, -1);
377 jtag_add_runtest(0, -1);
379 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
381 jtag_execute_queue();
385 LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
389 LOG_ERROR("BUG: called with in == NULL");
397 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
399 /* get pointers to arch-specific information */
400 armv4_5_common_t *armv4_5 = target->arch_info;
401 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
402 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
404 /* save r0 before using it and put system in ARM state
405 * to allow common handling of ARM and THUMB debugging */
407 /* fetch STR r0, [r0] */
408 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
409 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
410 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
411 /* STR r0, [r0] in Memory */
412 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
414 /* MOV r0, r15 fetched, STR in Decode */
415 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
416 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
417 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
418 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
419 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
420 /* nothing fetched, STR r0, [r0] in Memory */
421 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
423 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
424 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
426 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
428 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
429 /* LDR in Memory (to account for interlock) */
430 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
433 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
434 /* NOP fetched, BX in Decode, MOV in Execute */
435 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
436 /* NOP fetched, BX in Execute (1) */
437 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
439 jtag_execute_queue();
441 /* fix program counter:
442 * MOV r0, r15 was the 5th instruction (+8)
443 * reading PC in Thumb state gives address of instruction + 4
448 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
451 /* get pointers to arch-specific information */
452 armv4_5_common_t *armv4_5 = target->arch_info;
453 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
454 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
456 /* STMIA r0-15, [r0] at debug speed
457 * register values will start to appear on 4th DCLK
459 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
461 /* fetch NOP, STM in DECODE stage */
462 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
463 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
464 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
466 for (i = 0; i <= 15; i++)
469 /* nothing fetched, STM in MEMORY (i'th cycle) */
470 arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
475 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
478 /* get pointers to arch-specific information */
479 armv4_5_common_t *armv4_5 = target->arch_info;
480 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
481 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
482 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
483 u32 *buf_u32 = buffer;
484 u16 *buf_u16 = buffer;
487 /* STMIA r0-15, [r0] at debug speed
488 * register values will start to appear on 4th DCLK
490 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
492 /* fetch NOP, STM in DECODE stage */
493 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
494 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
495 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
497 for (i = 0; i <= 15; i++)
500 /* nothing fetched, STM in MEMORY (i'th cycle) */
504 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
507 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
510 arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
517 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
519 /* get pointers to arch-specific information */
520 armv4_5_common_t *armv4_5 = target->arch_info;
521 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
522 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
525 arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
526 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
527 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
528 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
529 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
532 arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
533 /* fetch NOP, STR in DECODE stage */
534 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
535 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
536 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
537 /* nothing fetched, STR in MEMORY */
538 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
542 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
544 /* get pointers to arch-specific information */
545 armv4_5_common_t *armv4_5 = target->arch_info;
546 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
547 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
549 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
552 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
553 /* MSR2 fetched, MSR1 in DECODE */
554 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
555 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
556 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
557 /* nothing fetched, MSR1 in EXECUTE (2) */
558 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
559 /* nothing fetched, MSR1 in EXECUTE (3) */
560 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
561 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
562 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
563 /* nothing fetched, MSR2 in EXECUTE (2) */
564 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
565 /* nothing fetched, MSR2 in EXECUTE (3) */
566 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
567 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
568 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
569 /* nothing fetched, MSR3 in EXECUTE (2) */
570 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
571 /* nothing fetched, MSR3 in EXECUTE (3) */
572 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
573 /* NOP fetched, MSR4 in EXECUTE (1) */
574 /* last MSR writes flags, which takes only one cycle */
575 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
578 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
580 /* get pointers to arch-specific information */
581 armv4_5_common_t *armv4_5 = target->arch_info;
582 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
583 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
585 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
588 arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
589 /* NOP fetched, MSR in DECODE */
590 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
591 /* NOP fetched, MSR in EXECUTE (1) */
592 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
594 /* rot == 4 writes flags, which takes only one cycle */
597 /* nothing fetched, MSR in EXECUTE (2) */
598 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
599 /* nothing fetched, MSR in EXECUTE (3) */
600 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
604 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
607 /* get pointers to arch-specific information */
608 armv4_5_common_t *armv4_5 = target->arch_info;
609 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
610 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
612 /* LDMIA r0-15, [r0] at debug speed
613 * register values will start to appear on 4th DCLK
615 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
617 /* fetch NOP, LDM in DECODE stage */
618 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
619 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
620 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
622 for (i = 0; i <= 15; i++)
625 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
626 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
628 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
632 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
634 /* get pointers to arch-specific information */
635 armv4_5_common_t *armv4_5 = target->arch_info;
636 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
637 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
639 /* put system-speed load-multiple into the pipeline */
640 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
641 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
645 void arm9tdmi_load_hword_reg(target_t *target, int num)
647 /* get pointers to arch-specific information */
648 armv4_5_common_t *armv4_5 = target->arch_info;
649 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
650 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
652 /* put system-speed load half-word into the pipeline */
653 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
654 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
657 void arm9tdmi_load_byte_reg(target_t *target, int num)
659 /* get pointers to arch-specific information */
660 armv4_5_common_t *armv4_5 = target->arch_info;
661 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
662 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
664 /* put system-speed load byte into the pipeline */
665 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
666 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
670 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
672 /* get pointers to arch-specific information */
673 armv4_5_common_t *armv4_5 = target->arch_info;
674 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
675 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
677 /* put system-speed store-multiple into the pipeline */
678 arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
679 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
683 void arm9tdmi_store_hword_reg(target_t *target, int num)
685 /* get pointers to arch-specific information */
686 armv4_5_common_t *armv4_5 = target->arch_info;
687 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
688 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
690 /* put system-speed store half-word into the pipeline */
691 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
692 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
696 void arm9tdmi_store_byte_reg(target_t *target, int num)
698 /* get pointers to arch-specific information */
699 armv4_5_common_t *armv4_5 = target->arch_info;
700 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
701 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
703 /* put system-speed store byte into the pipeline */
704 arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
705 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
709 void arm9tdmi_write_pc(target_t *target, u32 pc)
711 /* get pointers to arch-specific information */
712 armv4_5_common_t *armv4_5 = target->arch_info;
713 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
714 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
716 /* LDMIA r0-15, [r0] at debug speed
717 * register values will start to appear on 4th DCLK
719 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
721 /* fetch NOP, LDM in DECODE stage */
722 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
723 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
724 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
725 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
726 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
727 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
728 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
729 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
730 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
731 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
732 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
736 void arm9tdmi_branch_resume(target_t *target)
738 /* get pointers to arch-specific information */
739 armv4_5_common_t *armv4_5 = target->arch_info;
740 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
741 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
743 arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
744 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
748 void arm9tdmi_branch_resume_thumb(target_t *target)
752 /* get pointers to arch-specific information */
753 armv4_5_common_t *armv4_5 = target->arch_info;
754 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
755 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
756 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
758 /* LDMIA r0-15, [r0] at debug speed
759 * register values will start to appear on 4th DCLK
761 arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
763 /* fetch NOP, LDM in DECODE stage */
764 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
765 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
766 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
767 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
768 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
769 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
770 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
772 /* Branch and eXchange */
773 arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
775 embeddedice_read_reg(dbg_stat);
777 /* fetch NOP, BX in DECODE stage */
778 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
780 embeddedice_read_reg(dbg_stat);
782 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
783 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
785 /* target is now in Thumb state */
786 embeddedice_read_reg(dbg_stat);
788 /* load r0 value, MOV_IM in Decode*/
789 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
790 /* fetch NOP, LDR in Decode, MOV_IM in Execute */
791 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
792 /* fetch NOP, LDR in Execute */
793 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
794 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
795 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
796 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
797 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
799 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
800 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
802 embeddedice_read_reg(dbg_stat);
804 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
805 arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
809 void arm9tdmi_enable_single_step(target_t *target)
811 /* get pointers to arch-specific information */
812 armv4_5_common_t *armv4_5 = target->arch_info;
813 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
815 if (arm7_9->has_single_step)
817 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
818 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
822 arm7_9_enable_eice_step(target);
826 void arm9tdmi_disable_single_step(target_t *target)
828 /* get pointers to arch-specific information */
829 armv4_5_common_t *armv4_5 = target->arch_info;
830 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
832 if (arm7_9->has_single_step)
834 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
835 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
839 arm7_9_disable_eice_step(target);
843 void arm9tdmi_build_reg_cache(target_t *target)
845 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
846 /* get pointers to arch-specific information */
847 armv4_5_common_t *armv4_5 = target->arch_info;
849 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
850 armv4_5->core_cache = (*cache_p);
854 int arm9tdmi_examine(struct target_s *target)
856 /* get pointers to arch-specific information */
858 armv4_5_common_t *armv4_5 = target->arch_info;
859 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
860 if (!target->type->examined)
862 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
864 /* one extra register (vector catch) */
865 t=embeddedice_build_reg_cache(target, arm7_9);
869 arm7_9->eice_cache = (*cache_p);
873 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
874 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
875 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
877 target->type->examined = 1;
879 if ((retval=embeddedice_setup(target))!=ERROR_OK)
881 if ((retval=arm7_9_setup(target))!=ERROR_OK)
885 if ((retval=etm_setup(target))!=ERROR_OK)
891 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
894 arm9tdmi_build_reg_cache(target);
900 int arm9tdmi_quit(void)
906 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, const char *variant)
908 armv4_5_common_t *armv4_5;
909 arm7_9_common_t *arm7_9;
911 arm7_9 = &arm9tdmi->arm7_9_common;
912 armv4_5 = &arm7_9->armv4_5_common;
914 /* prepare JTAG information for the new target */
915 arm7_9->jtag_info.chain_pos = chain_pos;
916 arm7_9->jtag_info.scann_size = 5;
918 /* register arch-specific functions */
919 arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
920 arm7_9->change_to_arm = arm9tdmi_change_to_arm;
921 arm7_9->read_core_regs = arm9tdmi_read_core_regs;
922 arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
923 arm7_9->read_xpsr = arm9tdmi_read_xpsr;
925 arm7_9->write_xpsr = arm9tdmi_write_xpsr;
926 arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
927 arm7_9->write_core_regs = arm9tdmi_write_core_regs;
929 arm7_9->load_word_regs = arm9tdmi_load_word_regs;
930 arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
931 arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
933 arm7_9->store_word_regs = arm9tdmi_store_word_regs;
934 arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
935 arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
937 arm7_9->write_pc = arm9tdmi_write_pc;
938 arm7_9->branch_resume = arm9tdmi_branch_resume;
939 arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
941 arm7_9->enable_single_step = arm9tdmi_enable_single_step;
942 arm7_9->disable_single_step = arm9tdmi_disable_single_step;
944 arm7_9->pre_debug_entry = NULL;
945 arm7_9->post_debug_entry = NULL;
947 arm7_9->pre_restore_context = NULL;
948 arm7_9->post_restore_context = NULL;
950 /* initialize arch-specific breakpoint handling */
951 arm7_9->arm_bkpt = 0xdeeedeee;
952 arm7_9->thumb_bkpt = 0xdeee;
954 arm7_9->dbgreq_adjust_pc = 3;
955 arm7_9->arch_info = arm9tdmi;
957 arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
958 arm9tdmi->arch_info = NULL;
962 arm9tdmi->variant = strdup(variant);
966 arm9tdmi->variant = strdup("");
969 arm7_9_init_arch_info(target, arm7_9);
971 /* override use of DBGRQ, this is safe on ARM9TDMI */
972 arm7_9->use_dbgrq = 1;
974 /* all ARM9s have the vector catch register */
975 arm7_9->has_vector_catch = 1;
980 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
982 armv4_5_common_t *armv4_5 = target->arch_info;
983 arm7_9_common_t *arm7_9;
984 arm9tdmi_common_t *arm9tdmi;
986 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
991 arm7_9 = armv4_5->arch_info;
992 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
997 arm9tdmi = arm7_9->arch_info;
998 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
1003 *armv4_5_p = armv4_5;
1005 *arm9tdmi_p = arm9tdmi;
1012 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
1014 arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
1016 arm9tdmi_init_arch_info(target, arm9tdmi, target->chain_position, target->variant);
1021 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1025 command_t *arm9tdmi_cmd;
1028 retval = arm7_9_register_commands(cmd_ctx);
1030 arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1032 register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1039 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1041 target_t *target = get_current_target(cmd_ctx);
1042 armv4_5_common_t *armv4_5;
1043 arm7_9_common_t *arm7_9;
1044 arm9tdmi_common_t *arm9tdmi;
1045 reg_t *vector_catch;
1046 u32 vector_catch_value;
1049 if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1051 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1055 vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1057 /* read the vector catch register if necessary */
1058 if (!vector_catch->valid)
1059 embeddedice_read_reg(vector_catch);
1061 /* get the current setting */
1062 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1066 vector_catch_value = 0x0;
1067 if (strcmp(args[0], "all") == 0)
1069 vector_catch_value = 0xdf;
1071 else if (strcmp(args[0], "none") == 0)
1077 for (i = 0; i < argc; i++)
1079 /* go through list of vectors */
1080 for(j = 0; arm9tdmi_vectors[j].name; j++)
1082 if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1084 vector_catch_value |= arm9tdmi_vectors[j].value;
1089 /* complain if vector wasn't found */
1090 if (!arm9tdmi_vectors[j].name)
1092 command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1094 /* reread current setting */
1095 vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1102 /* store new settings */
1103 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1104 embeddedice_store_reg(vector_catch);
1107 /* output current settings (skip RESERVED vector) */
1108 for (i = 0; i < 8; i++)
1112 command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1113 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1123 * Local Variables: ***
1124 * c-basic-offset: 4 ***