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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   This program is free software; you can redistribute it and/or modify  *
   9  *   it under the terms of the GNU General Public License as published by  *
  10  *   the Free Software Foundation; either version 2 of the License, or     *
  11  *   (at your option) any later version.                                   *
  12  *                                                                         *
  13  *   This program is distributed in the hope that it will be useful,       *
  14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  16  *   GNU General Public License for more details.                          *
  17  *                                                                         *
  18  *   You should have received a copy of the GNU General Public License     *
  19  *   along with this program; if not, write to the                         *
  20  *   Free Software Foundation, Inc.,                                       *
  21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  22  ***************************************************************************/
  23 #ifdef HAVE_CONFIG_H
  24 #include "config.h"
  25 #endif
  26
  27 #include "arm9tdmi.h"
  28
  29 #include "arm7_9_common.h"
  30 #include "register.h"
  31 #include "target.h"
  32 #include "armv4_5.h"
  33 #include "embeddedice.h"
  34 #include "etm.h"
  35 #include "etb.h"
  36 #include "log.h"
  37 #include "jtag.h"
  38 #include "arm_jtag.h"
  39
  40 #include <stdlib.h>
  41 #include <string.h>
  42
  43 #if 0
  44 #define _DEBUG_INSTRUCTION_EXECUTION_
  45 #endif
  46
  47 /* cli handling */
  48 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx);
  49 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  50
  51 /* forward declarations */
  52 int arm9tdmi_target_create( struct target_s *target, Jim_Interp *interp );
  53
  54 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  55 int arm9tdmi_quit(void);
  56
  57 target_type_t arm9tdmi_target =
  58 {
  59         .name = "arm9tdmi",
  60
  61         .poll = arm7_9_poll,
  62         .arch_state = armv4_5_arch_state,
  63
  64         .target_request_data = arm7_9_target_request_data,
  65
  66         .halt = arm7_9_halt,
  67         .resume = arm7_9_resume,
  68         .step = arm7_9_step,
  69
  70         .assert_reset = arm7_9_assert_reset,
  71         .deassert_reset = arm7_9_deassert_reset,
  72         .soft_reset_halt = arm7_9_soft_reset_halt,
  73
  74         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  75
  76         .read_memory = arm7_9_read_memory,
  77         .write_memory = arm7_9_write_memory,
  78         .bulk_write_memory = arm7_9_bulk_write_memory,
  79         .checksum_memory = arm7_9_checksum_memory,
  80         .blank_check_memory = arm7_9_blank_check_memory,
  81
  82         .run_algorithm = armv4_5_run_algorithm,
  83
  84         .add_breakpoint = arm7_9_add_breakpoint,
  85         .remove_breakpoint = arm7_9_remove_breakpoint,
  86         .add_watchpoint = arm7_9_add_watchpoint,
  87         .remove_watchpoint = arm7_9_remove_watchpoint,
  88
  89         .register_commands = arm9tdmi_register_commands,
  90         .target_create = arm9tdmi_target_create,
  91         .init_target = arm9tdmi_init_target,
  92         .examine = arm9tdmi_examine,
  93         .quit = arm9tdmi_quit
  94 };
  95
  96 arm9tdmi_vector_t arm9tdmi_vectors[] =
  97 {
  98         {"reset", ARM9TDMI_RESET_VECTOR},
  99         {"undef", ARM9TDMI_UNDEF_VECTOR},
 100         {"swi", ARM9TDMI_SWI_VECTOR},
 101         {"pabt", ARM9TDMI_PABT_VECTOR},
 102         {"dabt", ARM9TDMI_DABT_VECTOR},
 103         {"reserved", ARM9TDMI_RESERVED_VECTOR},
 104         {"irq", ARM9TDMI_IRQ_VECTOR},
 105         {"fiq", ARM9TDMI_FIQ_VECTOR},
 106         {0, 0},
 107 };
 108
 109 int arm9tdmi_examine_debug_reason(target_t *target)
 110 {
 111         int retval = ERROR_OK;
 112         /* get pointers to arch-specific information */
 113         armv4_5_common_t *armv4_5 = target->arch_info;
 114         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 115
 116         /* only check the debug reason if we don't know it already */
 117         if ((target->debug_reason != DBG_REASON_DBGRQ)
 118                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 119         {
 120                 scan_field_t fields[3];
 121                 u8 databus[4];
 122                 u8 instructionbus[4];
 123                 u8 debug_reason;
 124
 125                 jtag_add_end_state(TAP_PD);
 126
 127                 fields[0].device = arm7_9->jtag_info.chain_pos;
 128                 fields[0].num_bits = 32;
 129                 fields[0].out_value = NULL;
 130                 fields[0].out_mask = NULL;
 131                 fields[0].in_value = databus;
 132                 fields[0].in_check_value = NULL;
 133                 fields[0].in_check_mask = NULL;
 134                 fields[0].in_handler = NULL;
 135                 fields[0].in_handler_priv = NULL;
 136
 137                 fields[1].device = arm7_9->jtag_info.chain_pos;
 138                 fields[1].num_bits = 3;
 139                 fields[1].out_value = NULL;
 140                 fields[1].out_mask = NULL;
 141                 fields[1].in_value = &debug_reason;
 142                 fields[1].in_check_value = NULL;
 143                 fields[1].in_check_mask = NULL;
 144                 fields[1].in_handler = NULL;
 145                 fields[1].in_handler_priv = NULL;
 146
 147                 fields[2].device = arm7_9->jtag_info.chain_pos;
 148                 fields[2].num_bits = 32;
 149                 fields[2].out_value = NULL;
 150                 fields[2].out_mask = NULL;
 151                 fields[2].in_value = instructionbus;
 152                 fields[2].in_check_value = NULL;
 153                 fields[2].in_check_mask = NULL;
 154                 fields[2].in_handler = NULL;
 155                 fields[2].in_handler_priv = NULL;
 156
 157                 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 158                 {
 159                         return retval;
 160                 }
 161                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 162
 163                 jtag_add_dr_scan(3, fields, TAP_PD);
 164                 if((retval = jtag_execute_queue()) != ERROR_OK)
 165                 {
 166                         return retval;
 167                 }
 168
 169                 fields[0].in_value = NULL;
 170                 fields[0].out_value = databus;
 171                 fields[1].in_value = NULL;
 172                 fields[1].out_value = &debug_reason;
 173                 fields[2].in_value = NULL;
 174                 fields[2].out_value = instructionbus;
 175
 176                 jtag_add_dr_scan(3, fields, TAP_PD);
 177
 178                 if (debug_reason & 0x4)
 179                         if (debug_reason & 0x2)
 180                                 target->debug_reason = DBG_REASON_WPTANDBKPT;
 181                 else
 182                         target->debug_reason = DBG_REASON_WATCHPOINT;
 183                 else
 184                         target->debug_reason = DBG_REASON_BREAKPOINT;
 185         }
 186
 187         return ERROR_OK;
 188 }
 189
 190 /* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
 191 int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
 192 {
 193         int retval = ERROR_OK;
 194         scan_field_t fields[3];
 195         u8 out_buf[4];
 196         u8 instr_buf[4];
 197         u8 sysspeed_buf = 0x0;
 198
 199         /* prepare buffer */
 200         buf_set_u32(out_buf, 0, 32, out);
 201
 202         buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 203
 204         if (sysspeed)
 205                 buf_set_u32(&sysspeed_buf, 2, 1, 1);
 206
 207         jtag_add_end_state(TAP_PD);
 208         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 209         {
 210                 return retval;
 211         }
 212
 213         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 214
 215         fields[0].device = jtag_info->chain_pos;
 216         fields[0].num_bits = 32;
 217         fields[0].out_value = out_buf;
 218         fields[0].out_mask = NULL;
 219         fields[0].in_value = NULL;
 220         if (in)
 221         {
 222                 fields[0].in_handler = arm_jtag_buf_to_u32;
 223                 fields[0].in_handler_priv = in;
 224         }
 225         else
 226         {
 227                 fields[0].in_handler = NULL;
 228                 fields[0].in_handler_priv = NULL;
 229         }
 230         fields[0].in_check_value = NULL;
 231         fields[0].in_check_mask = NULL;
 232
 233         fields[1].device = jtag_info->chain_pos;
 234         fields[1].num_bits = 3;
 235         fields[1].out_value = &sysspeed_buf;
 236         fields[1].out_mask = NULL;
 237         fields[1].in_value = NULL;
 238         fields[1].in_check_value = NULL;
 239         fields[1].in_check_mask = NULL;
 240         fields[1].in_handler = NULL;
 241         fields[1].in_handler_priv = NULL;
 242
 243         fields[2].device = jtag_info->chain_pos;
 244         fields[2].num_bits = 32;
 245         fields[2].out_value = instr_buf;
 246         fields[2].out_mask = NULL;
 247         fields[2].in_value = NULL;
 248         fields[2].in_check_value = NULL;
 249         fields[2].in_check_mask = NULL;
 250         fields[2].in_handler = NULL;
 251         fields[2].in_handler_priv = NULL;
 252
 253         jtag_add_dr_scan(3, fields, -1);
 254
 255         jtag_add_runtest(0, -1);
 256
 257 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 258         {
 259                 if((retval = jtag_execute_queue()) != ERROR_OK)
 260                 {
 261                         return retval;
 262                 }
 263
 264                 if (in)
 265                 {
 266                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
 267                 }
 268                 else
 269                         LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
 270         }
 271 #endif
 272
 273         return ERROR_OK;
 274 }
 275
 276 /* just read data (instruction and data-out = don't care) */
 277 int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 278 {
 279         int retval = ERROR_OK;;
 280         scan_field_t fields[3];
 281
 282         jtag_add_end_state(TAP_PD);
 283         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 284         {
 285                 return retval;
 286         }
 287
 288         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 289
 290         fields[0].device = jtag_info->chain_pos;
 291         fields[0].num_bits = 32;
 292         fields[0].out_value = NULL;
 293         fields[0].out_mask = NULL;
 294         fields[0].in_value = NULL;
 295         fields[0].in_handler = arm_jtag_buf_to_u32;
 296         fields[0].in_handler_priv = in;
 297         fields[0].in_check_value = NULL;
 298         fields[0].in_check_mask = NULL;
 299
 300         fields[1].device = jtag_info->chain_pos;
 301         fields[1].num_bits = 3;
 302         fields[1].out_value = NULL;
 303         fields[1].out_mask = NULL;
 304         fields[1].in_value = NULL;
 305         fields[1].in_handler = NULL;
 306         fields[1].in_handler_priv = NULL;
 307         fields[1].in_check_value = NULL;
 308         fields[1].in_check_mask = NULL;
 309
 310         fields[2].device = jtag_info->chain_pos;
 311         fields[2].num_bits = 32;
 312         fields[2].out_value = NULL;
 313         fields[2].out_mask = NULL;
 314         fields[2].in_value = NULL;
 315         fields[2].in_check_value = NULL;
 316         fields[2].in_check_mask = NULL;
 317         fields[2].in_handler = NULL;
 318         fields[2].in_handler_priv = NULL;
 319
 320         jtag_add_dr_scan(3, fields, -1);
 321
 322         jtag_add_runtest(0, -1);
 323
 324 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 325         {
 326                 if((retval = jtag_execute_queue()) != ERROR_OK)
 327                 {
 328                         return retval;
 329                 }
 330
 331                 if (in)
 332                 {
 333                         LOG_DEBUG("in: 0x%8.8x", *in);
 334                 }
 335                 else
 336                 {
 337                         LOG_ERROR("BUG: called with in == NULL");
 338                 }
 339         }
 340 #endif
 341
 342         return ERROR_OK;
 343 }
 344
 345 /* clock the target, and read the databus
 346  * the *in pointer points to a buffer where elements of 'size' bytes
 347  * are stored in big (be==1) or little (be==0) endianness
 348  */
 349 int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 350 {
 351         int retval = ERROR_OK;
 352         scan_field_t fields[3];
 353
 354         jtag_add_end_state(TAP_PD);
 355         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 356         {
 357                 return retval;
 358         }
 359
 360         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 361
 362         fields[0].device = jtag_info->chain_pos;
 363         fields[0].num_bits = 32;
 364         fields[0].out_value = NULL;
 365         fields[0].out_mask = NULL;
 366         fields[0].in_value = NULL;
 367         switch (size)
 368         {
 369                 case 4:
 370                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be32 : arm_jtag_buf_to_le32;
 371                         break;
 372                 case 2:
 373                         fields[0].in_handler = (be) ? arm_jtag_buf_to_be16 : arm_jtag_buf_to_le16;
 374                         break;
 375                 case 1:
 376                         fields[0].in_handler = arm_jtag_buf_to_8;
 377                         break;
 378         }
 379         fields[0].in_handler_priv = in;
 380         fields[0].in_check_value = NULL;
 381         fields[0].in_check_mask = NULL;
 382
 383         fields[1].device = jtag_info->chain_pos;
 384         fields[1].num_bits = 3;
 385         fields[1].out_value = NULL;
 386         fields[1].out_mask = NULL;
 387         fields[1].in_value = NULL;
 388         fields[1].in_handler = NULL;
 389         fields[1].in_handler_priv = NULL;
 390         fields[1].in_check_value = NULL;
 391         fields[1].in_check_mask = NULL;
 392
 393         fields[2].device = jtag_info->chain_pos;
 394         fields[2].num_bits = 32;
 395         fields[2].out_value = NULL;
 396         fields[2].out_mask = NULL;
 397         fields[2].in_value = NULL;
 398         fields[2].in_check_value = NULL;
 399         fields[2].in_check_mask = NULL;
 400         fields[2].in_handler = NULL;
 401         fields[2].in_handler_priv = NULL;
 402
 403         jtag_add_dr_scan(3, fields, -1);
 404
 405         jtag_add_runtest(0, -1);
 406
 407 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 408         {
 409                 if((retval = jtag_execute_queue()) != ERROR_OK)
 410                 {
 411                         return retval;
 412                 }
 413
 414                 if (in)
 415                 {
 416                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 417                 }
 418                 else
 419                 {
 420                         LOG_ERROR("BUG: called with in == NULL");
 421                 }
 422         }
 423 #endif
 424
 425         return ERROR_OK;
 426 }
 427
 428 void arm9tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 429 {
 430         int retval = ERROR_OK;
 431         /* get pointers to arch-specific information */
 432         armv4_5_common_t *armv4_5 = target->arch_info;
 433         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 434         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 435
 436         /* save r0 before using it and put system in ARM state
 437          * to allow common handling of ARM and THUMB debugging */
 438
 439         /* fetch STR r0, [r0] */
 440         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 441         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 442         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 443         /* STR r0, [r0] in Memory */
 444         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, r0, 0);
 445
 446         /* MOV r0, r15 fetched, STR in Decode */
 447         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), 0, NULL, 0);
 448         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 449         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), 0, NULL, 0);
 450         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 451         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 452         /* nothing fetched, STR r0, [r0] in Memory */
 453         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, pc, 0);
 454
 455         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 456         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 457         /* LDR in Decode */
 458         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 459         /* LDR in Execute */
 460         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 461         /* LDR in Memory (to account for interlock) */
 462         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 463
 464         /* fetch BX */
 465         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), 0, NULL, 0);
 466         /* NOP fetched, BX in Decode, MOV in Execute */
 467         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 468         /* NOP fetched, BX in Execute (1) */
 469         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 470
 471         if((retval = jtag_execute_queue()) != ERROR_OK)
 472         {
 473                 return retval;
 474         }
 475
 476         /* fix program counter:
 477          * MOV r0, r15 was the 5th instruction (+8)
 478          * reading PC in Thumb state gives address of instruction + 4
 479          */
 480         *pc -= 0xc;
 481 }
 482
 483 void arm9tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 484 {
 485         int i;
 486         /* get pointers to arch-specific information */
 487         armv4_5_common_t *armv4_5 = target->arch_info;
 488         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 489         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 490
 491         /* STMIA r0-15, [r0] at debug speed
 492          * register values will start to appear on 4th DCLK
 493          */
 494         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 495
 496         /* fetch NOP, STM in DECODE stage */
 497         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 498         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 499         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 500
 501         for (i = 0; i <= 15; i++)
 502         {
 503                 if (mask & (1 << i))
 504                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 505                         arm9tdmi_clock_data_in(jtag_info, core_regs[i]);
 506         }
 507
 508 }
 509
 510 void arm9tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 511 {
 512         int i;
 513         /* get pointers to arch-specific information */
 514         armv4_5_common_t *armv4_5 = target->arch_info;
 515         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 516         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 517         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 518         u32 *buf_u32 = buffer;
 519         u16 *buf_u16 = buffer;
 520         u8 *buf_u8 = buffer;
 521
 522         /* STMIA r0-15, [r0] at debug speed
 523          * register values will start to appear on 4th DCLK
 524          */
 525         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 526
 527         /* fetch NOP, STM in DECODE stage */
 528         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 529         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 530         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 531
 532         for (i = 0; i <= 15; i++)
 533         {
 534                 if (mask & (1 << i))
 535                         /* nothing fetched, STM in MEMORY (i'th cycle) */
 536                         switch (size)
 537                         {
 538                                 case 4:
 539                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 540                                         break;
 541                                 case 2:
 542                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 543                                         break;
 544                                 case 1:
 545                                         arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 546                                         break;
 547                         }
 548         }
 549
 550 }
 551
 552 void arm9tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 553 {
 554         /* get pointers to arch-specific information */
 555         armv4_5_common_t *armv4_5 = target->arch_info;
 556         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 557         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 558
 559         /* MRS r0, cpsr */
 560         arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0);
 561         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 562         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 563         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 564         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 565
 566         /* STR r0, [r15] */
 567         arm9tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), 0, NULL, 0);
 568         /* fetch NOP, STR in DECODE stage */
 569         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 570         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 571         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 572         /* nothing fetched, STR in MEMORY */
 573         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, xpsr, 0);
 574
 575 }
 576
 577 void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 578 {
 579         /* get pointers to arch-specific information */
 580         armv4_5_common_t *armv4_5 = target->arch_info;
 581         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 582         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 583
 584         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 585
 586         /* MSR1 fetched */
 587         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 588         /* MSR2 fetched, MSR1 in DECODE */
 589         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), 0, NULL, 0);
 590         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 591         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), 0, NULL, 0);
 592         /* nothing fetched, MSR1 in EXECUTE (2) */
 593         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 594         /* nothing fetched, MSR1 in EXECUTE (3) */
 595         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 596         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 597         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), 0, NULL, 0);
 598         /* nothing fetched, MSR2 in EXECUTE (2) */
 599         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 600         /* nothing fetched, MSR2 in EXECUTE (3) */
 601         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 602         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 603         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 604         /* nothing fetched, MSR3 in EXECUTE (2) */
 605         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 606         /* nothing fetched, MSR3 in EXECUTE (3) */
 607         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 608         /* NOP fetched, MSR4 in EXECUTE (1) */
 609         /* last MSR writes flags, which takes only one cycle */
 610         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 611 }
 612
 613 void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 614 {
 615         /* get pointers to arch-specific information */
 616         armv4_5_common_t *armv4_5 = target->arch_info;
 617         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 618         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 619
 620         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 621
 622         /* MSR fetched */
 623         arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
 624         /* NOP fetched, MSR in DECODE */
 625         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 626         /* NOP fetched, MSR in EXECUTE (1) */
 627         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 628
 629         /* rot == 4 writes flags, which takes only one cycle */
 630         if (rot != 4)
 631         {
 632                 /* nothing fetched, MSR in EXECUTE (2) */
 633                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 634                 /* nothing fetched, MSR in EXECUTE (3) */
 635                 arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 636         }
 637 }
 638
 639 void arm9tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 640 {
 641         int i;
 642         /* get pointers to arch-specific information */
 643         armv4_5_common_t *armv4_5 = target->arch_info;
 644         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 645         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 646
 647         /* LDMIA r0-15, [r0] at debug speed
 648         * register values will start to appear on 4th DCLK
 649         */
 650         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0);
 651
 652         /* fetch NOP, LDM in DECODE stage */
 653         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 654         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 655         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 656
 657         for (i = 0; i <= 15; i++)
 658         {
 659                 if (mask & (1 << i))
 660                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 661                         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, core_regs[i], NULL, 0);
 662         }
 663         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 664
 665 }
 666
 667 void arm9tdmi_load_word_regs(target_t *target, u32 mask)
 668 {
 669         /* get pointers to arch-specific information */
 670         armv4_5_common_t *armv4_5 = target->arch_info;
 671         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 672         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 673
 674         /* put system-speed load-multiple into the pipeline */
 675         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), 0, NULL, 0);
 676         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 677
 678 }
 679
 680 void arm9tdmi_load_hword_reg(target_t *target, int num)
 681 {
 682         /* get pointers to arch-specific information */
 683         armv4_5_common_t *armv4_5 = target->arch_info;
 684         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 685         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 686
 687         /* put system-speed load half-word into the pipeline */
 688         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), 0, NULL, 0);
 689         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 690 }
 691
 692 void arm9tdmi_load_byte_reg(target_t *target, int num)
 693 {
 694         /* get pointers to arch-specific information */
 695         armv4_5_common_t *armv4_5 = target->arch_info;
 696         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 697         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 698
 699         /* put system-speed load byte into the pipeline */
 700         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), 0, NULL, 0);
 701         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 702
 703 }
 704
 705 void arm9tdmi_store_word_regs(target_t *target, u32 mask)
 706 {
 707         /* get pointers to arch-specific information */
 708         armv4_5_common_t *armv4_5 = target->arch_info;
 709         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 710         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 711
 712         /* put system-speed store-multiple into the pipeline */
 713         arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), 0, NULL, 0);
 714         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 715
 716 }
 717
 718 void arm9tdmi_store_hword_reg(target_t *target, int num)
 719 {
 720         /* get pointers to arch-specific information */
 721         armv4_5_common_t *armv4_5 = target->arch_info;
 722         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 723         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 724
 725         /* put system-speed store half-word into the pipeline */
 726         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), 0, NULL, 0);
 727         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 728
 729 }
 730
 731 void arm9tdmi_store_byte_reg(target_t *target, int num)
 732 {
 733         /* get pointers to arch-specific information */
 734         armv4_5_common_t *armv4_5 = target->arch_info;
 735         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 736         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 737
 738         /* put system-speed store byte into the pipeline */
 739         arm9tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), 0, NULL, 0);
 740         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 741
 742 }
 743
 744 void arm9tdmi_write_pc(target_t *target, u32 pc)
 745 {
 746         /* get pointers to arch-specific information */
 747         armv4_5_common_t *armv4_5 = target->arch_info;
 748         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 749         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 750
 751         /* LDMIA r0-15, [r0] at debug speed
 752          * register values will start to appear on 4th DCLK
 753          */
 754         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), 0, NULL, 0);
 755
 756         /* fetch NOP, LDM in DECODE stage */
 757         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 758         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 759         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 760         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) (output data) */
 761         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, pc, NULL, 0);
 762         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 763         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 764         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 765         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 766         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 767         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 768
 769 }
 770
 771 void arm9tdmi_branch_resume(target_t *target)
 772 {
 773         /* get pointers to arch-specific information */
 774         armv4_5_common_t *armv4_5 = target->arch_info;
 775         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 776         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 777
 778         arm9tdmi_clock_out(jtag_info, ARMV4_5_B(0xfffffc, 0), 0, NULL, 0);
 779         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 780
 781 }
 782
 783 void arm9tdmi_branch_resume_thumb(target_t *target)
 784 {
 785         LOG_DEBUG("-");
 786
 787         /* get pointers to arch-specific information */
 788         armv4_5_common_t *armv4_5 = target->arch_info;
 789         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 790         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 791         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 792
 793         /* LDMIA r0-15, [r0] at debug speed
 794         * register values will start to appear on 4th DCLK
 795         */
 796         arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), 0, NULL, 0);
 797
 798         /* fetch NOP, LDM in DECODE stage */
 799         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 800         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 801         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 802         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 803         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 804         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 805         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 806
 807         /* Branch and eXchange */
 808         arm9tdmi_clock_out(jtag_info, ARMV4_5_BX(0), 0, NULL, 0);
 809
 810         embeddedice_read_reg(dbg_stat);
 811
 812         /* fetch NOP, BX in DECODE stage */
 813         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 814
 815         embeddedice_read_reg(dbg_stat);
 816
 817         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 818         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
 819
 820         /* target is now in Thumb state */
 821         embeddedice_read_reg(dbg_stat);
 822
 823         /* load r0 value, MOV_IM in Decode*/
 824         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), 0, NULL, 0);
 825         /* fetch NOP, LDR in Decode, MOV_IM in Execute */
 826         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 827         /* fetch NOP, LDR in Execute */
 828         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 829         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 830         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 831         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 832         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 833
 834         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 835         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 836
 837         embeddedice_read_reg(dbg_stat);
 838
 839         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f7), 0, NULL, 1);
 840         arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
 841
 842 }
 843
 844 void arm9tdmi_enable_single_step(target_t *target)
 845 {
 846         /* get pointers to arch-specific information */
 847         armv4_5_common_t *armv4_5 = target->arch_info;
 848         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 849
 850         if (arm7_9->has_single_step)
 851         {
 852                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 1);
 853                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 854         }
 855         else
 856         {
 857                 arm7_9_enable_eice_step(target);
 858         }
 859 }
 860
 861 void arm9tdmi_disable_single_step(target_t *target)
 862 {
 863         /* get pointers to arch-specific information */
 864         armv4_5_common_t *armv4_5 = target->arch_info;
 865         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 866
 867         if (arm7_9->has_single_step)
 868         {
 869                 buf_set_u32(arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].value, 3, 1, 0);
 870                 embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]);
 871         }
 872         else
 873         {
 874                 arm7_9_disable_eice_step(target);
 875         }
 876 }
 877
 878 void arm9tdmi_build_reg_cache(target_t *target)
 879 {
 880         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 881         /* get pointers to arch-specific information */
 882         armv4_5_common_t *armv4_5 = target->arch_info;
 883
 884         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 885         armv4_5->core_cache = (*cache_p);
 886 }
 887
 888
 889 int arm9tdmi_examine(struct target_s *target)
 890 {
 891         /* get pointers to arch-specific information */
 892         int retval;
 893         armv4_5_common_t *armv4_5 = target->arch_info;
 894         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 895         if (!target->type->examined)
 896         {
 897                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 898                 reg_cache_t *t;
 899                 /* one extra register (vector catch) */
 900                 t=embeddedice_build_reg_cache(target, arm7_9);
 901                 if (t==NULL)
 902                         return ERROR_FAIL;
 903                 (*cache_p) = t;
 904                 arm7_9->eice_cache = (*cache_p);
 905
 906                 if (arm7_9->etm_ctx)
 907                 {
 908                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 909                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 910                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 911                 }
 912                 target->type->examined = 1;
 913         }
 914         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 915                 return retval;
 916         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 917                 return retval;
 918         if (arm7_9->etm_ctx)
 919         {
 920                 if ((retval=etm_setup(target))!=ERROR_OK)
 921                         return retval;
 922         }
 923         return ERROR_OK;
 924 }
 925
 926 int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 927 {
 928
 929         arm9tdmi_build_reg_cache(target);
 930
 931         return ERROR_OK;
 932
 933 }
 934
 935 int arm9tdmi_quit(void)
 936 {
 937
 938         return ERROR_OK;
 939 }
 940
 941 int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int chain_pos, const char *variant)
 942 {
 943         armv4_5_common_t *armv4_5;
 944         arm7_9_common_t *arm7_9;
 945
 946         arm7_9 = &arm9tdmi->arm7_9_common;
 947         armv4_5 = &arm7_9->armv4_5_common;
 948
 949         /* prepare JTAG information for the new target */
 950         arm7_9->jtag_info.chain_pos = chain_pos;
 951         arm7_9->jtag_info.scann_size = 5;
 952
 953         /* register arch-specific functions */
 954         arm7_9->examine_debug_reason = arm9tdmi_examine_debug_reason;
 955         arm7_9->change_to_arm = arm9tdmi_change_to_arm;
 956         arm7_9->read_core_regs = arm9tdmi_read_core_regs;
 957         arm7_9->read_core_regs_target_buffer = arm9tdmi_read_core_regs_target_buffer;
 958         arm7_9->read_xpsr = arm9tdmi_read_xpsr;
 959
 960         arm7_9->write_xpsr = arm9tdmi_write_xpsr;
 961         arm7_9->write_xpsr_im8 = arm9tdmi_write_xpsr_im8;
 962         arm7_9->write_core_regs = arm9tdmi_write_core_regs;
 963
 964         arm7_9->load_word_regs = arm9tdmi_load_word_regs;
 965         arm7_9->load_hword_reg = arm9tdmi_load_hword_reg;
 966         arm7_9->load_byte_reg = arm9tdmi_load_byte_reg;
 967
 968         arm7_9->store_word_regs = arm9tdmi_store_word_regs;
 969         arm7_9->store_hword_reg = arm9tdmi_store_hword_reg;
 970         arm7_9->store_byte_reg = arm9tdmi_store_byte_reg;
 971
 972         arm7_9->write_pc = arm9tdmi_write_pc;
 973         arm7_9->branch_resume = arm9tdmi_branch_resume;
 974         arm7_9->branch_resume_thumb = arm9tdmi_branch_resume_thumb;
 975
 976         arm7_9->enable_single_step = arm9tdmi_enable_single_step;
 977         arm7_9->disable_single_step = arm9tdmi_disable_single_step;
 978
 979         arm7_9->pre_debug_entry = NULL;
 980         arm7_9->post_debug_entry = NULL;
 981
 982         arm7_9->pre_restore_context = NULL;
 983         arm7_9->post_restore_context = NULL;
 984
 985         /* initialize arch-specific breakpoint handling */
 986         arm7_9->arm_bkpt = 0xdeeedeee;
 987         arm7_9->thumb_bkpt = 0xdeee;
 988
 989         arm7_9->dbgreq_adjust_pc = 3;
 990         arm7_9->arch_info = arm9tdmi;
 991
 992         arm9tdmi->common_magic = ARM9TDMI_COMMON_MAGIC;
 993         arm9tdmi->arch_info = NULL;
 994
 995         if (variant)
 996         {
 997                 arm9tdmi->variant = strdup(variant);
 998         }
 999         else
1000         {
1001                 arm9tdmi->variant = strdup("");
1002         }
1003
1004         arm7_9_init_arch_info(target, arm7_9);
1005
1006         /* override use of DBGRQ, this is safe on ARM9TDMI */
1007         arm7_9->use_dbgrq = 1;
1008
1009         /* all ARM9s have the vector catch register */
1010         arm7_9->has_vector_catch = 1;
1011
1012         return ERROR_OK;
1013 }
1014
1015 int arm9tdmi_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p)
1016 {
1017         armv4_5_common_t *armv4_5 = target->arch_info;
1018         arm7_9_common_t *arm7_9;
1019         arm9tdmi_common_t *arm9tdmi;
1020
1021         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
1022         {
1023                 return -1;
1024         }
1025
1026         arm7_9 = armv4_5->arch_info;
1027         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
1028         {
1029                 return -1;
1030         }
1031
1032         arm9tdmi = arm7_9->arch_info;
1033         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
1034         {
1035                 return -1;
1036         }
1037
1038         *armv4_5_p = armv4_5;
1039         *arm7_9_p = arm7_9;
1040         *arm9tdmi_p = arm9tdmi;
1041
1042         return ERROR_OK;
1043 }
1044
1045
1046
1047 int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp)
1048 {
1049         arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
1050
1051         arm9tdmi_init_arch_info(target, arm9tdmi, target->chain_position, target->variant);
1052
1053         return ERROR_OK;
1054 }
1055
1056 int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
1057 {
1058         int retval;
1059
1060         command_t *arm9tdmi_cmd;
1061
1062
1063         retval = arm7_9_register_commands(cmd_ctx);
1064
1065         arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
1066
1067         register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
1068
1069
1070         return retval;
1071
1072 }
1073
1074 int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1075 {
1076         target_t *target = get_current_target(cmd_ctx);
1077         armv4_5_common_t *armv4_5;
1078         arm7_9_common_t *arm7_9;
1079         arm9tdmi_common_t *arm9tdmi;
1080         reg_t *vector_catch;
1081         u32 vector_catch_value;
1082         int i, j;
1083
1084         if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
1085         {
1086                 command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
1087                 return ERROR_OK;
1088         }
1089
1090         vector_catch = &arm7_9->eice_cache->reg_list[EICE_VEC_CATCH];
1091
1092         /* read the vector catch register if necessary */
1093         if (!vector_catch->valid)
1094                 embeddedice_read_reg(vector_catch);
1095
1096         /* get the current setting */
1097         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1098
1099         if (argc > 0)
1100         {
1101                 vector_catch_value = 0x0;
1102                 if (strcmp(args[0], "all") == 0)
1103                 {
1104                         vector_catch_value = 0xdf;
1105                 }
1106                 else if (strcmp(args[0], "none") == 0)
1107                 {
1108                         /* do nothing */
1109                 }
1110                 else
1111                 {
1112                         for (i = 0; i < argc; i++)
1113                         {
1114                                 /* go through list of vectors */
1115                                 for(j = 0; arm9tdmi_vectors[j].name; j++)
1116                                 {
1117                                         if (strcmp(args[i], arm9tdmi_vectors[j].name) == 0)
1118                                         {
1119                                                 vector_catch_value |= arm9tdmi_vectors[j].value;
1120                                                 break;
1121                                         }
1122                                 }
1123
1124                                 /* complain if vector wasn't found */
1125                                 if (!arm9tdmi_vectors[j].name)
1126                                 {
1127                                         command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
1128
1129                                         /* reread current setting */
1130                                         vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
1131
1132                                         break;
1133                                 }
1134                         }
1135                 }
1136
1137                 /* store new settings */
1138                 buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
1139                 embeddedice_store_reg(vector_catch);
1140         }
1141
1142         /* output current settings (skip RESERVED vector) */
1143         for (i = 0; i < 8; i++)
1144         {
1145                 if (i != 5)
1146                 {
1147                         command_print(cmd_ctx, "%s: %s", arm9tdmi_vectors[i].name,
1148                                 (vector_catch_value & (1 << i)) ? "catch" : "don't catch");
1149                 }
1150         }
1151
1152         return ERROR_OK;
1153 }