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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 1
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm926ejs_quit();
  52 int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size);
  53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm926ejs_soft_reset_halt(struct target_s *target);
  56
  57 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
  58
  59 target_type_t arm926ejs_target =
  60 {
  61         .name = "arm926ejs",
  62
  63         .poll = arm7_9_poll,
  64         .arch_state = arm926ejs_arch_state,
  65
  66         .target_request_data = arm7_9_target_request_data,
  67
  68         .halt = arm7_9_halt,
  69         .resume = arm7_9_resume,
  70         .step = arm7_9_step,
  71
  72         .assert_reset = arm7_9_assert_reset,
  73         .deassert_reset = arm7_9_deassert_reset,
  74         .soft_reset_halt = arm926ejs_soft_reset_halt,
  75         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  76
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  78
  79         .read_memory = arm7_9_read_memory,
  80         .write_memory = arm926ejs_write_memory,
  81         .bulk_write_memory = arm7_9_bulk_write_memory,
  82         .checksum_memory = arm7_9_checksum_memory,
  83
  84         .run_algorithm = armv4_5_run_algorithm,
  85
  86         .add_breakpoint = arm7_9_add_breakpoint,
  87         .remove_breakpoint = arm7_9_remove_breakpoint,
  88         .add_watchpoint = arm7_9_add_watchpoint,
  89         .remove_watchpoint = arm7_9_remove_watchpoint,
  90
  91         .register_commands = arm926ejs_register_commands,
  92         .target_command = arm926ejs_target_command,
  93         .init_target = arm926ejs_init_target,
  94         .quit = arm926ejs_quit
  95 };
  96
  97 int arm926ejs_catch_broken_irscan(u8 *in_value, void *priv)
  98 {
  99         /* The ARM926EJ-S' instruction register is 4 bits wide */
 100         *in_value &= 0xf;
 101
 102         if ((*in_value == 0x0f) || (*in_value == 0x00))
 103         {
 104                 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 105                 return ERROR_OK;
 106         }
 107         else
 108         {
 109                 return ERROR_JTAG_QUEUE_FAILED;
 110         }
 111 }
 112
 113 int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
 114 {
 115         armv4_5_common_t *armv4_5 = target->arch_info;
 116         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 117         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 118         scan_field_t fields[4];
 119         u8 address_buf[2];
 120         u8 nr_w_buf = 0;
 121         u8 access = 1;
 122         error_handler_t error_handler;
 123
 124         buf_set_u32(address_buf, 0, 14, address);
 125
 126         jtag_add_end_state(TAP_RTI);
 127         arm_jtag_scann(jtag_info, 0xf);
 128         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 129
 130         fields[0].device = jtag_info->chain_pos;
 131         fields[0].num_bits = 32;
 132         fields[0].out_value = NULL;
 133         fields[0].out_mask = NULL;
 134         fields[0].in_value = NULL;
 135         fields[0].in_check_value = NULL;
 136         fields[0].in_check_mask = NULL;
 137         fields[0].in_handler = NULL;
 138         fields[0].in_handler_priv = NULL;
 139
 140         fields[1].device = jtag_info->chain_pos;
 141         fields[1].num_bits = 1;
 142         fields[1].out_value = &access;
 143         fields[1].out_mask = NULL;
 144         fields[1].in_value = &access;
 145         fields[1].in_check_value = NULL;
 146         fields[1].in_check_mask = NULL;
 147         fields[1].in_handler = NULL;
 148         fields[1].in_handler_priv = NULL;
 149
 150         fields[2].device = jtag_info->chain_pos;
 151         fields[2].num_bits = 14;
 152         fields[2].out_value = address_buf;
 153         fields[2].out_mask = NULL;
 154         fields[2].in_value = NULL;
 155         fields[2].in_check_value = NULL;
 156         fields[2].in_check_mask = NULL;
 157         fields[2].in_handler = NULL;
 158         fields[2].in_handler_priv = NULL;
 159
 160         fields[3].device = jtag_info->chain_pos;
 161         fields[3].num_bits = 1;
 162         fields[3].out_value = &nr_w_buf;
 163         fields[3].out_mask = NULL;
 164         fields[3].in_value = NULL;
 165         fields[3].in_check_value = NULL;
 166         fields[3].in_check_mask = NULL;
 167         fields[3].in_handler = NULL;
 168         fields[3].in_handler_priv = NULL;
 169
 170         jtag_add_dr_scan(4, fields, -1, NULL);
 171
 172         fields[0].in_handler_priv = value;
 173         fields[0].in_handler = arm_jtag_buf_to_u32;
 174
 175         do
 176         {
 177                 /* rescan with NOP, to wait for the access to complete */
 178                 access = 0;
 179                 nr_w_buf = 0;
 180                 jtag_add_dr_scan(4, fields, -1, NULL);
 181                 jtag_execute_queue();
 182         } while (buf_get_u32(&access, 0, 1) != 1);
 183
 184 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 185         DEBUG("addr: 0x%x value: %8.8x", address, *value);
 186 #endif
 187
 188         error_handler.error_handler = arm926ejs_catch_broken_irscan;
 189         error_handler.error_handler_priv = NULL;
 190
 191         arm_jtag_set_instr(jtag_info, 0xc, &error_handler);
 192
 193         return ERROR_OK;
 194 }
 195
 196 int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
 197 {
 198         armv4_5_common_t *armv4_5 = target->arch_info;
 199         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 200         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 201         scan_field_t fields[4];
 202         u8 value_buf[4];
 203         u8 address_buf[2];
 204         u8 nr_w_buf = 1;
 205         u8 access = 1;
 206         error_handler_t error_handler;
 207
 208         buf_set_u32(address_buf, 0, 14, address);
 209         buf_set_u32(value_buf, 0, 32, value);
 210
 211         jtag_add_end_state(TAP_RTI);
 212         arm_jtag_scann(jtag_info, 0xf);
 213         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 214
 215         fields[0].device = jtag_info->chain_pos;
 216         fields[0].num_bits = 32;
 217         fields[0].out_value = value_buf;
 218         fields[0].out_mask = NULL;
 219         fields[0].in_value = NULL;
 220         fields[0].in_check_value = NULL;
 221         fields[0].in_check_mask = NULL;
 222         fields[0].in_handler = NULL;
 223         fields[0].in_handler_priv = NULL;
 224
 225         fields[1].device = jtag_info->chain_pos;
 226         fields[1].num_bits = 1;
 227         fields[1].out_value = &access;
 228         fields[1].out_mask = NULL;
 229         fields[1].in_value = &access;
 230         fields[1].in_check_value = NULL;
 231         fields[1].in_check_mask = NULL;
 232         fields[1].in_handler = NULL;
 233         fields[1].in_handler_priv = NULL;
 234
 235         fields[2].device = jtag_info->chain_pos;
 236         fields[2].num_bits = 14;
 237         fields[2].out_value = address_buf;
 238         fields[2].out_mask = NULL;
 239         fields[2].in_value = NULL;
 240         fields[2].in_check_value = NULL;
 241         fields[2].in_check_mask = NULL;
 242         fields[2].in_handler = NULL;
 243         fields[2].in_handler_priv = NULL;
 244
 245         fields[3].device = jtag_info->chain_pos;
 246         fields[3].num_bits = 1;
 247         fields[3].out_value = &nr_w_buf;
 248         fields[3].out_mask = NULL;
 249         fields[3].in_value = NULL;
 250         fields[3].in_check_value = NULL;
 251         fields[3].in_check_mask = NULL;
 252         fields[3].in_handler = NULL;
 253         fields[3].in_handler_priv = NULL;
 254
 255         jtag_add_dr_scan(4, fields, -1, NULL);
 256
 257         do
 258         {
 259                 /* rescan with NOP, to wait for the access to complete */
 260                 access = 0;
 261                 nr_w_buf = 0;
 262                 jtag_add_dr_scan(4, fields, -1, NULL);
 263                 jtag_execute_queue();
 264         } while (buf_get_u32(&access, 0, 1) != 1);
 265
 266 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 267         DEBUG("addr: 0x%x value: %8.8x", address, value);
 268 #endif
 269
 270         error_handler.error_handler = arm926ejs_catch_broken_irscan;
 271         error_handler.error_handler_priv = NULL;
 272
 273         arm_jtag_set_instr(jtag_info, 0xf, &error_handler);
 274
 275         return ERROR_OK;
 276 }
 277
 278 int arm926ejs_examine_debug_reason(target_t *target)
 279 {
 280         armv4_5_common_t *armv4_5 = target->arch_info;
 281         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 282         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 283         int debug_reason;
 284         int retval;
 285
 286         embeddedice_read_reg(dbg_stat);
 287         if ((retval = jtag_execute_queue()) != ERROR_OK)
 288                 return retval;
 289
 290         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 291
 292         switch (debug_reason)
 293         {
 294                 case 1:
 295                         DEBUG("breakpoint from EICE unit 0");
 296                         target->debug_reason = DBG_REASON_BREAKPOINT;
 297                         break;
 298                 case 2:
 299                         DEBUG("breakpoint from EICE unit 1");
 300                         target->debug_reason = DBG_REASON_BREAKPOINT;
 301                         break;
 302                 case 3:
 303                         DEBUG("soft breakpoint (BKPT instruction)");
 304                         target->debug_reason = DBG_REASON_BREAKPOINT;
 305                         break;
 306                 case 4:
 307                         DEBUG("vector catch breakpoint");
 308                         target->debug_reason = DBG_REASON_BREAKPOINT;
 309                         break;
 310                 case 5:
 311                         DEBUG("external breakpoint");
 312                         target->debug_reason = DBG_REASON_BREAKPOINT;
 313                         break;
 314                 case 6:
 315                         DEBUG("watchpoint from EICE unit 0");
 316                         target->debug_reason = DBG_REASON_WATCHPOINT;
 317                         break;
 318                 case 7:
 319                         DEBUG("watchpoint from EICE unit 1");
 320                         target->debug_reason = DBG_REASON_WATCHPOINT;
 321                         break;
 322                 case 8:
 323                         DEBUG("external watchpoint");
 324                         target->debug_reason = DBG_REASON_WATCHPOINT;
 325                         break;
 326                 case 9:
 327                         DEBUG("internal debug request");
 328                         target->debug_reason = DBG_REASON_DBGRQ;
 329                         break;
 330                 case 10:
 331                         DEBUG("external debug request");
 332                         target->debug_reason = DBG_REASON_DBGRQ;
 333                         break;
 334                 case 11:
 335                         ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 336                         break;
 337                 default:
 338                         ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 339                         target->debug_reason = DBG_REASON_DBGRQ;
 340         }
 341
 342         return ERROR_OK;
 343 }
 344
 345 u32 arm926ejs_get_ttb(target_t *target)
 346 {
 347         int retval;
 348         u32 ttb = 0x0;
 349
 350         if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb)) != ERROR_OK)
 351                 return retval;
 352
 353         return ttb;
 354 }
 355
 356 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 357 {
 358         u32 cp15_control;
 359
 360         /* read cp15 control register */
 361         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
 362         jtag_execute_queue();
 363
 364         if (mmu)
 365         {
 366                 /* invalidate TLB */
 367                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0);
 368
 369                 cp15_control &= ~0x1U;
 370         }
 371
 372         if (d_u_cache)
 373         {
 374                 u32 debug_override;
 375                 /* read-modify-write CP15 debug override register
 376                  * to enable "test and clean all" */
 377                 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override);
 378                 debug_override |= 0x80000;
 379                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
 380
 381                 /* clean and invalidate DCache */
 382                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
 383
 384                 /* write CP15 debug override register
 385                  * to disable "test and clean all" */
 386                 debug_override &= ~0x80000;
 387                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
 388
 389                 cp15_control &= ~0x4U;
 390         }
 391
 392         if (i_cache)
 393         {
 394                 /* invalidate ICache */
 395                 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
 396
 397                 cp15_control &= ~0x1000U;
 398         }
 399
 400         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
 401 }
 402
 403 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 404 {
 405         u32 cp15_control;
 406
 407         /* read cp15 control register */
 408         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
 409         jtag_execute_queue();
 410
 411         if (mmu)
 412                 cp15_control |= 0x1U;
 413
 414         if (d_u_cache)
 415                 cp15_control |= 0x4U;
 416
 417         if (i_cache)
 418                 cp15_control |= 0x1000U;
 419
 420         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
 421 }
 422
 423 void arm926ejs_post_debug_entry(target_t *target)
 424 {
 425         armv4_5_common_t *armv4_5 = target->arch_info;
 426         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 427         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 428         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 429
 430         /* examine cp15 control reg */
 431         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg);
 432         jtag_execute_queue();
 433         DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 434
 435         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 436         {
 437                 u32 cache_type_reg;
 438                 /* identify caches */
 439                 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg);
 440                 jtag_execute_queue();
 441                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 442         }
 443
 444         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 445         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 446         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 447
 448         /* save i/d fault status and address register */
 449         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs->d_fsr);
 450         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs->i_fsr);
 451         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs->d_far);
 452
 453         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 454                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 455
 456
 457         u32 cache_dbg_ctrl;
 458
 459         /* read-modify-write CP15 cache debug control register
 460          * to disable I/D-cache linefills and force WT */
 461         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
 462         cache_dbg_ctrl |= 0x7;
 463         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 464 }
 465
 466 void arm926ejs_pre_restore_context(target_t *target)
 467 {
 468         armv4_5_common_t *armv4_5 = target->arch_info;
 469         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 470         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 471         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 472
 473         /* restore i/d fault status and address register */
 474         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr);
 475         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr);
 476         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs->d_far);
 477
 478         u32 cache_dbg_ctrl;
 479
 480         /* read-modify-write CP15 cache debug control register
 481          * to reenable I/D-cache linefills and disable WT */
 482         arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
 483         cache_dbg_ctrl &= ~0x7;
 484         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 485 }
 486
 487 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 488 {
 489         armv4_5_common_t *armv4_5 = target->arch_info;
 490         arm7_9_common_t *arm7_9;
 491         arm9tdmi_common_t *arm9tdmi;
 492         arm926ejs_common_t *arm926ejs;
 493
 494         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 495         {
 496                 return -1;
 497         }
 498
 499         arm7_9 = armv4_5->arch_info;
 500         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 501         {
 502                 return -1;
 503         }
 504
 505         arm9tdmi = arm7_9->arch_info;
 506         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 507         {
 508                 return -1;
 509         }
 510
 511         arm926ejs = arm9tdmi->arch_info;
 512         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 513         {
 514                 return -1;
 515         }
 516
 517         *armv4_5_p = armv4_5;
 518         *arm7_9_p = arm7_9;
 519         *arm9tdmi_p = arm9tdmi;
 520         *arm926ejs_p = arm926ejs;
 521
 522         return ERROR_OK;
 523 }
 524
 525 int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
 526 {
 527         armv4_5_common_t *armv4_5 = target->arch_info;
 528         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 529         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 530         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 531
 532         char *state[] =
 533         {
 534                 "disabled", "enabled"
 535         };
 536
 537         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 538         {
 539                 ERROR("BUG: called for a non-ARMv4/5 target");
 540                 exit(-1);
 541         }
 542
 543         snprintf(buf, buf_size,
 544                         "target halted in %s state due to %s, current mode: %s\n"
 545                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 546                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 547                          armv4_5_state_strings[armv4_5->core_state],
 548                          target_debug_reason_strings[target->debug_reason],
 549                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 550                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 551                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 552                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 553                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 554                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 555
 556         return ERROR_OK;
 557 }
 558
 559 int arm926ejs_soft_reset_halt(struct target_s *target)
 560 {
 561         armv4_5_common_t *armv4_5 = target->arch_info;
 562         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 563         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 564         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 565         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 566
 567         if (target->state == TARGET_RUNNING)
 568         {
 569                 target->type->halt(target);
 570         }
 571
 572         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 573         {
 574                 embeddedice_read_reg(dbg_stat);
 575                 jtag_execute_queue();
 576         }
 577
 578         target->state = TARGET_HALTED;
 579
 580         /* SVC, ARM state, IRQ and FIQ disabled */
 581         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 582         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 583         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 584
 585         /* start fetching from 0x0 */
 586         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 587         armv4_5->core_cache->reg_list[15].dirty = 1;
 588         armv4_5->core_cache->reg_list[15].valid = 1;
 589
 590         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 591         armv4_5->core_state = ARMV4_5_STATE_ARM;
 592
 593         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 594         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 595         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 596         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 597
 598         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 599
 600         return ERROR_OK;
 601 }
 602
 603 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 604 {
 605         int retval;
 606         armv4_5_common_t *armv4_5 = target->arch_info;
 607         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 608         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 609         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 610
 611         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 612                 return retval;
 613
 614         /* If ICache is enabled, we have to invalidate affected ICache lines
 615          * the DCache is forced to write-through, so we don't have to clean it here
 616          */
 617         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 618         {
 619                 if (count <= 1)
 620                 {
 621                         /* invalidate ICache single entry with MVA */
 622                         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address);
 623                 }
 624                 else
 625                 {
 626                         /* invalidate ICache */
 627                         arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address);
 628                 }
 629         }
 630
 631         return retval;
 632 }
 633
 634 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 635 {
 636         arm9tdmi_init_target(cmd_ctx, target);
 637
 638         return ERROR_OK;
 639
 640 }
 641
 642 int arm926ejs_quit()
 643 {
 644
 645         return ERROR_OK;
 646 }
 647
 648 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
 649 {
 650         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 651         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 652
 653         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 654          */
 655         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 656
 657         arm9tdmi->arch_info = arm926ejs;
 658         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 659
 660         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 661         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 662
 663         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 664         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 665         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 666         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 667         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 668         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 669         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 670         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 671
 672         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 673
 674         /* The ARM926EJ-S implements the ARMv5TE architecture which
 675          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 676          */
 677         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 678         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 679
 680         arm7_9->sw_bkpts_use_wp = 0;
 681         arm7_9->sw_bkpts_enabled = 1;
 682
 683         return ERROR_OK;
 684 }
 685
 686 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 687 {
 688         int chain_pos;
 689         char *variant = NULL;
 690         arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
 691
 692         if (argc < 4)
 693         {
 694                 ERROR("'target arm926ejs' requires at least one additional argument");
 695                 exit(-1);
 696         }
 697
 698         chain_pos = strtoul(args[3], NULL, 0);
 699
 700         if (argc >= 5)
 701                 variant = args[4];
 702
 703         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 704
 705         arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
 706
 707         return ERROR_OK;
 708 }
 709
 710 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 711 {
 712         int retval;
 713         command_t *arm926ejs_cmd;
 714
 715
 716         retval = arm9tdmi_register_commands(cmd_ctx);
 717
 718         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 719
 720         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 721
 722         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 723         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 724
 725         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 726         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 727         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 728
 729         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 730         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 731         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 732
 733         return ERROR_OK;
 734 }
 735
 736 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 737 {
 738         int retval;
 739         target_t *target = get_current_target(cmd_ctx);
 740         armv4_5_common_t *armv4_5;
 741         arm7_9_common_t *arm7_9;
 742         arm9tdmi_common_t *arm9tdmi;
 743         arm926ejs_common_t *arm926ejs;
 744         int opcode_1;
 745         int opcode_2;
 746         int CRn;
 747         int CRm;
 748
 749         if ((argc < 4) || (argc > 5))
 750         {
 751                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 752                 return ERROR_OK;
 753         }
 754
 755         opcode_1 = strtoul(args[0], NULL, 0);
 756         opcode_2 = strtoul(args[1], NULL, 0);
 757         CRn = strtoul(args[2], NULL, 0);
 758         CRm = strtoul(args[3], NULL, 0);
 759
 760         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 761         {
 762                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 763                 return ERROR_OK;
 764         }
 765
 766         if (target->state != TARGET_HALTED)
 767         {
 768                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 769                 return ERROR_OK;
 770         }
 771
 772         if (argc == 4)
 773         {
 774                 u32 value;
 775                 if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), &value)) != ERROR_OK)
 776                 {
 777                         command_print(cmd_ctx, "couldn't access register");
 778                         return ERROR_OK;
 779                 }
 780                 jtag_execute_queue();
 781
 782                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 783         }
 784         else
 785         {
 786                 u32 value = strtoul(args[4], NULL, 0);
 787                 if ((retval = arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), value)) != ERROR_OK)
 788                 {
 789                         command_print(cmd_ctx, "couldn't access register");
 790                         return ERROR_OK;
 791                 }
 792                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 793         }
 794
 795         return ERROR_OK;
 796 }
 797
 798 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 799 {
 800         target_t *target = get_current_target(cmd_ctx);
 801         armv4_5_common_t *armv4_5;
 802         arm7_9_common_t *arm7_9;
 803         arm9tdmi_common_t *arm9tdmi;
 804         arm926ejs_common_t *arm926ejs;
 805
 806         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 807         {
 808                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 809                 return ERROR_OK;
 810         }
 811
 812         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 813 }
 814
 815 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 816 {
 817         target_t *target = get_current_target(cmd_ctx);
 818         armv4_5_common_t *armv4_5;
 819         arm7_9_common_t *arm7_9;
 820         arm9tdmi_common_t *arm9tdmi;
 821         arm926ejs_common_t *arm926ejs;
 822         arm_jtag_t *jtag_info;
 823
 824         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 825         {
 826                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 827                 return ERROR_OK;
 828         }
 829
 830         jtag_info = &arm7_9->jtag_info;
 831
 832         if (target->state != TARGET_HALTED)
 833         {
 834                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 835                 return ERROR_OK;
 836         }
 837
 838         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 839 }
 840
 841 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 842 {
 843         target_t *target = get_current_target(cmd_ctx);
 844         armv4_5_common_t *armv4_5;
 845         arm7_9_common_t *arm7_9;
 846         arm9tdmi_common_t *arm9tdmi;
 847         arm926ejs_common_t *arm926ejs;
 848         arm_jtag_t *jtag_info;
 849
 850         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 851         {
 852                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 853                 return ERROR_OK;
 854         }
 855
 856         jtag_info = &arm7_9->jtag_info;
 857
 858         if (target->state != TARGET_HALTED)
 859         {
 860                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 861                 return ERROR_OK;
 862         }
 863
 864         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 865 }
 866
 867 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 868 {
 869         target_t *target = get_current_target(cmd_ctx);
 870         armv4_5_common_t *armv4_5;
 871         arm7_9_common_t *arm7_9;
 872         arm9tdmi_common_t *arm9tdmi;
 873         arm926ejs_common_t *arm926ejs;
 874         arm_jtag_t *jtag_info;
 875
 876         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 877         {
 878                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 879                 return ERROR_OK;
 880         }
 881
 882         jtag_info = &arm7_9->jtag_info;
 883
 884         if (target->state != TARGET_HALTED)
 885         {
 886                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 887                 return ERROR_OK;
 888         }
 889
 890         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 891 }