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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27 #include "time_support.h"
  28
  29 #include <stdlib.h>
  30 #include <string.h>
  31
  32 #if 0
  33 #define _DEBUG_INSTRUCTION_EXECUTION_
  34 #endif
  35
  36 /* cli handling */
  37 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
  38
  39 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  45
  46 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  48
  49 /* forward declarations */
  50 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  51 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  52 int arm926ejs_quit(void);
  53 int arm926ejs_arch_state(struct target_s *target);
  54 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  56 int arm926ejs_soft_reset_halt(struct target_s *target);
  57 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
  58 static int arm926ejs_mmu(struct target_s *target, int *enabled);
  59
  60 target_type_t arm926ejs_target =
  61 {
  62         .name = "arm926ejs",
  63
  64         .poll = arm7_9_poll,
  65         .arch_state = arm926ejs_arch_state,
  66
  67         .target_request_data = arm7_9_target_request_data,
  68
  69         .halt = arm7_9_halt,
  70         .resume = arm7_9_resume,
  71         .step = arm7_9_step,
  72
  73         .assert_reset = arm7_9_assert_reset,
  74         .deassert_reset = arm7_9_deassert_reset,
  75         .soft_reset_halt = arm926ejs_soft_reset_halt,
  76
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  78
  79         .read_memory = arm7_9_read_memory,
  80         .write_memory = arm926ejs_write_memory,
  81         .bulk_write_memory = arm7_9_bulk_write_memory,
  82         .checksum_memory = arm7_9_checksum_memory,
  83         .blank_check_memory = arm7_9_blank_check_memory,
  84
  85         .run_algorithm = armv4_5_run_algorithm,
  86
  87         .add_breakpoint = arm7_9_add_breakpoint,
  88         .remove_breakpoint = arm7_9_remove_breakpoint,
  89         .add_watchpoint = arm7_9_add_watchpoint,
  90         .remove_watchpoint = arm7_9_remove_watchpoint,
  91
  92         .register_commands = arm926ejs_register_commands,
  93         .target_create = arm926ejs_target_create,
  94         .init_target = arm926ejs_init_target,
  95         .examine = arm9tdmi_examine,
  96         .quit = arm926ejs_quit,
  97         .virt2phys = arm926ejs_virt2phys,
  98         .mmu = arm926ejs_mmu
  99 };
 100
 101
 102 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 103 {
 104         /* The ARM926EJ-S' instruction register is 4 bits wide */
 105         u8 t = *captured & 0xf;
 106         u8 t2 = *field->in_check_value & 0xf;
 107         if (t == t2)
 108         {
 109                 return ERROR_OK;
 110         }
 111         else if ((t == 0x0f) || (t == 0x00))
 112         {
 113                 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 114                 return ERROR_OK;
 115         }
 116         return ERROR_JTAG_QUEUE_FAILED;;
 117 }
 118
 119 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
 120
 121 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
 122 {
 123         int retval = ERROR_OK;
 124         armv4_5_common_t *armv4_5 = target->arch_info;
 125         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 126         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 127         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 128         scan_field_t fields[4];
 129         u8 address_buf[2];
 130         u8 nr_w_buf = 0;
 131         u8 access = 1;
 132
 133         buf_set_u32(address_buf, 0, 14, address);
 134
 135         jtag_add_end_state(TAP_RTI);
 136         if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 137         {
 138                 return retval;
 139         }
 140         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 141
 142         fields[0].device = jtag_info->chain_pos;
 143         fields[0].num_bits = 32;
 144         fields[0].out_value = NULL;
 145         fields[0].out_mask = NULL;
 146         fields[0].in_value = NULL;
 147         fields[0].in_check_value = NULL;
 148         fields[0].in_check_mask = NULL;
 149         fields[0].in_handler = NULL;
 150         fields[0].in_handler_priv = NULL;
 151
 152         fields[1].device = jtag_info->chain_pos;
 153         fields[1].num_bits = 1;
 154         fields[1].out_value = &access;
 155         fields[1].out_mask = NULL;
 156         fields[1].in_value = &access;
 157         fields[1].in_check_value = NULL;
 158         fields[1].in_check_mask = NULL;
 159         fields[1].in_handler = NULL;
 160         fields[1].in_handler_priv = NULL;
 161
 162         fields[2].device = jtag_info->chain_pos;
 163         fields[2].num_bits = 14;
 164         fields[2].out_value = address_buf;
 165         fields[2].out_mask = NULL;
 166         fields[2].in_value = NULL;
 167         fields[2].in_check_value = NULL;
 168         fields[2].in_check_mask = NULL;
 169         fields[2].in_handler = NULL;
 170         fields[2].in_handler_priv = NULL;
 171
 172         fields[3].device = jtag_info->chain_pos;
 173         fields[3].num_bits = 1;
 174         fields[3].out_value = &nr_w_buf;
 175         fields[3].out_mask = NULL;
 176         fields[3].in_value = NULL;
 177         fields[3].in_check_value = NULL;
 178         fields[3].in_check_mask = NULL;
 179         fields[3].in_handler = NULL;
 180         fields[3].in_handler_priv = NULL;
 181
 182         jtag_add_dr_scan(4, fields, -1);
 183
 184         fields[0].in_handler_priv = value;
 185         fields[0].in_handler = arm_jtag_buf_to_u32;
 186
 187         /*TODO: add timeout*/
 188         do
 189         {
 190                 /* rescan with NOP, to wait for the access to complete */
 191                 access = 0;
 192                 nr_w_buf = 0;
 193                 jtag_add_dr_scan(4, fields, -1);
 194                 if((retval = jtag_execute_queue()) != ERROR_OK)
 195                 {
 196                         return retval;
 197                 }
 198         } while (buf_get_u32(&access, 0, 1) != 1);
 199
 200 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 201         LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 202 #endif
 203
 204         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 205
 206         return ERROR_OK;
 207 }
 208
 209 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
 210 {
 211         int retval = ERROR_OK;
 212         armv4_5_common_t *armv4_5 = target->arch_info;
 213         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 214         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 215         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 216         scan_field_t fields[4];
 217         u8 value_buf[4];
 218         u8 address_buf[2];
 219         u8 nr_w_buf = 1;
 220         u8 access = 1;
 221
 222         buf_set_u32(address_buf, 0, 14, address);
 223         buf_set_u32(value_buf, 0, 32, value);
 224
 225         jtag_add_end_state(TAP_RTI);
 226         if((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 227         {
 228                 return retval;
 229         }
 230         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 231
 232         fields[0].device = jtag_info->chain_pos;
 233         fields[0].num_bits = 32;
 234         fields[0].out_value = value_buf;
 235         fields[0].out_mask = NULL;
 236         fields[0].in_value = NULL;
 237         fields[0].in_check_value = NULL;
 238         fields[0].in_check_mask = NULL;
 239         fields[0].in_handler = NULL;
 240         fields[0].in_handler_priv = NULL;
 241
 242         fields[1].device = jtag_info->chain_pos;
 243         fields[1].num_bits = 1;
 244         fields[1].out_value = &access;
 245         fields[1].out_mask = NULL;
 246         fields[1].in_value = &access;
 247         fields[1].in_check_value = NULL;
 248         fields[1].in_check_mask = NULL;
 249         fields[1].in_handler = NULL;
 250         fields[1].in_handler_priv = NULL;
 251
 252         fields[2].device = jtag_info->chain_pos;
 253         fields[2].num_bits = 14;
 254         fields[2].out_value = address_buf;
 255         fields[2].out_mask = NULL;
 256         fields[2].in_value = NULL;
 257         fields[2].in_check_value = NULL;
 258         fields[2].in_check_mask = NULL;
 259         fields[2].in_handler = NULL;
 260         fields[2].in_handler_priv = NULL;
 261
 262         fields[3].device = jtag_info->chain_pos;
 263         fields[3].num_bits = 1;
 264         fields[3].out_value = &nr_w_buf;
 265         fields[3].out_mask = NULL;
 266         fields[3].in_value = NULL;
 267         fields[3].in_check_value = NULL;
 268         fields[3].in_check_mask = NULL;
 269         fields[3].in_handler = NULL;
 270         fields[3].in_handler_priv = NULL;
 271
 272         jtag_add_dr_scan(4, fields, -1);
 273         /*TODO: add timeout*/
 274         do
 275         {
 276                 /* rescan with NOP, to wait for the access to complete */
 277                 access = 0;
 278                 nr_w_buf = 0;
 279                 jtag_add_dr_scan(4, fields, -1);
 280                 if((retval = jtag_execute_queue()) != ERROR_OK)
 281                 {
 282                         return retval;
 283                 }
 284         } while (buf_get_u32(&access, 0, 1) != 1);
 285
 286 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 287         LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 288 #endif
 289
 290         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 291
 292         return ERROR_OK;
 293 }
 294
 295 int arm926ejs_examine_debug_reason(target_t *target)
 296 {
 297         armv4_5_common_t *armv4_5 = target->arch_info;
 298         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 299         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 300         int debug_reason;
 301         int retval;
 302
 303         embeddedice_read_reg(dbg_stat);
 304         if ((retval = jtag_execute_queue()) != ERROR_OK)
 305                 return retval;
 306
 307         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 308
 309         switch (debug_reason)
 310         {
 311                 case 1:
 312                         LOG_DEBUG("breakpoint from EICE unit 0");
 313                         target->debug_reason = DBG_REASON_BREAKPOINT;
 314                         break;
 315                 case 2:
 316                         LOG_DEBUG("breakpoint from EICE unit 1");
 317                         target->debug_reason = DBG_REASON_BREAKPOINT;
 318                         break;
 319                 case 3:
 320                         LOG_DEBUG("soft breakpoint (BKPT instruction)");
 321                         target->debug_reason = DBG_REASON_BREAKPOINT;
 322                         break;
 323                 case 4:
 324                         LOG_DEBUG("vector catch breakpoint");
 325                         target->debug_reason = DBG_REASON_BREAKPOINT;
 326                         break;
 327                 case 5:
 328                         LOG_DEBUG("external breakpoint");
 329                         target->debug_reason = DBG_REASON_BREAKPOINT;
 330                         break;
 331                 case 6:
 332                         LOG_DEBUG("watchpoint from EICE unit 0");
 333                         target->debug_reason = DBG_REASON_WATCHPOINT;
 334                         break;
 335                 case 7:
 336                         LOG_DEBUG("watchpoint from EICE unit 1");
 337                         target->debug_reason = DBG_REASON_WATCHPOINT;
 338                         break;
 339                 case 8:
 340                         LOG_DEBUG("external watchpoint");
 341                         target->debug_reason = DBG_REASON_WATCHPOINT;
 342                         break;
 343                 case 9:
 344                         LOG_DEBUG("internal debug request");
 345                         target->debug_reason = DBG_REASON_DBGRQ;
 346                         break;
 347                 case 10:
 348                         LOG_DEBUG("external debug request");
 349                         target->debug_reason = DBG_REASON_DBGRQ;
 350                         break;
 351                 case 11:
 352                         LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 353                         target->debug_reason = DBG_REASON_DBGRQ;
 354                         break;
 355                 default:
 356                         LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 357                         target->debug_reason = DBG_REASON_DBGRQ;
 358                         break;
 359         }
 360
 361         return retval;
 362 }
 363
 364 u32 arm926ejs_get_ttb(target_t *target)
 365 {
 366         armv4_5_common_t *armv4_5 = target->arch_info;
 367         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 368         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 369         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 370         int retval;
 371         u32 ttb = 0x0;
 372
 373         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
 374                 return retval;
 375
 376         return ttb;
 377 }
 378
 379 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 380 {
 381         armv4_5_common_t *armv4_5 = target->arch_info;
 382         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 383         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 384         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 385         u32 cp15_control;
 386
 387         /* read cp15 control register */
 388         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 389         jtag_execute_queue();
 390
 391         if (mmu)
 392         {
 393                 /* invalidate TLB */
 394                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
 395
 396                 cp15_control &= ~0x1U;
 397         }
 398
 399         if (d_u_cache)
 400         {
 401                 u32 debug_override;
 402                 /* read-modify-write CP15 debug override register
 403                  * to enable "test and clean all" */
 404                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
 405                 debug_override |= 0x80000;
 406                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 407
 408                 /* clean and invalidate DCache */
 409                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 410
 411                 /* write CP15 debug override register
 412                  * to disable "test and clean all" */
 413                 debug_override &= ~0x80000;
 414                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 415
 416                 cp15_control &= ~0x4U;
 417         }
 418
 419         if (i_cache)
 420         {
 421                 /* invalidate ICache */
 422                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 423
 424                 cp15_control &= ~0x1000U;
 425         }
 426
 427         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 428 }
 429
 430 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 431 {
 432         armv4_5_common_t *armv4_5 = target->arch_info;
 433         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 434         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 435         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 436         u32 cp15_control;
 437
 438         /* read cp15 control register */
 439         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 440         jtag_execute_queue();
 441
 442         if (mmu)
 443                 cp15_control |= 0x1U;
 444
 445         if (d_u_cache)
 446                 cp15_control |= 0x4U;
 447
 448         if (i_cache)
 449                 cp15_control |= 0x1000U;
 450
 451         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 452 }
 453
 454 void arm926ejs_post_debug_entry(target_t *target)
 455 {
 456         armv4_5_common_t *armv4_5 = target->arch_info;
 457         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 458         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 459         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 460
 461         /* examine cp15 control reg */
 462         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 463         jtag_execute_queue();
 464         LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 465
 466         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 467         {
 468                 u32 cache_type_reg;
 469                 /* identify caches */
 470                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
 471                 jtag_execute_queue();
 472                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 473         }
 474
 475         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 476         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 477         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 478
 479         /* save i/d fault status and address register */
 480         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
 481         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 482         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 483
 484         LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 485                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 486
 487
 488         u32 cache_dbg_ctrl;
 489
 490         /* read-modify-write CP15 cache debug control register
 491          * to disable I/D-cache linefills and force WT */
 492         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 493         cache_dbg_ctrl |= 0x7;
 494         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 495 }
 496
 497 void arm926ejs_pre_restore_context(target_t *target)
 498 {
 499         armv4_5_common_t *armv4_5 = target->arch_info;
 500         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 501         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 502         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 503
 504         /* restore i/d fault status and address register */
 505         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
 506         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
 507         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
 508
 509         u32 cache_dbg_ctrl;
 510
 511         /* read-modify-write CP15 cache debug control register
 512          * to reenable I/D-cache linefills and disable WT */
 513         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 514         cache_dbg_ctrl &= ~0x7;
 515         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 516 }
 517
 518 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 519 {
 520         armv4_5_common_t *armv4_5 = target->arch_info;
 521         arm7_9_common_t *arm7_9;
 522         arm9tdmi_common_t *arm9tdmi;
 523         arm926ejs_common_t *arm926ejs;
 524
 525         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 526         {
 527                 return -1;
 528         }
 529
 530         arm7_9 = armv4_5->arch_info;
 531         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 532         {
 533                 return -1;
 534         }
 535
 536         arm9tdmi = arm7_9->arch_info;
 537         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 538         {
 539                 return -1;
 540         }
 541
 542         arm926ejs = arm9tdmi->arch_info;
 543         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 544         {
 545                 return -1;
 546         }
 547
 548         *armv4_5_p = armv4_5;
 549         *arm7_9_p = arm7_9;
 550         *arm9tdmi_p = arm9tdmi;
 551         *arm926ejs_p = arm926ejs;
 552
 553         return ERROR_OK;
 554 }
 555
 556 int arm926ejs_arch_state(struct target_s *target)
 557 {
 558         armv4_5_common_t *armv4_5 = target->arch_info;
 559         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 560         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 561         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 562
 563         char *state[] =
 564         {
 565                 "disabled", "enabled"
 566         };
 567
 568         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 569         {
 570                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 571                 exit(-1);
 572         }
 573
 574         LOG_USER(
 575                         "target halted in %s state due to %s, current mode: %s\n"
 576                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 577                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 578                          armv4_5_state_strings[armv4_5->core_state],
 579                          Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 580                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 581                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 582                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 583                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 584                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 585                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 586
 587         return ERROR_OK;
 588 }
 589
 590 int arm926ejs_soft_reset_halt(struct target_s *target)
 591 {
 592         int retval = ERROR_OK;
 593         armv4_5_common_t *armv4_5 = target->arch_info;
 594         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 595         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 596         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 597         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 598
 599         if((retval = target_halt(target)) != ERROR_OK)
 600         {
 601                 return retval;
 602         }
 603
 604         long long then=timeval_ms();
 605         int timeout;
 606         while (!(timeout=((timeval_ms()-then)>1000)))
 607         {
 608                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 609                 {
 610                         embeddedice_read_reg(dbg_stat);
 611                         if((retval = jtag_execute_queue()) != ERROR_OK)
 612                         {
 613                                 return retval;
 614                         }
 615                 }  else
 616                 {
 617                         break;
 618                 }
 619                 if (debug_level>=1)
 620                 {
 621                         /* do not eat all CPU, time out after 1 se*/
 622                         alive_sleep(100);
 623                 } else
 624                 {
 625                         keep_alive();
 626                 }
 627         }
 628         if (timeout)
 629         {
 630                 LOG_ERROR("Failed to halt CPU after 1 sec");
 631                 return ERROR_TARGET_TIMEOUT;
 632         }
 633
 634         target->state = TARGET_HALTED;
 635
 636         /* SVC, ARM state, IRQ and FIQ disabled */
 637         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 638         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 639         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 640
 641         /* start fetching from 0x0 */
 642         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 643         armv4_5->core_cache->reg_list[15].dirty = 1;
 644         armv4_5->core_cache->reg_list[15].valid = 1;
 645
 646         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 647         armv4_5->core_state = ARMV4_5_STATE_ARM;
 648
 649         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 650         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 651         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 652         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 653
 654         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 655
 656 }
 657
 658 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 659 {
 660         int retval;
 661         armv4_5_common_t *armv4_5 = target->arch_info;
 662         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 663         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 664         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 665
 666         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 667                 return retval;
 668
 669         /* If ICache is enabled, we have to invalidate affected ICache lines
 670          * the DCache is forced to write-through, so we don't have to clean it here
 671          */
 672         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 673         {
 674                 if (count <= 1)
 675                 {
 676                         /* invalidate ICache single entry with MVA */
 677                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
 678                 }
 679                 else
 680                 {
 681                         /* invalidate ICache */
 682                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
 683                 }
 684         }
 685
 686         return retval;
 687 }
 688
 689 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 690 {
 691         arm9tdmi_init_target(cmd_ctx, target);
 692
 693         return ERROR_OK;
 694
 695 }
 696
 697 int arm926ejs_quit(void)
 698 {
 699
 700         return ERROR_OK;
 701 }
 702
 703 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, const char *variant)
 704 {
 705         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 706         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 707
 708         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 709          */
 710         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 711
 712         arm9tdmi->arch_info = arm926ejs;
 713         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 714
 715         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 716         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 717
 718         arm926ejs->read_cp15 = arm926ejs_cp15_read;
 719         arm926ejs->write_cp15 = arm926ejs_cp15_write;
 720         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 721         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 722         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 723         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 724         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 725         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 726         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 727         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 728
 729         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 730
 731         /* The ARM926EJ-S implements the ARMv5TE architecture which
 732          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 733          */
 734         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 735         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 736
 737         return ERROR_OK;
 738 }
 739
 740 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 741 {
 742         arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 743
 744         arm926ejs_init_arch_info(target, arm926ejs, target->chain_position, target->variant);
 745
 746         return ERROR_OK;
 747 }
 748
 749 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 750 {
 751         int retval;
 752         command_t *arm926ejs_cmd;
 753
 754
 755         retval = arm9tdmi_register_commands(cmd_ctx);
 756
 757         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 758
 759         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 760
 761         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 762         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 763
 764         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 765         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 766         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 767
 768         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 769         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 770         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 771
 772         return retval;
 773 }
 774
 775 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 776 {
 777         int retval;
 778         target_t *target = get_current_target(cmd_ctx);
 779         armv4_5_common_t *armv4_5;
 780         arm7_9_common_t *arm7_9;
 781         arm9tdmi_common_t *arm9tdmi;
 782         arm926ejs_common_t *arm926ejs;
 783         int opcode_1;
 784         int opcode_2;
 785         int CRn;
 786         int CRm;
 787
 788         if ((argc < 4) || (argc > 5))
 789         {
 790                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 791                 return ERROR_OK;
 792         }
 793
 794         opcode_1 = strtoul(args[0], NULL, 0);
 795         opcode_2 = strtoul(args[1], NULL, 0);
 796         CRn = strtoul(args[2], NULL, 0);
 797         CRm = strtoul(args[3], NULL, 0);
 798
 799         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 800         {
 801                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 802                 return ERROR_OK;
 803         }
 804
 805         if (target->state != TARGET_HALTED)
 806         {
 807                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 808                 return ERROR_OK;
 809         }
 810
 811         if (argc == 4)
 812         {
 813                 u32 value;
 814                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
 815                 {
 816                         command_print(cmd_ctx, "couldn't access register");
 817                         return ERROR_OK;
 818                 }
 819                 if((retval = jtag_execute_queue()) != ERROR_OK)
 820                 {
 821                         return retval;
 822                 }
 823
 824                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 825         }
 826         else
 827         {
 828                 u32 value = strtoul(args[4], NULL, 0);
 829                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
 830                 {
 831                         command_print(cmd_ctx, "couldn't access register");
 832                         return ERROR_OK;
 833                 }
 834                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 835         }
 836
 837         return ERROR_OK;
 838 }
 839
 840 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 841 {
 842         target_t *target = get_current_target(cmd_ctx);
 843         armv4_5_common_t *armv4_5;
 844         arm7_9_common_t *arm7_9;
 845         arm9tdmi_common_t *arm9tdmi;
 846         arm926ejs_common_t *arm926ejs;
 847
 848         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 849         {
 850                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 851                 return ERROR_OK;
 852         }
 853
 854         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 855 }
 856
 857 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 858 {
 859         target_t *target = get_current_target(cmd_ctx);
 860         armv4_5_common_t *armv4_5;
 861         arm7_9_common_t *arm7_9;
 862         arm9tdmi_common_t *arm9tdmi;
 863         arm926ejs_common_t *arm926ejs;
 864         arm_jtag_t *jtag_info;
 865
 866         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 867         {
 868                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 869                 return ERROR_OK;
 870         }
 871
 872         jtag_info = &arm7_9->jtag_info;
 873
 874         if (target->state != TARGET_HALTED)
 875         {
 876                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 877                 return ERROR_OK;
 878         }
 879
 880         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 881 }
 882
 883 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 884 {
 885         target_t *target = get_current_target(cmd_ctx);
 886         armv4_5_common_t *armv4_5;
 887         arm7_9_common_t *arm7_9;
 888         arm9tdmi_common_t *arm9tdmi;
 889         arm926ejs_common_t *arm926ejs;
 890         arm_jtag_t *jtag_info;
 891
 892         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 893         {
 894                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 895                 return ERROR_OK;
 896         }
 897
 898         jtag_info = &arm7_9->jtag_info;
 899
 900         if (target->state != TARGET_HALTED)
 901         {
 902                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 903                 return ERROR_OK;
 904         }
 905
 906         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 907 }
 908
 909 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 910 {
 911         target_t *target = get_current_target(cmd_ctx);
 912         armv4_5_common_t *armv4_5;
 913         arm7_9_common_t *arm7_9;
 914         arm9tdmi_common_t *arm9tdmi;
 915         arm926ejs_common_t *arm926ejs;
 916         arm_jtag_t *jtag_info;
 917
 918         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 919         {
 920                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 921                 return ERROR_OK;
 922         }
 923
 924         jtag_info = &arm7_9->jtag_info;
 925
 926         if (target->state != TARGET_HALTED)
 927         {
 928                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 929                 return ERROR_OK;
 930         }
 931
 932         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 933 }
 934 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 935 {
 936         int retval;
 937         int type;
 938         u32 cb;
 939         int domain;
 940         u32 ap;
 941
 942         armv4_5_common_t *armv4_5;
 943         arm7_9_common_t *arm7_9;
 944         arm9tdmi_common_t *arm9tdmi;
 945         arm926ejs_common_t *arm926ejs;
 946         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
 947         if (retval != ERROR_OK)
 948         {
 949                 return retval;
 950         }
 951         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 952         if (type == -1)
 953         {
 954                 return ret;
 955         }
 956         *physical = ret;
 957         return ERROR_OK;
 958 }
 959
 960 static int arm926ejs_mmu(struct target_s *target, int *enabled)
 961 {
 962         armv4_5_common_t *armv4_5 = target->arch_info;
 963         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
 964
 965         if (target->state != TARGET_HALTED)
 966         {
 967                 LOG_ERROR("Target not halted");
 968                 return ERROR_TARGET_INVALID;
 969         }
 970         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
 971         return ERROR_OK;
 972 }