marked infinite loop in code w/TODO and fixed warning.
[fw/openocd] / src / target / arm926ejs.c
1 /***************************************************************************
2  *   Copyright (C) 2007 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   This program is free software; you can redistribute it and/or modify  *
6  *   it under the terms of the GNU General Public License as published by  *
7  *   the Free Software Foundation; either version 2 of the License, or     *
8  *   (at your option) any later version.                                   *
9  *                                                                         *
10  *   This program is distributed in the hope that it will be useful,       *
11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
13  *   GNU General Public License for more details.                          *
14  *                                                                         *
15  *   You should have received a copy of the GNU General Public License     *
16  *   along with this program; if not, write to the                         *
17  *   Free Software Foundation, Inc.,                                       *
18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
19  ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "arm926ejs.h"
25 #include "jtag.h"
26 #include "log.h"
27
28 #include <stdlib.h>
29 #include <string.h>
30
31 #if 1
32 #define _DEBUG_INSTRUCTION_EXECUTION_
33 #endif
34
35 /* cli handling */
36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
37
38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44
45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47
48 /* forward declarations */
49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm926ejs_quit();
52 int arm926ejs_arch_state(struct target_s *target);
53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm926ejs_soft_reset_halt(struct target_s *target);
56 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
57 static int arm926ejs_mmu(struct target_s *target, int *enabled);
58
59 target_type_t arm926ejs_target =
60 {
61         .name = "arm926ejs",
62
63         .poll = arm7_9_poll,
64         .arch_state = arm926ejs_arch_state,
65
66         .target_request_data = arm7_9_target_request_data,
67
68         .halt = arm7_9_halt,
69         .resume = arm7_9_resume,
70         .step = arm7_9_step,
71
72         .assert_reset = arm7_9_assert_reset,
73         .deassert_reset = arm7_9_deassert_reset,
74         .soft_reset_halt = arm926ejs_soft_reset_halt,
75         .prepare_reset_halt = arm7_9_prepare_reset_halt,
76         
77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78
79         .read_memory = arm7_9_read_memory,
80         .write_memory = arm926ejs_write_memory,
81         .bulk_write_memory = arm7_9_bulk_write_memory,
82         .checksum_memory = arm7_9_checksum_memory,
83         
84         .run_algorithm = armv4_5_run_algorithm,
85
86         .add_breakpoint = arm7_9_add_breakpoint,
87         .remove_breakpoint = arm7_9_remove_breakpoint,
88         .add_watchpoint = arm7_9_add_watchpoint,
89         .remove_watchpoint = arm7_9_remove_watchpoint,
90
91         .register_commands = arm926ejs_register_commands,
92         .target_command = arm926ejs_target_command,
93         .init_target = arm926ejs_init_target,
94         .quit = arm926ejs_quit,
95         .virt2phys = arm926ejs_virt2phys,
96         .mmu = arm926ejs_mmu
97 };
98
99
100 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
101 {
102         /* The ARM926EJ-S' instruction register is 4 bits wide */
103         u8 t = *captured & 0xf;
104         u8 t2 = *field->in_check_value & 0xf;
105         if (t == t2)
106         {
107                 return ERROR_OK;
108         }
109         else if ((t == 0x0f) || (t == 0x00))
110         {
111                 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
112                 return ERROR_OK;
113         }
114         return ERROR_JTAG_QUEUE_FAILED;;
115 }
116
117 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
118
119 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
120 {
121         armv4_5_common_t *armv4_5 = target->arch_info;
122         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
123         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
124         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
125         scan_field_t fields[4];
126         u8 address_buf[2];
127         u8 nr_w_buf = 0;
128         u8 access = 1;
129         
130         buf_set_u32(address_buf, 0, 14, address);
131         
132         jtag_add_end_state(TAP_RTI);
133         arm_jtag_scann(jtag_info, 0xf);
134         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
135
136         fields[0].device = jtag_info->chain_pos;
137         fields[0].num_bits = 32;
138         fields[0].out_value = NULL;
139         fields[0].out_mask = NULL;
140         fields[0].in_value = NULL;
141         fields[0].in_check_value = NULL;
142         fields[0].in_check_mask = NULL;
143         fields[0].in_handler = NULL;
144         fields[0].in_handler_priv = NULL;
145
146         fields[1].device = jtag_info->chain_pos;
147         fields[1].num_bits = 1;
148         fields[1].out_value = &access;
149         fields[1].out_mask = NULL;
150         fields[1].in_value = &access;
151         fields[1].in_check_value = NULL;
152         fields[1].in_check_mask = NULL;
153         fields[1].in_handler = NULL;
154         fields[1].in_handler_priv = NULL;
155
156         fields[2].device = jtag_info->chain_pos;
157         fields[2].num_bits = 14;
158         fields[2].out_value = address_buf;
159         fields[2].out_mask = NULL;
160         fields[2].in_value = NULL;
161         fields[2].in_check_value = NULL;
162         fields[2].in_check_mask = NULL;
163         fields[2].in_handler = NULL;
164         fields[2].in_handler_priv = NULL;
165
166         fields[3].device = jtag_info->chain_pos;
167         fields[3].num_bits = 1;
168         fields[3].out_value = &nr_w_buf;
169         fields[3].out_mask = NULL;
170         fields[3].in_value = NULL;
171         fields[3].in_check_value = NULL;
172         fields[3].in_check_mask = NULL;
173         fields[3].in_handler = NULL;
174         fields[3].in_handler_priv = NULL;
175         
176         jtag_add_dr_scan(4, fields, -1);
177
178         fields[0].in_handler_priv = value;
179         fields[0].in_handler = arm_jtag_buf_to_u32;
180         
181         /*TODO: add timeout*/
182         do
183         {
184                 /* rescan with NOP, to wait for the access to complete */
185                 access = 0;
186                 nr_w_buf = 0;
187                 jtag_add_dr_scan(4, fields, -1);
188                 jtag_execute_queue();
189         } while (buf_get_u32(&access, 0, 1) != 1);
190
191 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
192         DEBUG("addr: 0x%x value: %8.8x", address, *value);
193 #endif
194         
195         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
196
197         return ERROR_OK;
198 }
199
200 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
201 {
202         armv4_5_common_t *armv4_5 = target->arch_info;
203         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
204         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
205         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
206         scan_field_t fields[4];
207         u8 value_buf[4];
208         u8 address_buf[2];
209         u8 nr_w_buf = 1;
210         u8 access = 1;
211         
212         buf_set_u32(address_buf, 0, 14, address);
213         buf_set_u32(value_buf, 0, 32, value);
214         
215         jtag_add_end_state(TAP_RTI);
216         arm_jtag_scann(jtag_info, 0xf);
217         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
218
219         fields[0].device = jtag_info->chain_pos;
220         fields[0].num_bits = 32;
221         fields[0].out_value = value_buf;
222         fields[0].out_mask = NULL;
223         fields[0].in_value = NULL;
224         fields[0].in_check_value = NULL;
225         fields[0].in_check_mask = NULL;
226         fields[0].in_handler = NULL;
227         fields[0].in_handler_priv = NULL;
228
229         fields[1].device = jtag_info->chain_pos;
230         fields[1].num_bits = 1;
231         fields[1].out_value = &access;
232         fields[1].out_mask = NULL;
233         fields[1].in_value = &access;
234         fields[1].in_check_value = NULL;
235         fields[1].in_check_mask = NULL;
236         fields[1].in_handler = NULL;
237         fields[1].in_handler_priv = NULL;
238
239         fields[2].device = jtag_info->chain_pos;
240         fields[2].num_bits = 14;
241         fields[2].out_value = address_buf;
242         fields[2].out_mask = NULL;
243         fields[2].in_value = NULL;
244         fields[2].in_check_value = NULL;
245         fields[2].in_check_mask = NULL;
246         fields[2].in_handler = NULL;
247         fields[2].in_handler_priv = NULL;
248
249         fields[3].device = jtag_info->chain_pos;
250         fields[3].num_bits = 1;
251         fields[3].out_value = &nr_w_buf;
252         fields[3].out_mask = NULL;
253         fields[3].in_value = NULL;
254         fields[3].in_check_value = NULL;
255         fields[3].in_check_mask = NULL;
256         fields[3].in_handler = NULL;
257         fields[3].in_handler_priv = NULL;
258         
259         jtag_add_dr_scan(4, fields, -1);
260         /*TODO: add timeout*/
261         do
262         {
263                 /* rescan with NOP, to wait for the access to complete */
264                 access = 0;
265                 nr_w_buf = 0;
266                 jtag_add_dr_scan(4, fields, -1);
267                 jtag_execute_queue();
268         } while (buf_get_u32(&access, 0, 1) != 1);
269
270 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
271         DEBUG("addr: 0x%x value: %8.8x", address, value);
272 #endif
273
274         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
275
276         return ERROR_OK;
277 }
278
279 int arm926ejs_examine_debug_reason(target_t *target)
280 {
281         armv4_5_common_t *armv4_5 = target->arch_info;
282         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
283         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
284         int debug_reason;
285         int retval;
286
287         embeddedice_read_reg(dbg_stat);
288         if ((retval = jtag_execute_queue()) != ERROR_OK)
289                 return retval;
290         
291         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
292         
293         switch (debug_reason)
294         {
295                 case 1:
296                         DEBUG("breakpoint from EICE unit 0");
297                         target->debug_reason = DBG_REASON_BREAKPOINT;
298                         break;
299                 case 2:
300                         DEBUG("breakpoint from EICE unit 1");
301                         target->debug_reason = DBG_REASON_BREAKPOINT;
302                         break;
303                 case 3:
304                         DEBUG("soft breakpoint (BKPT instruction)");
305                         target->debug_reason = DBG_REASON_BREAKPOINT;
306                         break;
307                 case 4:
308                         DEBUG("vector catch breakpoint");
309                         target->debug_reason = DBG_REASON_BREAKPOINT;
310                         break;
311                 case 5:
312                         DEBUG("external breakpoint");
313                         target->debug_reason = DBG_REASON_BREAKPOINT;
314                         break;
315                 case 6:
316                         DEBUG("watchpoint from EICE unit 0");
317                         target->debug_reason = DBG_REASON_WATCHPOINT;
318                         break;
319                 case 7:
320                         DEBUG("watchpoint from EICE unit 1");
321                         target->debug_reason = DBG_REASON_WATCHPOINT;
322                         break;
323                 case 8:
324                         DEBUG("external watchpoint");
325                         target->debug_reason = DBG_REASON_WATCHPOINT;
326                         break;
327                 case 9:
328                         DEBUG("internal debug request");
329                         target->debug_reason = DBG_REASON_DBGRQ;
330                         break;
331                 case 10:
332                         DEBUG("external debug request");
333                         target->debug_reason = DBG_REASON_DBGRQ;
334                         break;
335                 case 11:
336                         ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
337                         break;
338                 default:
339                         ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
340                         target->debug_reason = DBG_REASON_DBGRQ;
341                         retval = ERROR_TARGET_FAILURE;
342                         break;
343         }
344         
345         return retval;
346 }
347
348 u32 arm926ejs_get_ttb(target_t *target)
349 {
350         armv4_5_common_t *armv4_5 = target->arch_info;
351         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
352         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
353         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
354         int retval;
355         u32 ttb = 0x0;
356
357         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
358                 return retval;
359
360         return ttb;
361 }
362
363 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
364 {
365         armv4_5_common_t *armv4_5 = target->arch_info;
366         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
367         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
368         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
369         u32 cp15_control;
370
371         /* read cp15 control register */
372         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
373         jtag_execute_queue();
374         
375         if (mmu)
376         {
377                 /* invalidate TLB */
378                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
379                 
380                 cp15_control &= ~0x1U;
381         }
382         
383         if (d_u_cache)
384         {
385                 u32 debug_override;
386                 /* read-modify-write CP15 debug override register 
387                  * to enable "test and clean all" */
388                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
389                 debug_override |= 0x80000;
390                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
391                 
392                 /* clean and invalidate DCache */
393                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
394
395                 /* write CP15 debug override register 
396                  * to disable "test and clean all" */
397                 debug_override &= ~0x80000;
398                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
399                 
400                 cp15_control &= ~0x4U;
401         }
402         
403         if (i_cache)
404         {
405                 /* invalidate ICache */
406                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
407                 
408                 cp15_control &= ~0x1000U;
409         }
410         
411         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
412 }
413
414 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
415 {
416         armv4_5_common_t *armv4_5 = target->arch_info;
417         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
418         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
419         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
420         u32 cp15_control;
421
422         /* read cp15 control register */
423         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
424         jtag_execute_queue();
425                 
426         if (mmu)
427                 cp15_control |= 0x1U;
428         
429         if (d_u_cache)
430                 cp15_control |= 0x4U;
431         
432         if (i_cache)
433                 cp15_control |= 0x1000U;
434         
435         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
436 }
437
438 void arm926ejs_post_debug_entry(target_t *target)
439 {
440         armv4_5_common_t *armv4_5 = target->arch_info;
441         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
442         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
443         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
444
445         /* examine cp15 control reg */
446         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
447         jtag_execute_queue();
448         DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
449
450         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
451         {
452                 u32 cache_type_reg;
453                 /* identify caches */
454                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
455                 jtag_execute_queue();
456                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
457         }
458
459         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
460         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
461         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
462
463         /* save i/d fault status and address register */
464         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
465         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
466         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
467         
468         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
469                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);  
470
471
472         u32 cache_dbg_ctrl;
473         
474         /* read-modify-write CP15 cache debug control register 
475          * to disable I/D-cache linefills and force WT */
476         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
477         cache_dbg_ctrl |= 0x7;
478         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
479 }
480
481 void arm926ejs_pre_restore_context(target_t *target)
482 {
483         armv4_5_common_t *armv4_5 = target->arch_info;
484         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
485         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
486         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
487
488         /* restore i/d fault status and address register */
489         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
490         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
491         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
492         
493         u32 cache_dbg_ctrl;
494         
495         /* read-modify-write CP15 cache debug control register 
496          * to reenable I/D-cache linefills and disable WT */
497         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
498         cache_dbg_ctrl &= ~0x7;
499         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
500 }
501
502 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
503 {
504         armv4_5_common_t *armv4_5 = target->arch_info;
505         arm7_9_common_t *arm7_9;
506         arm9tdmi_common_t *arm9tdmi;
507         arm926ejs_common_t *arm926ejs;
508         
509         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
510         {
511                 return -1;
512         }
513         
514         arm7_9 = armv4_5->arch_info;
515         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
516         {
517                 return -1;
518         }
519         
520         arm9tdmi = arm7_9->arch_info;
521         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
522         {
523                 return -1;
524         }
525         
526         arm926ejs = arm9tdmi->arch_info;
527         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
528         {
529                 return -1;
530         }
531         
532         *armv4_5_p = armv4_5;
533         *arm7_9_p = arm7_9;
534         *arm9tdmi_p = arm9tdmi;
535         *arm926ejs_p = arm926ejs;
536         
537         return ERROR_OK;
538 }
539
540 int arm926ejs_arch_state(struct target_s *target)
541 {
542         armv4_5_common_t *armv4_5 = target->arch_info;
543         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
544         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
545         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
546         
547         char *state[] = 
548         {
549                 "disabled", "enabled"
550         };
551         
552         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
553         {
554                 ERROR("BUG: called for a non-ARMv4/5 target");
555                 exit(-1);
556         }
557         
558         USER(
559                         "target halted in %s state due to %s, current mode: %s\n"
560                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
561                         "MMU: %s, D-Cache: %s, I-Cache: %s",
562                          armv4_5_state_strings[armv4_5->core_state],
563                          target_debug_reason_strings[target->debug_reason],
564                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
565                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
566                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
567                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
568                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], 
569                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
570         
571         return ERROR_OK;
572 }
573
574 int arm926ejs_soft_reset_halt(struct target_s *target)
575 {
576         armv4_5_common_t *armv4_5 = target->arch_info;
577         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
578         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
579         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
580         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
581         
582         target->type->halt(target);
583         
584         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
585         {
586                 embeddedice_read_reg(dbg_stat);
587                 jtag_execute_queue();
588         }
589         
590         target->state = TARGET_HALTED;
591         
592         /* SVC, ARM state, IRQ and FIQ disabled */
593         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
594         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
595         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
596         
597         /* start fetching from 0x0 */
598         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
599         armv4_5->core_cache->reg_list[15].dirty = 1;
600         armv4_5->core_cache->reg_list[15].valid = 1;
601         
602         armv4_5->core_mode = ARMV4_5_MODE_SVC;
603         armv4_5->core_state = ARMV4_5_STATE_ARM;
604         
605         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
606         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
607         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
608         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
609
610         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
611         
612         return ERROR_OK;
613 }
614
615 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
616 {
617         int retval;
618         armv4_5_common_t *armv4_5 = target->arch_info;
619         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
620         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
621         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
622         
623         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
624                 return retval;
625
626         /* If ICache is enabled, we have to invalidate affected ICache lines
627          * the DCache is forced to write-through, so we don't have to clean it here
628          */
629         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
630         {
631                 if (count <= 1)
632                 {
633                         /* invalidate ICache single entry with MVA */
634                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
635                 }
636                 else
637                 {
638                         /* invalidate ICache */
639                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
640                 }
641         }
642
643         return retval;
644 }
645
646 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
647 {
648         arm9tdmi_init_target(cmd_ctx, target);
649                 
650         return ERROR_OK;
651         
652 }
653
654 int arm926ejs_quit()
655 {
656         
657         return ERROR_OK;
658 }
659
660 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
661 {
662         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
663         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
664         
665         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
666          */
667         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
668
669         arm9tdmi->arch_info = arm926ejs;
670         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
671         
672         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
673         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
674         
675         arm926ejs->read_cp15 = arm926ejs_cp15_read;
676         arm926ejs->write_cp15 = arm926ejs_cp15_write;
677         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
678         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
679         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
680         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
681         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
682         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
683         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
684         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
685         
686         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
687         
688         /* The ARM926EJ-S implements the ARMv5TE architecture which
689          * has the BKPT instruction, so we don't have to use a watchpoint comparator
690          */
691         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
692         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
693         
694         arm7_9->sw_bkpts_use_wp = 0;
695         arm7_9->sw_bkpts_enabled = 1;
696         
697         return ERROR_OK;
698 }
699
700 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
701 {
702         int chain_pos;
703         char *variant = NULL;
704         arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
705         memset(arm926ejs, 0, sizeof(*arm926ejs));
706         
707         if (argc < 4)
708         {
709                 ERROR("'target arm926ejs' requires at least one additional argument");
710                 exit(-1);
711         }
712         
713         chain_pos = strtoul(args[3], NULL, 0);
714         
715         if (argc >= 5)
716                 variant = args[4];
717         
718         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
719         
720         arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
721
722         return ERROR_OK;
723 }
724
725 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
726 {
727         int retval;
728         command_t *arm926ejs_cmd;
729         
730                 
731         retval = arm9tdmi_register_commands(cmd_ctx);
732         
733         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
734
735         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
736         
737         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
738         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
739
740         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
741         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
742         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
743
744         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
745         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
746         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
747
748         return ERROR_OK;
749 }
750
751 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
752 {
753         int retval;
754         target_t *target = get_current_target(cmd_ctx);
755         armv4_5_common_t *armv4_5;
756         arm7_9_common_t *arm7_9;
757         arm9tdmi_common_t *arm9tdmi;
758         arm926ejs_common_t *arm926ejs;
759         int opcode_1;
760         int opcode_2;
761         int CRn;
762         int CRm;
763
764         if ((argc < 4) || (argc > 5))
765         {
766                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
767                 return ERROR_OK;
768         }
769         
770         opcode_1 = strtoul(args[0], NULL, 0);
771         opcode_2 = strtoul(args[1], NULL, 0);
772         CRn = strtoul(args[2], NULL, 0);
773         CRm = strtoul(args[3], NULL, 0);
774
775         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
776         {
777                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
778                 return ERROR_OK;
779         }
780         
781         if (target->state != TARGET_HALTED)
782         {
783                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
784                 return ERROR_OK;
785         }
786         
787         if (argc == 4)
788         {
789                 u32 value;
790                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
791                 {
792                         command_print(cmd_ctx, "couldn't access register");
793                         return ERROR_OK;
794                 }
795                 jtag_execute_queue();
796                 
797                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
798         }
799         else
800         {
801                 u32 value = strtoul(args[4], NULL, 0);
802                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
803                 {
804                         command_print(cmd_ctx, "couldn't access register");
805                         return ERROR_OK;
806                 }
807                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
808         }
809
810         return ERROR_OK;
811 }
812
813 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
814 {
815         target_t *target = get_current_target(cmd_ctx);
816         armv4_5_common_t *armv4_5;
817         arm7_9_common_t *arm7_9;
818         arm9tdmi_common_t *arm9tdmi;
819         arm926ejs_common_t *arm926ejs;
820         
821         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
822         {
823                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
824                 return ERROR_OK;
825         }
826         
827         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
828 }
829
830 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
831 {       
832         target_t *target = get_current_target(cmd_ctx);
833         armv4_5_common_t *armv4_5;
834         arm7_9_common_t *arm7_9;
835         arm9tdmi_common_t *arm9tdmi;
836         arm926ejs_common_t *arm926ejs;
837         arm_jtag_t *jtag_info;
838
839         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
840         {
841                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
842                 return ERROR_OK;
843         }
844         
845         jtag_info = &arm7_9->jtag_info;
846         
847         if (target->state != TARGET_HALTED)
848         {
849                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
850                 return ERROR_OK;
851         }
852                 
853         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
854 }
855
856 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
857 {       
858         target_t *target = get_current_target(cmd_ctx);
859         armv4_5_common_t *armv4_5;
860         arm7_9_common_t *arm7_9;
861         arm9tdmi_common_t *arm9tdmi;
862         arm926ejs_common_t *arm926ejs;
863         arm_jtag_t *jtag_info;
864
865         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
866         {
867                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
868                 return ERROR_OK;
869         }
870         
871         jtag_info = &arm7_9->jtag_info;
872         
873         if (target->state != TARGET_HALTED)
874         {
875                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
876                 return ERROR_OK;
877         }
878         
879         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
880 }
881
882 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
883 {       
884         target_t *target = get_current_target(cmd_ctx);
885         armv4_5_common_t *armv4_5;
886         arm7_9_common_t *arm7_9;
887         arm9tdmi_common_t *arm9tdmi;
888         arm926ejs_common_t *arm926ejs;
889         arm_jtag_t *jtag_info;
890
891         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
892         {
893                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
894                 return ERROR_OK;
895         }
896         
897         jtag_info = &arm7_9->jtag_info;
898         
899         if (target->state != TARGET_HALTED)
900         {
901                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
902                 return ERROR_OK;
903         }
904         
905         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
906 }
907 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
908 {
909         int retval;
910         int type;
911         u32 cb;
912         int domain;
913         u32 ap;
914         
915         armv4_5_common_t *armv4_5;
916         arm7_9_common_t *arm7_9;
917         arm9tdmi_common_t *arm9tdmi;
918         arm926ejs_common_t *arm926ejs;
919         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
920         if (retval != ERROR_OK)
921         {
922                 return retval;
923         }
924         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
925         if (type == -1)
926         {
927                 return ret;
928         }
929         *physical = ret;
930         return ERROR_OK;
931 }
932
933 static int arm926ejs_mmu(struct target_s *target, int *enabled)
934 {
935         armv4_5_common_t *armv4_5 = target->arch_info;
936         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
937         
938         if (target->state != TARGET_HALTED)
939         {
940                 ERROR("Target not halted");
941                 return ERROR_TARGET_INVALID;
942         }
943         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
944         return ERROR_OK;
945 }