arm: add error propagation for enable/disable mmu caches
[fw/openocd] / src / target / arm926ejs.c
1 /***************************************************************************
2  *   Copyright (C) 2007 by Dominic Rath                                    *
3  *   Dominic.Rath@gmx.de                                                   *
4  *                                                                         *
5  *   Copyright (C) 2007,2008,2009 by Ã˜yvind Harboe                         *
6  *   oyvind.harboe@zylin.com                                               *
7  *                                                                         *
8  *   This program is free software; you can redistribute it and/or modify  *
9  *   it under the terms of the GNU General Public License as published by  *
10  *   the Free Software Foundation; either version 2 of the License, or     *
11  *   (at your option) any later version.                                   *
12  *                                                                         *
13  *   This program is distributed in the hope that it will be useful,       *
14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
16  *   GNU General Public License for more details.                          *
17  *                                                                         *
18  *   You should have received a copy of the GNU General Public License     *
19  *   along with this program; if not, write to the                         *
20  *   Free Software Foundation, Inc.,                                       *
21  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
22  ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "arm926ejs.h"
28 #include <helper/time_support.h>
29 #include "target_type.h"
30 #include "register.h"
31 #include "arm_opcodes.h"
32
33
34 /*
35  * The ARM926 is built around the ARM9EJ-S core, and most JTAG docs
36  * are in the ARM9EJ-S Technical Reference Manual (ARM DDI 0222B) not
37  * the ARM926 manual (ARM DDI 0198E).  The scan chains are:
38  *
39  *   1 ... core debugging
40  *   2 ... EmbeddedICE
41  *   3 ... external boundary scan (SoC-specific, unused here)
42  *   6 ... ETM
43  *   15 ... coprocessor 15
44  */
45
46 #if 0
47 #define _DEBUG_INSTRUCTION_EXECUTION_
48 #endif
49
50 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
51
52 static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2,
53                 uint32_t CRn, uint32_t CRm, uint32_t *value)
54 {
55         int retval = ERROR_OK;
56         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
57         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
58         uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
59         struct scan_field fields[4];
60         uint8_t address_buf[2] = {0, 0};
61         uint8_t nr_w_buf = 0;
62         uint8_t access_t = 1;
63
64         buf_set_u32(address_buf, 0, 14, address);
65
66         if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
67         {
68                 return retval;
69         }
70         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
71
72         fields[0].num_bits = 32;
73         fields[0].out_value = NULL;
74         fields[0].in_value = (uint8_t *)value;
75
76         fields[1].num_bits = 1;
77         fields[1].out_value = &access_t;
78         fields[1].in_value = &access_t;
79
80         fields[2].num_bits = 14;
81         fields[2].out_value = address_buf;
82         fields[2].in_value = NULL;
83
84         fields[3].num_bits = 1;
85         fields[3].out_value = &nr_w_buf;
86         fields[3].in_value = NULL;
87
88         jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
89
90         long long then = timeval_ms();
91
92         for (;;)
93         {
94                 /* rescan with NOP, to wait for the access to complete */
95                 access_t = 0;
96                 nr_w_buf = 0;
97                 jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
98
99                 jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
100
101                 if ((retval = jtag_execute_queue()) != ERROR_OK)
102                 {
103                         return retval;
104                 }
105
106                 if (buf_get_u32(&access_t, 0, 1) == 1)
107                 {
108                         break;
109                 }
110
111                 /* 10ms timeout */
112                 if ((timeval_ms()-then)>10)
113                 {
114                         LOG_ERROR("cp15 read operation timed out");
115                         return ERROR_FAIL;
116                 }
117         }
118
119 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
120         LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
121 #endif
122
123         arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
124
125         return ERROR_OK;
126 }
127
128 static int arm926ejs_mrc(struct target *target, int cpnum, uint32_t op1,
129                 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
130 {
131         if (cpnum != 15) {
132                 LOG_ERROR("Only cp15 is supported");
133                 return ERROR_FAIL;
134         }
135         return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
136 }
137
138 static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op2,
139                 uint32_t CRn, uint32_t CRm, uint32_t value)
140 {
141         int retval = ERROR_OK;
142         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
143         struct arm_jtag *jtag_info = &arm7_9->jtag_info;
144         uint32_t address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
145         struct scan_field fields[4];
146         uint8_t value_buf[4];
147         uint8_t address_buf[2] = {0, 0};
148         uint8_t nr_w_buf = 1;
149         uint8_t access_t = 1;
150
151         buf_set_u32(address_buf, 0, 14, address);
152         buf_set_u32(value_buf, 0, 32, value);
153
154         if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
155         {
156                 return retval;
157         }
158         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
159
160         fields[0].num_bits = 32;
161         fields[0].out_value = value_buf;
162         fields[0].in_value = NULL;
163
164         fields[1].num_bits = 1;
165         fields[1].out_value = &access_t;
166         fields[1].in_value = &access_t;
167
168         fields[2].num_bits = 14;
169         fields[2].out_value = address_buf;
170         fields[2].in_value = NULL;
171
172         fields[3].num_bits = 1;
173         fields[3].out_value = &nr_w_buf;
174         fields[3].in_value = NULL;
175
176         jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
177
178         long long then = timeval_ms();
179
180         for (;;)
181         {
182                 /* rescan with NOP, to wait for the access to complete */
183                 access_t = 0;
184                 nr_w_buf = 0;
185                 jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
186                 if ((retval = jtag_execute_queue()) != ERROR_OK)
187                 {
188                         return retval;
189                 }
190
191                 if (buf_get_u32(&access_t, 0, 1) == 1)
192                 {
193                         break;
194                 }
195
196                 /* 10ms timeout */
197                 if ((timeval_ms()-then)>10)
198                 {
199                         LOG_ERROR("cp15 write operation timed out");
200                         return ERROR_FAIL;
201                 }
202         }
203
204 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
205         LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
206 #endif
207
208         arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
209
210         return ERROR_OK;
211 }
212
213 static int arm926ejs_mcr(struct target *target, int cpnum, uint32_t op1,
214                 uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
215 {
216         if (cpnum != 15) {
217                 LOG_ERROR("Only cp15 is supported");
218                 return ERROR_FAIL;
219         }
220         return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
221 }
222
223 static int arm926ejs_examine_debug_reason(struct target *target)
224 {
225         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
226         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
227         int debug_reason;
228         int retval;
229
230         embeddedice_read_reg(dbg_stat);
231         if ((retval = jtag_execute_queue()) != ERROR_OK)
232                 return retval;
233
234         /* Method-Of-Entry (MOE) field */
235         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
236
237         switch (debug_reason)
238         {
239                 case 0:
240                         LOG_DEBUG("no *NEW* debug entry (?missed one?)");
241                         /* ... since last restart or debug reset ... */
242                         target->debug_reason = DBG_REASON_DBGRQ;
243                         break;
244                 case 1:
245                         LOG_DEBUG("breakpoint from EICE unit 0");
246                         target->debug_reason = DBG_REASON_BREAKPOINT;
247                         break;
248                 case 2:
249                         LOG_DEBUG("breakpoint from EICE unit 1");
250                         target->debug_reason = DBG_REASON_BREAKPOINT;
251                         break;
252                 case 3:
253                         LOG_DEBUG("soft breakpoint (BKPT instruction)");
254                         target->debug_reason = DBG_REASON_BREAKPOINT;
255                         break;
256                 case 4:
257                         LOG_DEBUG("vector catch breakpoint");
258                         target->debug_reason = DBG_REASON_BREAKPOINT;
259                         break;
260                 case 5:
261                         LOG_DEBUG("external breakpoint");
262                         target->debug_reason = DBG_REASON_BREAKPOINT;
263                         break;
264                 case 6:
265                         LOG_DEBUG("watchpoint from EICE unit 0");
266                         target->debug_reason = DBG_REASON_WATCHPOINT;
267                         break;
268                 case 7:
269                         LOG_DEBUG("watchpoint from EICE unit 1");
270                         target->debug_reason = DBG_REASON_WATCHPOINT;
271                         break;
272                 case 8:
273                         LOG_DEBUG("external watchpoint");
274                         target->debug_reason = DBG_REASON_WATCHPOINT;
275                         break;
276                 case 9:
277                         LOG_DEBUG("internal debug request");
278                         target->debug_reason = DBG_REASON_DBGRQ;
279                         break;
280                 case 10:
281                         LOG_DEBUG("external debug request");
282                         target->debug_reason = DBG_REASON_DBGRQ;
283                         break;
284                 case 11:
285                         LOG_DEBUG("debug re-entry from system speed access");
286                         /* This is normal when connecting to something that's
287                          * already halted, or in some related code paths, but
288                          * otherwise is surprising (and presumably wrong).
289                          */
290                         switch (target->debug_reason) {
291                         case DBG_REASON_DBGRQ:
292                                 break;
293                         default:
294                                 LOG_ERROR("unexpected -- debug re-entry");
295                                 /* FALLTHROUGH */
296                         case DBG_REASON_UNDEFINED:
297                                 target->debug_reason = DBG_REASON_DBGRQ;
298                                 break;
299                         }
300                         break;
301                 case 12:
302                         /* FIX!!!! here be dragons!!! We need to fail here so
303                          * the target will interpreted as halted but we won't
304                          * try to talk to it right now... a resume + halt seems
305                          * to sync things up again. Please send an email to
306                          * openocd development mailing list if you have hardware
307                          * to donate to look into this problem....
308                          */
309                         LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt.");
310                         target->debug_reason = DBG_REASON_DBGRQ;
311                         break;
312                 default:
313                         LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason);
314                         /* Oh agony! should we interpret this as a halt request or
315                          * that the target stopped on it's own accord?
316                          */
317                         target->debug_reason = DBG_REASON_DBGRQ;
318                         /* if we fail here, we won't talk to the target and it will
319                          * be reported to be in the halted state */
320                         break;
321         }
322
323         return ERROR_OK;
324 }
325
326 static int arm926ejs_get_ttb(struct target *target, uint32_t *result)
327 {
328         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
329         int retval;
330         uint32_t ttb = 0x0;
331
332         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
333                 return retval;
334
335         *result = ttb;
336
337         return ERROR_OK;
338 }
339
340 static int arm926ejs_disable_mmu_caches(struct target *target, int mmu,
341                 int d_u_cache, int i_cache)
342 {
343         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
344         uint32_t cp15_control;
345         int retval;
346
347         /* read cp15 control register */
348         retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
349         if (retval != ERROR_OK)
350                 return retval;
351         retval = jtag_execute_queue();
352         if (retval != ERROR_OK)
353                 return retval;
354
355         if (mmu)
356         {
357                 /* invalidate TLB */
358                 retval = arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
359                 if (retval != ERROR_OK)
360                         return retval;
361
362                 cp15_control &= ~0x1U;
363         }
364
365         if (d_u_cache)
366         {
367                 uint32_t debug_override;
368                 /* read-modify-write CP15 debug override register
369                  * to enable "test and clean all" */
370                 retval = arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
371                 if (retval != ERROR_OK)
372                         return retval;
373                 debug_override |= 0x80000;
374                 retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
375                 if (retval != ERROR_OK)
376                         return retval;
377
378                 /* clean and invalidate DCache */
379                 retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
380                 if (retval != ERROR_OK)
381                         return retval;
382
383                 /* write CP15 debug override register
384                  * to disable "test and clean all" */
385                 debug_override &= ~0x80000;
386                 retval = arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
387                 if (retval != ERROR_OK)
388                         return retval;
389
390                 cp15_control &= ~0x4U;
391         }
392
393         if (i_cache)
394         {
395                 /* invalidate ICache */
396                 retval = arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
397                 if (retval != ERROR_OK)
398                         return retval;
399
400                 cp15_control &= ~0x1000U;
401         }
402
403         retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
404         return retval;
405 }
406
407 static int arm926ejs_enable_mmu_caches(struct target *target, int mmu,
408                 int d_u_cache, int i_cache)
409 {
410         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
411         uint32_t cp15_control;
412         int retval;
413
414         /* read cp15 control register */
415         retval = arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
416         if (retval != ERROR_OK)
417                 return retval;
418         retval = jtag_execute_queue();
419         if (retval != ERROR_OK)
420                 return retval;
421
422         if (mmu)
423                 cp15_control |= 0x1U;
424
425         if (d_u_cache)
426                 cp15_control |= 0x4U;
427
428         if (i_cache)
429                 cp15_control |= 0x1000U;
430
431         retval = arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
432         return retval;
433 }
434
435 static void arm926ejs_post_debug_entry(struct target *target)
436 {
437         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
438
439         /* examine cp15 control reg */
440         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
441         jtag_execute_queue();
442         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
443
444         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
445         {
446                 uint32_t cache_type_reg;
447                 /* identify caches */
448                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
449                 jtag_execute_queue();
450                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
451         }
452
453         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
454         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
455         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
456
457         /* save i/d fault status and address register */
458         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
459         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
460         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
461
462         LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
463                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
464
465         uint32_t cache_dbg_ctrl;
466
467         /* read-modify-write CP15 cache debug control register
468          * to disable I/D-cache linefills and force WT */
469         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
470         cache_dbg_ctrl |= 0x7;
471         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
472 }
473
474 static void arm926ejs_pre_restore_context(struct target *target)
475 {
476         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
477
478         /* restore i/d fault status and address register */
479         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
480         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
481         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
482
483         uint32_t cache_dbg_ctrl;
484
485         /* read-modify-write CP15 cache debug control register
486          * to reenable I/D-cache linefills and disable WT */
487         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
488         cache_dbg_ctrl &= ~0x7;
489         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
490 }
491
492 static const char arm926_not[] = "target is not an ARM926";
493
494 static int arm926ejs_verify_pointer(struct command_context *cmd_ctx,
495                 struct arm926ejs_common *arm926)
496 {
497         if (arm926->common_magic != ARM926EJS_COMMON_MAGIC) {
498                 command_print(cmd_ctx, arm926_not);
499                 return ERROR_TARGET_INVALID;
500         }
501         return ERROR_OK;
502 }
503
504 /** Logs summary of ARM926 state for a halted target. */
505 int arm926ejs_arch_state(struct target *target)
506 {
507         static const char *state[] =
508         {
509                 "disabled", "enabled"
510         };
511
512         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
513         struct arm *armv4_5;
514
515         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
516         {
517                 LOG_ERROR("BUG: %s", arm926_not);
518                 return ERROR_TARGET_INVALID;
519         }
520
521         armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
522
523         arm_arch_state(target);
524         LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
525                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
526                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
527                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
528
529         return ERROR_OK;
530 }
531
532 int arm926ejs_soft_reset_halt(struct target *target)
533 {
534         int retval = ERROR_OK;
535         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
536         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
537         struct arm *armv4_5 = &arm7_9->armv4_5_common;
538         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
539
540         if ((retval = target_halt(target)) != ERROR_OK)
541         {
542                 return retval;
543         }
544
545         long long then = timeval_ms();
546         int timeout;
547         while (!(timeout = ((timeval_ms()-then) > 1000)))
548         {
549                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
550                 {
551                         embeddedice_read_reg(dbg_stat);
552                         if ((retval = jtag_execute_queue()) != ERROR_OK)
553                         {
554                                 return retval;
555                         }
556                 }  else
557                 {
558                         break;
559                 }
560                 if (debug_level >= 1)
561                 {
562                         /* do not eat all CPU, time out after 1 se*/
563                         alive_sleep(100);
564                 } else
565                 {
566                         keep_alive();
567                 }
568         }
569         if (timeout)
570         {
571                 LOG_ERROR("Failed to halt CPU after 1 sec");
572                 return ERROR_TARGET_TIMEOUT;
573         }
574
575         target->state = TARGET_HALTED;
576
577         /* SVC, ARM state, IRQ and FIQ disabled */
578         uint32_t cpsr;
579
580         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
581         cpsr &= ~0xff;
582         cpsr |= 0xd3;
583         arm_set_cpsr(armv4_5, cpsr);
584         armv4_5->cpsr->dirty = 1;
585
586         /* start fetching from 0x0 */
587         buf_set_u32(armv4_5->pc->value, 0, 32, 0x0);
588         armv4_5->pc->dirty = 1;
589         armv4_5->pc->valid = 1;
590
591         retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
592         if (retval != ERROR_OK)
593                 return retval;
594         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
595         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
596         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
597
598         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
599 }
600
601 /** Writes a buffer, in the specified word size, with current MMU settings. */
602 int arm926ejs_write_memory(struct target *target, uint32_t address,
603                 uint32_t size, uint32_t count, uint8_t *buffer)
604 {
605         int retval;
606         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
607
608         /* FIX!!!! this should be cleaned up and made much more general. The
609          * plan is to write up and test on arm926ejs specifically and
610          * then generalize and clean up afterwards.
611          *
612          *
613          * Also it should be moved to the callbacks that handle breakpoints
614          * specifically and not the generic memory write fn's. See XScale code.
615          **/
616         if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
617         {
618                 /* special case the handling of single word writes to bypass MMU
619                  * to allow implementation of breakpoints in memory marked read only
620                  * by MMU */
621                 if (arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
622                 {
623                         /* flush and invalidate data cache
624                          *
625                          * MCR p15,0,p,c7,c10,1 - clean cache line using virtual address
626                          *
627                          */
628                         retval = arm926ejs->write_cp15(target, 0, 1, 7, 10, address&~0x3);
629                         if (retval != ERROR_OK)
630                                 return retval;
631                 }
632
633                 uint32_t pa;
634                 retval = target->type->virt2phys(target, address, &pa);
635                 if (retval != ERROR_OK)
636                         return retval;
637
638                 /* write directly to physical memory bypassing any read only MMU bits, etc. */
639                 retval = armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, pa, size, count, buffer);
640                 if (retval != ERROR_OK)
641                         return retval;
642         } else
643         {
644                 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
645                         return retval;
646         }
647
648         /* If ICache is enabled, we have to invalidate affected ICache lines
649          * the DCache is forced to write-through, so we don't have to clean it here
650          */
651         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
652         {
653                 if (count <= 1)
654                 {
655                         /* invalidate ICache single entry with MVA */
656                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
657                 }
658                 else
659                 {
660                         /* invalidate ICache */
661                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
662                 }
663         }
664
665         return retval;
666 }
667
668 static int arm926ejs_write_phys_memory(struct target *target,
669                 uint32_t address, uint32_t size,
670                 uint32_t count, uint8_t *buffer)
671 {
672         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
673
674         return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu,
675                         address, size, count, buffer);
676 }
677
678 static int arm926ejs_read_phys_memory(struct target *target,
679                 uint32_t address, uint32_t size,
680                 uint32_t count, uint8_t *buffer)
681 {
682         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
683
684         return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu,
685                         address, size, count, buffer);
686 }
687
688 int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs,
689                 struct jtag_tap *tap)
690 {
691         struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common;
692
693         arm7_9->armv4_5_common.mrc = arm926ejs_mrc;
694         arm7_9->armv4_5_common.mcr = arm926ejs_mcr;
695
696         /* initialize arm7/arm9 specific info (including armv4_5) */
697         arm9tdmi_init_arch_info(target, arm7_9, tap);
698
699         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
700
701         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
702         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
703
704         arm926ejs->read_cp15 = arm926ejs_cp15_read;
705         arm926ejs->write_cp15 = arm926ejs_cp15_write;
706         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
707         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
708         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
709         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
710         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
711         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
712         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
713         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
714
715         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
716
717         /* The ARM926EJ-S implements the ARMv5TE architecture which
718          * has the BKPT instruction, so we don't have to use a watchpoint comparator
719          */
720         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
721         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
722
723         return ERROR_OK;
724 }
725
726 static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
727 {
728         struct arm926ejs_common *arm926ejs = calloc(1,sizeof(struct arm926ejs_common));
729
730         /* ARM9EJ-S core always reports 0x1 in Capture-IR */
731         target->tap->ir_capture_mask = 0x0f;
732
733         return arm926ejs_init_arch_info(target, arm926ejs, target->tap);
734 }
735
736 COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
737 {
738         int retval;
739         struct target *target = get_current_target(CMD_CTX);
740         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
741
742         retval = arm926ejs_verify_pointer(CMD_CTX, arm926ejs);
743         if (retval != ERROR_OK)
744                 return retval;
745
746         return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache);
747 }
748
749 static int arm926ejs_virt2phys(struct target *target, uint32_t virtual, uint32_t *physical)
750 {
751         uint32_t cb;
752         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
753
754         uint32_t ret;
755         int retval = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu,
756                         virtual, &cb, &ret);
757         if (retval != ERROR_OK)
758                 return retval;
759         *physical = ret;
760         return ERROR_OK;
761 }
762
763 static int arm926ejs_mmu(struct target *target, int *enabled)
764 {
765         struct arm926ejs_common *arm926ejs = target_to_arm926(target);
766
767         if (target->state != TARGET_HALTED)
768         {
769                 LOG_ERROR("Target not halted");
770                 return ERROR_TARGET_INVALID;
771         }
772         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
773         return ERROR_OK;
774 }
775
776 static const struct command_registration arm926ejs_exec_command_handlers[] = {
777         {
778                 .name = "cache_info",
779                 .handler = arm926ejs_handle_cache_info_command,
780                 .mode = COMMAND_EXEC,
781                 .help = "display information about target caches",
782
783         },
784         COMMAND_REGISTRATION_DONE
785 };
786 const struct command_registration arm926ejs_command_handlers[] = {
787         {
788                 .chain = arm9tdmi_command_handlers,
789         },
790         {
791                 .name = "arm926ejs",
792                 .mode = COMMAND_ANY,
793                 .help = "arm926ejs command group",
794                 .chain = arm926ejs_exec_command_handlers,
795         },
796         COMMAND_REGISTRATION_DONE
797 };
798
799 /** Holds methods for ARM926 targets. */
800 struct target_type arm926ejs_target =
801 {
802         .name = "arm926ejs",
803
804         .poll = arm7_9_poll,
805         .arch_state = arm926ejs_arch_state,
806
807         .target_request_data = arm7_9_target_request_data,
808
809         .halt = arm7_9_halt,
810         .resume = arm7_9_resume,
811         .step = arm7_9_step,
812
813         .assert_reset = arm7_9_assert_reset,
814         .deassert_reset = arm7_9_deassert_reset,
815         .soft_reset_halt = arm926ejs_soft_reset_halt,
816
817         .get_gdb_reg_list = arm_get_gdb_reg_list,
818
819         .read_memory = arm7_9_read_memory,
820         .write_memory = arm926ejs_write_memory,
821         .bulk_write_memory = arm7_9_bulk_write_memory,
822
823         .checksum_memory = arm_checksum_memory,
824         .blank_check_memory = arm_blank_check_memory,
825
826         .run_algorithm = armv4_5_run_algorithm,
827
828         .add_breakpoint = arm7_9_add_breakpoint,
829         .remove_breakpoint = arm7_9_remove_breakpoint,
830         .add_watchpoint = arm7_9_add_watchpoint,
831         .remove_watchpoint = arm7_9_remove_watchpoint,
832
833         .commands = arm926ejs_command_handlers,
834         .target_create = arm926ejs_target_create,
835         .init_target = arm9tdmi_init_target,
836         .examine = arm7_9_examine,
837         .check_reset = arm7_9_check_reset,
838         .virt2phys = arm926ejs_virt2phys,
839         .mmu = arm926ejs_mmu,
840
841         .read_phys_memory = arm926ejs_read_phys_memory,
842         .write_phys_memory = arm926ejs_write_phys_memory,
843 };