1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 /* forward declarations */
49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
52 int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size);
53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm926ejs_soft_reset_halt(struct target_s *target);
57 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
59 target_type_t arm926ejs_target =
64 .arch_state = arm926ejs_arch_state,
67 .resume = arm7_9_resume,
70 .assert_reset = arm7_9_assert_reset,
71 .deassert_reset = arm7_9_deassert_reset,
72 .soft_reset_halt = arm926ejs_soft_reset_halt,
73 .prepare_reset_halt = arm7_9_prepare_reset_halt,
75 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
77 .read_memory = arm7_9_read_memory,
78 .write_memory = arm926ejs_write_memory,
79 .bulk_write_memory = arm7_9_bulk_write_memory,
81 .run_algorithm = armv4_5_run_algorithm,
83 .add_breakpoint = arm7_9_add_breakpoint,
84 .remove_breakpoint = arm7_9_remove_breakpoint,
85 .add_watchpoint = arm7_9_add_watchpoint,
86 .remove_watchpoint = arm7_9_remove_watchpoint,
88 .register_commands = arm926ejs_register_commands,
89 .target_command = arm926ejs_target_command,
90 .init_target = arm926ejs_init_target,
91 .quit = arm926ejs_quit
94 int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
96 armv4_5_common_t *armv4_5 = target->arch_info;
97 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
98 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
99 scan_field_t fields[4];
104 buf_set_u32(address_buf, 0, 14, address);
106 jtag_add_end_state(TAP_RTI);
107 arm_jtag_scann(jtag_info, 0xf);
108 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
110 fields[0].device = jtag_info->chain_pos;
111 fields[0].num_bits = 32;
112 fields[0].out_value = NULL;
113 fields[0].out_mask = NULL;
114 fields[0].in_value = NULL;
115 fields[0].in_check_value = NULL;
116 fields[0].in_check_mask = NULL;
117 fields[0].in_handler = NULL;
118 fields[0].in_handler_priv = NULL;
120 fields[1].device = jtag_info->chain_pos;
121 fields[1].num_bits = 1;
122 fields[1].out_value = &access;
123 fields[1].out_mask = NULL;
124 fields[1].in_value = &access;
125 fields[1].in_check_value = NULL;
126 fields[1].in_check_mask = NULL;
127 fields[1].in_handler = NULL;
128 fields[1].in_handler_priv = NULL;
130 fields[2].device = jtag_info->chain_pos;
131 fields[2].num_bits = 14;
132 fields[2].out_value = address_buf;
133 fields[2].out_mask = NULL;
134 fields[2].in_value = NULL;
135 fields[2].in_check_value = NULL;
136 fields[2].in_check_mask = NULL;
137 fields[2].in_handler = NULL;
138 fields[2].in_handler_priv = NULL;
140 fields[3].device = jtag_info->chain_pos;
141 fields[3].num_bits = 1;
142 fields[3].out_value = &nr_w_buf;
143 fields[3].out_mask = NULL;
144 fields[3].in_value = NULL;
145 fields[3].in_check_value = NULL;
146 fields[3].in_check_mask = NULL;
147 fields[3].in_handler = NULL;
148 fields[3].in_handler_priv = NULL;
150 jtag_add_dr_scan(4, fields, -1);
152 /* rescan with NOP, to wait for the access to complete */
155 fields[0].in_handler_priv = value;
156 fields[0].in_handler = arm_jtag_buf_to_u32;
160 jtag_add_dr_scan(4, fields, -1);
161 jtag_execute_queue();
162 } while (buf_get_u32(&access, 0, 1) != 1);
164 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
165 DEBUG("addr: 0x%x value: %8.8x", address, *value);
171 int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
173 armv4_5_common_t *armv4_5 = target->arch_info;
174 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
175 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
176 scan_field_t fields[4];
182 buf_set_u32(address_buf, 0, 14, address);
183 buf_set_u32(value_buf, 0, 32, value);
185 jtag_add_end_state(TAP_RTI);
186 arm_jtag_scann(jtag_info, 0xf);
187 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
189 fields[0].device = jtag_info->chain_pos;
190 fields[0].num_bits = 32;
191 fields[0].out_value = value_buf;
192 fields[0].out_mask = NULL;
193 fields[0].in_value = NULL;
194 fields[0].in_check_value = NULL;
195 fields[0].in_check_mask = NULL;
196 fields[0].in_handler = NULL;
197 fields[0].in_handler_priv = NULL;
199 fields[1].device = jtag_info->chain_pos;
200 fields[1].num_bits = 1;
201 fields[1].out_value = &access;
202 fields[1].out_mask = NULL;
203 fields[1].in_value = &access;
204 fields[1].in_check_value = NULL;
205 fields[1].in_check_mask = NULL;
206 fields[1].in_handler = NULL;
207 fields[1].in_handler_priv = NULL;
209 fields[2].device = jtag_info->chain_pos;
210 fields[2].num_bits = 14;
211 fields[2].out_value = address_buf;
212 fields[2].out_mask = NULL;
213 fields[2].in_value = NULL;
214 fields[2].in_check_value = NULL;
215 fields[2].in_check_mask = NULL;
216 fields[2].in_handler = NULL;
217 fields[2].in_handler_priv = NULL;
219 fields[3].device = jtag_info->chain_pos;
220 fields[3].num_bits = 1;
221 fields[3].out_value = &nr_w_buf;
222 fields[3].out_mask = NULL;
223 fields[3].in_value = NULL;
224 fields[3].in_check_value = NULL;
225 fields[3].in_check_mask = NULL;
226 fields[3].in_handler = NULL;
227 fields[3].in_handler_priv = NULL;
229 jtag_add_dr_scan(4, fields, -1);
231 /* rescan with NOP, to wait for the access to complete */
236 jtag_add_dr_scan(4, fields, -1);
237 jtag_execute_queue();
238 } while (buf_get_u32(&access, 0, 1) != 1);
240 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
241 DEBUG("addr: 0x%x value: %8.8x", address, value);
247 int arm926ejs_examine_debug_reason(target_t *target)
249 armv4_5_common_t *armv4_5 = target->arch_info;
250 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
251 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
255 embeddedice_read_reg(dbg_stat);
256 if ((retval = jtag_execute_queue()) != ERROR_OK)
259 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
261 switch (debug_reason)
264 DEBUG("breakpoint from EICE unit 0");
265 target->debug_reason = DBG_REASON_BREAKPOINT;
268 DEBUG("breakpoint from EICE unit 1");
269 target->debug_reason = DBG_REASON_BREAKPOINT;
272 DEBUG("soft breakpoint (BKPT instruction)");
273 target->debug_reason = DBG_REASON_BREAKPOINT;
276 DEBUG("vector catch breakpoint");
277 target->debug_reason = DBG_REASON_BREAKPOINT;
280 DEBUG("external breakpoint");
281 target->debug_reason = DBG_REASON_BREAKPOINT;
284 DEBUG("watchpoint from EICE unit 0");
285 target->debug_reason = DBG_REASON_WATCHPOINT;
288 DEBUG("watchpoint from EICE unit 1");
289 target->debug_reason = DBG_REASON_WATCHPOINT;
292 DEBUG("external watchpoint");
293 target->debug_reason = DBG_REASON_WATCHPOINT;
296 DEBUG("internal debug request");
297 target->debug_reason = DBG_REASON_DBGRQ;
300 DEBUG("external debug request");
301 target->debug_reason = DBG_REASON_DBGRQ;
304 ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
307 ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
308 target->debug_reason = DBG_REASON_DBGRQ;
314 u32 arm926ejs_get_ttb(target_t *target)
319 if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 2, 0), &ttb)) != ERROR_OK)
325 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
329 /* read cp15 control register */
330 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
331 jtag_execute_queue();
336 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 8, 7), 0x0);
338 cp15_control &= ~0x1U;
344 /* read-modify-write CP15 debug override register
345 * to enable "test and clean all" */
346 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), &debug_override);
347 debug_override |= 0x80000;
348 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
350 /* clean and invalidate DCache */
351 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
353 /* write CP15 debug override register
354 * to disable "test and clean all" */
355 debug_override &= ~0x80000;
356 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 15, 0), debug_override);
358 cp15_control &= ~0x4U;
363 /* invalidate ICache */
364 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), 0x0);
366 cp15_control &= ~0x1000U;
369 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
372 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
376 /* read cp15 control register */
377 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &cp15_control);
378 jtag_execute_queue();
381 cp15_control |= 0x1U;
384 cp15_control |= 0x4U;
387 cp15_control |= 0x1000U;
389 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), cp15_control);
392 void arm926ejs_post_debug_entry(target_t *target)
394 armv4_5_common_t *armv4_5 = target->arch_info;
395 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
396 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
397 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
399 /* examine cp15 control reg */
400 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 1, 0), &arm926ejs->cp15_control_reg);
401 jtag_execute_queue();
402 DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
404 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
407 /* identify caches */
408 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 0, 0), &cache_type_reg);
409 jtag_execute_queue();
410 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
413 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
414 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
415 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
417 /* save i/d fault status and address register */
418 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), &arm926ejs->d_fsr);
419 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), &arm926ejs->i_fsr);
420 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), &arm926ejs->d_far);
422 DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
423 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
428 /* read-modify-write CP15 cache debug control register
429 * to disable I/D-cache linefills and force WT */
430 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
431 cache_dbg_ctrl |= 0x7;
432 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
436 void arm926ejs_pre_restore_context(target_t *target)
438 armv4_5_common_t *armv4_5 = target->arch_info;
439 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
440 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
441 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
443 /* restore i/d fault status and address register */
444 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 5, 0), arm926ejs->d_fsr);
445 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 5, 0), arm926ejs->i_fsr);
446 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 6, 0), arm926ejs->d_far);
450 /* read-modify-write CP15 cache debug control register
451 * to reenable I/D-cache linefills and disable WT */
452 arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
453 cache_dbg_ctrl |= 0x7;
454 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
457 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
459 armv4_5_common_t *armv4_5 = target->arch_info;
460 arm7_9_common_t *arm7_9;
461 arm9tdmi_common_t *arm9tdmi;
462 arm926ejs_common_t *arm926ejs;
464 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
469 arm7_9 = armv4_5->arch_info;
470 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
475 arm9tdmi = arm7_9->arch_info;
476 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
481 arm926ejs = arm9tdmi->arch_info;
482 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
487 *armv4_5_p = armv4_5;
489 *arm9tdmi_p = arm9tdmi;
490 *arm926ejs_p = arm926ejs;
495 int arm926ejs_arch_state(struct target_s *target, char *buf, int buf_size)
497 armv4_5_common_t *armv4_5 = target->arch_info;
498 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
499 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
500 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
504 "disabled", "enabled"
507 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
509 ERROR("BUG: called for a non-ARMv4/5 target");
513 snprintf(buf, buf_size,
514 "target halted in %s state due to %s, current mode: %s\n"
515 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
516 "MMU: %s, D-Cache: %s, I-Cache: %s",
517 armv4_5_state_strings[armv4_5->core_state],
518 target_debug_reason_strings[target->debug_reason],
519 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
520 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
521 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
522 state[arm926ejs->armv4_5_mmu.mmu_enabled],
523 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
524 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
529 int arm926ejs_soft_reset_halt(struct target_s *target)
531 armv4_5_common_t *armv4_5 = target->arch_info;
532 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
533 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
534 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
535 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
537 if (target->state == TARGET_RUNNING)
539 target->type->halt(target);
542 while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
544 embeddedice_read_reg(dbg_stat);
545 jtag_execute_queue();
548 target->state = TARGET_HALTED;
550 /* SVC, ARM state, IRQ and FIQ disabled */
551 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
552 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
553 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
555 /* start fetching from 0x0 */
556 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
557 armv4_5->core_cache->reg_list[15].dirty = 1;
558 armv4_5->core_cache->reg_list[15].valid = 1;
560 armv4_5->core_mode = ARMV4_5_MODE_SVC;
561 armv4_5->core_state = ARMV4_5_STATE_ARM;
563 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
564 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
565 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
566 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
568 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
573 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
576 armv4_5_common_t *armv4_5 = target->arch_info;
577 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
578 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
579 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
581 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
584 /* If ICache is enabled, we have to invalidate affected ICache lines
585 * the DCache is forced to write-through, so we don't have to clean it here
587 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
591 /* invalidate ICache single entry with MVA */
592 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 1, 7, 5), address);
596 /* invalidate ICache */
597 arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(0, 0, 7, 5), address);
604 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
606 arm9tdmi_init_target(cmd_ctx, target);
618 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
620 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
621 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
623 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
625 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
627 arm9tdmi->arch_info = arm926ejs;
628 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
630 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
631 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
633 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
634 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
635 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
636 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
637 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
638 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
639 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
640 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
642 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
647 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
650 char *variant = NULL;
651 arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
655 ERROR("'target arm926ejs' requires at least one additional argument");
659 chain_pos = strtoul(args[3], NULL, 0);
664 DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
666 arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
671 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
674 command_t *arm926ejs_cmd;
677 retval = arm9tdmi_register_commands(cmd_ctx);
679 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
681 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
683 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
684 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
686 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
687 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
688 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
690 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
691 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
692 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
697 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
700 target_t *target = get_current_target(cmd_ctx);
701 armv4_5_common_t *armv4_5;
702 arm7_9_common_t *arm7_9;
703 arm9tdmi_common_t *arm9tdmi;
704 arm926ejs_common_t *arm926ejs;
710 if ((argc < 4) || (argc > 5))
712 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
716 opcode_1 = strtoul(args[0], NULL, 0);
717 opcode_2 = strtoul(args[1], NULL, 0);
718 CRn = strtoul(args[2], NULL, 0);
719 CRm = strtoul(args[3], NULL, 0);
721 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
723 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
727 if (target->state != TARGET_HALTED)
729 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
736 if ((retval = arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), &value)) != ERROR_OK)
738 command_print(cmd_ctx, "couldn't access register");
741 jtag_execute_queue();
743 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
747 u32 value = strtoul(args[4], NULL, 0);
748 if ((retval = arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm), value)) != ERROR_OK)
750 command_print(cmd_ctx, "couldn't access register");
753 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
759 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
761 target_t *target = get_current_target(cmd_ctx);
762 armv4_5_common_t *armv4_5;
763 arm7_9_common_t *arm7_9;
764 arm9tdmi_common_t *arm9tdmi;
765 arm926ejs_common_t *arm926ejs;
767 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
769 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
773 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
776 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
778 target_t *target = get_current_target(cmd_ctx);
779 armv4_5_common_t *armv4_5;
780 arm7_9_common_t *arm7_9;
781 arm9tdmi_common_t *arm9tdmi;
782 arm926ejs_common_t *arm926ejs;
783 arm_jtag_t *jtag_info;
785 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
787 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
791 jtag_info = &arm7_9->jtag_info;
793 if (target->state != TARGET_HALTED)
795 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
799 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
802 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
804 target_t *target = get_current_target(cmd_ctx);
805 armv4_5_common_t *armv4_5;
806 arm7_9_common_t *arm7_9;
807 arm9tdmi_common_t *arm9tdmi;
808 arm926ejs_common_t *arm926ejs;
809 arm_jtag_t *jtag_info;
811 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
813 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
817 jtag_info = &arm7_9->jtag_info;
819 if (target->state != TARGET_HALTED)
821 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
825 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
828 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
830 target_t *target = get_current_target(cmd_ctx);
831 armv4_5_common_t *armv4_5;
832 arm7_9_common_t *arm7_9;
833 arm9tdmi_common_t *arm9tdmi;
834 arm926ejs_common_t *arm926ejs;
835 arm_jtag_t *jtag_info;
837 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
839 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
843 jtag_info = &arm7_9->jtag_info;
845 if (target->state != TARGET_HALTED)
847 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
851 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);