git.gag.com Git - fw/openocd/blob - src/target/arm926ejs.c

   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "time_support.h"
  26 #include "target_type.h"
  27
  28
  29 #if 0
  30 #define _DEBUG_INSTRUCTION_EXECUTION_
  31 #endif
  32
  33 /* cli handling */
  34 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  35 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  36 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  37 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  38 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40
  41 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 /* forward declarations */
  45 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
  46 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  47 int arm926ejs_quit(void);
  48 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  49
  50 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
  51 static int arm926ejs_mmu(struct target_s *target, int *enabled);
  52
  53 target_type_t arm926ejs_target =
  54 {
  55         .name = "arm926ejs",
  56
  57         .poll = arm7_9_poll,
  58         .arch_state = arm926ejs_arch_state,
  59
  60         .target_request_data = arm7_9_target_request_data,
  61
  62         .halt = arm7_9_halt,
  63         .resume = arm7_9_resume,
  64         .step = arm7_9_step,
  65
  66         .assert_reset = arm7_9_assert_reset,
  67         .deassert_reset = arm7_9_deassert_reset,
  68         .soft_reset_halt = arm926ejs_soft_reset_halt,
  69
  70         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  71
  72         .read_memory = arm7_9_read_memory,
  73         .write_memory = arm926ejs_write_memory,
  74         .bulk_write_memory = arm7_9_bulk_write_memory,
  75         .checksum_memory = arm7_9_checksum_memory,
  76         .blank_check_memory = arm7_9_blank_check_memory,
  77
  78         .run_algorithm = armv4_5_run_algorithm,
  79
  80         .add_breakpoint = arm7_9_add_breakpoint,
  81         .remove_breakpoint = arm7_9_remove_breakpoint,
  82         .add_watchpoint = arm7_9_add_watchpoint,
  83         .remove_watchpoint = arm7_9_remove_watchpoint,
  84
  85         .register_commands = arm926ejs_register_commands,
  86         .target_create = arm926ejs_target_create,
  87         .init_target = arm926ejs_init_target,
  88         .examine = arm9tdmi_examine,
  89         .quit = arm926ejs_quit,
  90         .virt2phys = arm926ejs_virt2phys,
  91         .mmu = arm926ejs_mmu
  92 };
  93
  94 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
  95 {
  96         /* FIX!!!! this code should be reenabled. For now it does not check
  97          * the queue...*/
  98         return 0;
  99 #if 0
 100         /* The ARM926EJ-S' instruction register is 4 bits wide */
 101         u8 t = *captured & 0xf;
 102         u8 t2 = *field->in_check_value & 0xf;
 103         if (t == t2)
 104         {
 105                 return ERROR_OK;
 106         }
 107         else if ((t == 0x0f) || (t == 0x00))
 108         {
 109                 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 110                 return ERROR_OK;
 111         }
 112         return ERROR_JTAG_QUEUE_FAILED;;
 113 #endif
 114 }
 115
 116 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
 117
 118 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
 119 {
 120         int retval = ERROR_OK;
 121         armv4_5_common_t *armv4_5 = target->arch_info;
 122         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 123         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 124         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 125         scan_field_t fields[4];
 126         u8 address_buf[2];
 127         u8 nr_w_buf = 0;
 128         u8 access = 1;
 129
 130         buf_set_u32(address_buf, 0, 14, address);
 131
 132         jtag_set_end_state(TAP_IDLE);
 133         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 134         {
 135                 return retval;
 136         }
 137         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 138
 139         fields[0].tap = jtag_info->tap;
 140         fields[0].num_bits = 32;
 141         fields[0].out_value = NULL;
 142         fields[0].in_value = (u8 *)value;
 143
 144
 145         fields[1].tap = jtag_info->tap;
 146         fields[1].num_bits = 1;
 147         fields[1].out_value = &access;
 148         fields[1].in_value = &access;
 149
 150         fields[2].tap = jtag_info->tap;
 151         fields[2].num_bits = 14;
 152         fields[2].out_value = address_buf;
 153         fields[2].in_value = NULL;
 154
 155         fields[3].tap = jtag_info->tap;
 156         fields[3].num_bits = 1;
 157         fields[3].out_value = &nr_w_buf;
 158         fields[3].in_value = NULL;
 159
 160         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 161
 162         /*TODO: add timeout*/
 163         do
 164         {
 165                 /* rescan with NOP, to wait for the access to complete */
 166                 access = 0;
 167                 nr_w_buf = 0;
 168                 jtag_add_dr_scan(4, fields, jtag_get_end_state());
 169
 170                 jtag_add_callback(arm_le_to_h_u32, (u8 *)value);
 171
 172                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 173                 {
 174                         return retval;
 175                 }
 176         } while (buf_get_u32(&access, 0, 1) != 1);
 177
 178 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 179         LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 180 #endif
 181
 182         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 183
 184         return ERROR_OK;
 185 }
 186
 187 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
 188 {
 189         int retval = ERROR_OK;
 190         armv4_5_common_t *armv4_5 = target->arch_info;
 191         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 192         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 193         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 194         scan_field_t fields[4];
 195         u8 value_buf[4];
 196         u8 address_buf[2];
 197         u8 nr_w_buf = 1;
 198         u8 access = 1;
 199
 200         buf_set_u32(address_buf, 0, 14, address);
 201         buf_set_u32(value_buf, 0, 32, value);
 202
 203         jtag_set_end_state(TAP_IDLE);
 204         if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
 205         {
 206                 return retval;
 207         }
 208         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 209
 210         fields[0].tap = jtag_info->tap;
 211         fields[0].num_bits = 32;
 212         fields[0].out_value = value_buf;
 213         fields[0].in_value = NULL;
 214
 215         fields[1].tap = jtag_info->tap;
 216         fields[1].num_bits = 1;
 217         fields[1].out_value = &access;
 218         fields[1].in_value = &access;
 219
 220         fields[2].tap = jtag_info->tap;
 221         fields[2].num_bits = 14;
 222         fields[2].out_value = address_buf;
 223         fields[2].in_value = NULL;
 224
 225         fields[3].tap = jtag_info->tap;
 226         fields[3].num_bits = 1;
 227         fields[3].out_value = &nr_w_buf;
 228         fields[3].in_value = NULL;
 229
 230         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 231         /*TODO: add timeout*/
 232         do
 233         {
 234                 /* rescan with NOP, to wait for the access to complete */
 235                 access = 0;
 236                 nr_w_buf = 0;
 237                 jtag_add_dr_scan(4, fields, jtag_get_end_state());
 238                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 239                 {
 240                         return retval;
 241                 }
 242         } while (buf_get_u32(&access, 0, 1) != 1);
 243
 244 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 245         LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 246 #endif
 247
 248         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 249
 250         return ERROR_OK;
 251 }
 252
 253 int arm926ejs_examine_debug_reason(target_t *target)
 254 {
 255         armv4_5_common_t *armv4_5 = target->arch_info;
 256         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 257         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 258         int debug_reason;
 259         int retval;
 260
 261         embeddedice_read_reg(dbg_stat);
 262         if ((retval = jtag_execute_queue()) != ERROR_OK)
 263                 return retval;
 264
 265         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 266
 267         switch (debug_reason)
 268         {
 269                 case 1:
 270                         LOG_DEBUG("breakpoint from EICE unit 0");
 271                         target->debug_reason = DBG_REASON_BREAKPOINT;
 272                         break;
 273                 case 2:
 274                         LOG_DEBUG("breakpoint from EICE unit 1");
 275                         target->debug_reason = DBG_REASON_BREAKPOINT;
 276                         break;
 277                 case 3:
 278                         LOG_DEBUG("soft breakpoint (BKPT instruction)");
 279                         target->debug_reason = DBG_REASON_BREAKPOINT;
 280                         break;
 281                 case 4:
 282                         LOG_DEBUG("vector catch breakpoint");
 283                         target->debug_reason = DBG_REASON_BREAKPOINT;
 284                         break;
 285                 case 5:
 286                         LOG_DEBUG("external breakpoint");
 287                         target->debug_reason = DBG_REASON_BREAKPOINT;
 288                         break;
 289                 case 6:
 290                         LOG_DEBUG("watchpoint from EICE unit 0");
 291                         target->debug_reason = DBG_REASON_WATCHPOINT;
 292                         break;
 293                 case 7:
 294                         LOG_DEBUG("watchpoint from EICE unit 1");
 295                         target->debug_reason = DBG_REASON_WATCHPOINT;
 296                         break;
 297                 case 8:
 298                         LOG_DEBUG("external watchpoint");
 299                         target->debug_reason = DBG_REASON_WATCHPOINT;
 300                         break;
 301                 case 9:
 302                         LOG_DEBUG("internal debug request");
 303                         target->debug_reason = DBG_REASON_DBGRQ;
 304                         break;
 305                 case 10:
 306                         LOG_DEBUG("external debug request");
 307                         target->debug_reason = DBG_REASON_DBGRQ;
 308                         break;
 309                 case 11:
 310                         LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 311                         break;
 312                 case 12:
 313                         /* FIX!!!! here be dragons!!! We need to fail here so
 314                          * the target will interpreted as halted but we won't
 315                          * try to talk to it right now... a resume + halt seems
 316                          * to sync things up again. Please send an email to
 317                          * openocd development mailing list if you have hardware
 318                          * to donate to look into this problem....
 319                          */
 320                         LOG_ERROR("mystery debug reason MOE=0xc. Try issuing a resume + halt.");
 321                         target->debug_reason = DBG_REASON_DBGRQ;
 322                         retval = ERROR_TARGET_FAILURE;
 323                         break;
 324                 default:
 325                         LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 326                         target->debug_reason = DBG_REASON_DBGRQ;
 327                         /* if we fail here, we won't talk to the target and it will
 328                          * be reported to be in the halted state */
 329                         retval = ERROR_TARGET_FAILURE;
 330                         break;
 331         }
 332
 333         return retval;
 334 }
 335
 336 u32 arm926ejs_get_ttb(target_t *target)
 337 {
 338         armv4_5_common_t *armv4_5 = target->arch_info;
 339         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 340         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 341         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 342         int retval;
 343         u32 ttb = 0x0;
 344
 345         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
 346                 return retval;
 347
 348         return ttb;
 349 }
 350
 351 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 352 {
 353         armv4_5_common_t *armv4_5 = target->arch_info;
 354         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 355         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 356         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 357         u32 cp15_control;
 358
 359         /* read cp15 control register */
 360         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 361         jtag_execute_queue();
 362
 363         if (mmu)
 364         {
 365                 /* invalidate TLB */
 366                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
 367
 368                 cp15_control &= ~0x1U;
 369         }
 370
 371         if (d_u_cache)
 372         {
 373                 u32 debug_override;
 374                 /* read-modify-write CP15 debug override register
 375                  * to enable "test and clean all" */
 376                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
 377                 debug_override |= 0x80000;
 378                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 379
 380                 /* clean and invalidate DCache */
 381                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 382
 383                 /* write CP15 debug override register
 384                  * to disable "test and clean all" */
 385                 debug_override &= ~0x80000;
 386                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 387
 388                 cp15_control &= ~0x4U;
 389         }
 390
 391         if (i_cache)
 392         {
 393                 /* invalidate ICache */
 394                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 395
 396                 cp15_control &= ~0x1000U;
 397         }
 398
 399         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 400 }
 401
 402 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 403 {
 404         armv4_5_common_t *armv4_5 = target->arch_info;
 405         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 406         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 407         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 408         u32 cp15_control;
 409
 410         /* read cp15 control register */
 411         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 412         jtag_execute_queue();
 413
 414         if (mmu)
 415                 cp15_control |= 0x1U;
 416
 417         if (d_u_cache)
 418                 cp15_control |= 0x4U;
 419
 420         if (i_cache)
 421                 cp15_control |= 0x1000U;
 422
 423         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 424 }
 425
 426 void arm926ejs_post_debug_entry(target_t *target)
 427 {
 428         armv4_5_common_t *armv4_5 = target->arch_info;
 429         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 430         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 431         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 432
 433         /* examine cp15 control reg */
 434         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 435         jtag_execute_queue();
 436         LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 437
 438         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 439         {
 440                 u32 cache_type_reg;
 441                 /* identify caches */
 442                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
 443                 jtag_execute_queue();
 444                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 445         }
 446
 447         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 448         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 449         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 450
 451         /* save i/d fault status and address register */
 452         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
 453         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 454         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 455
 456         LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 457                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 458
 459         u32 cache_dbg_ctrl;
 460
 461         /* read-modify-write CP15 cache debug control register
 462          * to disable I/D-cache linefills and force WT */
 463         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 464         cache_dbg_ctrl |= 0x7;
 465         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 466 }
 467
 468 void arm926ejs_pre_restore_context(target_t *target)
 469 {
 470         armv4_5_common_t *armv4_5 = target->arch_info;
 471         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 472         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 473         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 474
 475         /* restore i/d fault status and address register */
 476         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
 477         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
 478         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
 479
 480         u32 cache_dbg_ctrl;
 481
 482         /* read-modify-write CP15 cache debug control register
 483          * to reenable I/D-cache linefills and disable WT */
 484         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 485         cache_dbg_ctrl &= ~0x7;
 486         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 487 }
 488
 489 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 490 {
 491         armv4_5_common_t *armv4_5 = target->arch_info;
 492         arm7_9_common_t *arm7_9;
 493         arm9tdmi_common_t *arm9tdmi;
 494         arm926ejs_common_t *arm926ejs;
 495
 496         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 497         {
 498                 return -1;
 499         }
 500
 501         arm7_9 = armv4_5->arch_info;
 502         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 503         {
 504                 return -1;
 505         }
 506
 507         arm9tdmi = arm7_9->arch_info;
 508         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 509         {
 510                 return -1;
 511         }
 512
 513         arm926ejs = arm9tdmi->arch_info;
 514         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 515         {
 516                 return -1;
 517         }
 518
 519         *armv4_5_p = armv4_5;
 520         *arm7_9_p = arm7_9;
 521         *arm9tdmi_p = arm9tdmi;
 522         *arm926ejs_p = arm926ejs;
 523
 524         return ERROR_OK;
 525 }
 526
 527 int arm926ejs_arch_state(struct target_s *target)
 528 {
 529         armv4_5_common_t *armv4_5 = target->arch_info;
 530         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 531         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 532         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 533
 534         char *state[] =
 535         {
 536                 "disabled", "enabled"
 537         };
 538
 539         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 540         {
 541                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 542                 exit(-1);
 543         }
 544
 545         LOG_USER(
 546                         "target halted in %s state due to %s, current mode: %s\n"
 547                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 548                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 549                          armv4_5_state_strings[armv4_5->core_state],
 550                          Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 551                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 552                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 553                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 554                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 555                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 556                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 557
 558         return ERROR_OK;
 559 }
 560
 561 int arm926ejs_soft_reset_halt(struct target_s *target)
 562 {
 563         int retval = ERROR_OK;
 564         armv4_5_common_t *armv4_5 = target->arch_info;
 565         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 566         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 567         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 568         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 569
 570         if ((retval = target_halt(target)) != ERROR_OK)
 571         {
 572                 return retval;
 573         }
 574
 575         long long then=timeval_ms();
 576         int timeout;
 577         while (!(timeout=((timeval_ms()-then)>1000)))
 578         {
 579                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 580                 {
 581                         embeddedice_read_reg(dbg_stat);
 582                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 583                         {
 584                                 return retval;
 585                         }
 586                 }  else
 587                 {
 588                         break;
 589                 }
 590                 if (debug_level>=1)
 591                 {
 592                         /* do not eat all CPU, time out after 1 se*/
 593                         alive_sleep(100);
 594                 } else
 595                 {
 596                         keep_alive();
 597                 }
 598         }
 599         if (timeout)
 600         {
 601                 LOG_ERROR("Failed to halt CPU after 1 sec");
 602                 return ERROR_TARGET_TIMEOUT;
 603         }
 604
 605         target->state = TARGET_HALTED;
 606
 607         /* SVC, ARM state, IRQ and FIQ disabled */
 608         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 609         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 610         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 611
 612         /* start fetching from 0x0 */
 613         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 614         armv4_5->core_cache->reg_list[15].dirty = 1;
 615         armv4_5->core_cache->reg_list[15].valid = 1;
 616
 617         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 618         armv4_5->core_state = ARMV4_5_STATE_ARM;
 619
 620         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 621         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 622         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 623         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 624
 625         return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 626 }
 627
 628 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 629 {
 630         int retval;
 631         armv4_5_common_t *armv4_5 = target->arch_info;
 632         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 633         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 634         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 635
 636         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 637                 return retval;
 638
 639         /* If ICache is enabled, we have to invalidate affected ICache lines
 640          * the DCache is forced to write-through, so we don't have to clean it here
 641          */
 642         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 643         {
 644                 if (count <= 1)
 645                 {
 646                         /* invalidate ICache single entry with MVA */
 647                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
 648                 }
 649                 else
 650                 {
 651                         /* invalidate ICache */
 652                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
 653                 }
 654         }
 655
 656         return retval;
 657 }
 658
 659 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 660 {
 661         arm9tdmi_init_target(cmd_ctx, target);
 662
 663         return ERROR_OK;
 664 }
 665
 666 int arm926ejs_quit(void)
 667 {
 668         return ERROR_OK;
 669 }
 670
 671 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, jtag_tap_t *tap)
 672 {
 673         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 674         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 675
 676         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 677          */
 678         arm9tdmi_init_arch_info(target, arm9tdmi, tap);
 679
 680         arm9tdmi->arch_info = arm926ejs;
 681         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 682
 683         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 684         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 685
 686         arm926ejs->read_cp15 = arm926ejs_cp15_read;
 687         arm926ejs->write_cp15 = arm926ejs_cp15_write;
 688         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 689         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 690         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 691         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 692         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 693         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 694         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 695         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 696
 697         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 698
 699         /* The ARM926EJ-S implements the ARMv5TE architecture which
 700          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 701          */
 702         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 703         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 704
 705         return ERROR_OK;
 706 }
 707
 708 int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp)
 709 {
 710         arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
 711
 712         arm926ejs_init_arch_info(target, arm926ejs, target->tap);
 713
 714         return ERROR_OK;
 715 }
 716
 717 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 718 {
 719         int retval;
 720         command_t *arm926ejs_cmd;
 721
 722
 723         retval = arm9tdmi_register_commands(cmd_ctx);
 724
 725         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 726
 727         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 728
 729         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 730         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 731
 732         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 733         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 734         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 735
 736         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 737         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 738         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 739
 740         return retval;
 741 }
 742
 743 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 744 {
 745         int retval;
 746         target_t *target = get_current_target(cmd_ctx);
 747         armv4_5_common_t *armv4_5;
 748         arm7_9_common_t *arm7_9;
 749         arm9tdmi_common_t *arm9tdmi;
 750         arm926ejs_common_t *arm926ejs;
 751         int opcode_1;
 752         int opcode_2;
 753         int CRn;
 754         int CRm;
 755
 756         if ((argc < 4) || (argc > 5))
 757         {
 758                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 759                 return ERROR_OK;
 760         }
 761
 762         opcode_1 = strtoul(args[0], NULL, 0);
 763         opcode_2 = strtoul(args[1], NULL, 0);
 764         CRn = strtoul(args[2], NULL, 0);
 765         CRm = strtoul(args[3], NULL, 0);
 766
 767         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 768         {
 769                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 770                 return ERROR_OK;
 771         }
 772
 773         if (target->state != TARGET_HALTED)
 774         {
 775                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 776                 return ERROR_OK;
 777         }
 778
 779         if (argc == 4)
 780         {
 781                 u32 value;
 782                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
 783                 {
 784                         command_print(cmd_ctx, "couldn't access register");
 785                         return ERROR_OK;
 786                 }
 787                 if ((retval = jtag_execute_queue()) != ERROR_OK)
 788                 {
 789                         return retval;
 790                 }
 791
 792                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 793         }
 794         else
 795         {
 796                 u32 value = strtoul(args[4], NULL, 0);
 797                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
 798                 {
 799                         command_print(cmd_ctx, "couldn't access register");
 800                         return ERROR_OK;
 801                 }
 802                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 803         }
 804
 805         return ERROR_OK;
 806 }
 807
 808 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 809 {
 810         target_t *target = get_current_target(cmd_ctx);
 811         armv4_5_common_t *armv4_5;
 812         arm7_9_common_t *arm7_9;
 813         arm9tdmi_common_t *arm9tdmi;
 814         arm926ejs_common_t *arm926ejs;
 815
 816         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 817         {
 818                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 819                 return ERROR_OK;
 820         }
 821
 822         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 823 }
 824
 825 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 826 {
 827         target_t *target = get_current_target(cmd_ctx);
 828         armv4_5_common_t *armv4_5;
 829         arm7_9_common_t *arm7_9;
 830         arm9tdmi_common_t *arm9tdmi;
 831         arm926ejs_common_t *arm926ejs;
 832         arm_jtag_t *jtag_info;
 833
 834         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 835         {
 836                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 837                 return ERROR_OK;
 838         }
 839
 840         jtag_info = &arm7_9->jtag_info;
 841
 842         if (target->state != TARGET_HALTED)
 843         {
 844                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 845                 return ERROR_OK;
 846         }
 847
 848         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 849 }
 850
 851 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 852 {
 853         target_t *target = get_current_target(cmd_ctx);
 854         armv4_5_common_t *armv4_5;
 855         arm7_9_common_t *arm7_9;
 856         arm9tdmi_common_t *arm9tdmi;
 857         arm926ejs_common_t *arm926ejs;
 858         arm_jtag_t *jtag_info;
 859
 860         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 861         {
 862                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 863                 return ERROR_OK;
 864         }
 865
 866         jtag_info = &arm7_9->jtag_info;
 867
 868         if (target->state != TARGET_HALTED)
 869         {
 870                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 871                 return ERROR_OK;
 872         }
 873
 874         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 875 }
 876
 877 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 878 {
 879         target_t *target = get_current_target(cmd_ctx);
 880         armv4_5_common_t *armv4_5;
 881         arm7_9_common_t *arm7_9;
 882         arm9tdmi_common_t *arm9tdmi;
 883         arm926ejs_common_t *arm926ejs;
 884         arm_jtag_t *jtag_info;
 885
 886         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 887         {
 888                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 889                 return ERROR_OK;
 890         }
 891
 892         jtag_info = &arm7_9->jtag_info;
 893
 894         if (target->state != TARGET_HALTED)
 895         {
 896                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 897                 return ERROR_OK;
 898         }
 899
 900         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 901 }
 902
 903 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 904 {
 905         int retval;
 906         int type;
 907         u32 cb;
 908         int domain;
 909         u32 ap;
 910
 911         armv4_5_common_t *armv4_5;
 912         arm7_9_common_t *arm7_9;
 913         arm9tdmi_common_t *arm9tdmi;
 914         arm926ejs_common_t *arm926ejs;
 915         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
 916         if (retval != ERROR_OK)
 917         {
 918                 return retval;
 919         }
 920         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 921         if (type == -1)
 922         {
 923                 return ret;
 924         }
 925         *physical = ret;
 926         return ERROR_OK;
 927 }
 928
 929 static int arm926ejs_mmu(struct target_s *target, int *enabled)
 930 {
 931         armv4_5_common_t *armv4_5 = target->arch_info;
 932         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
 933
 934         if (target->state != TARGET_HALTED)
 935         {
 936                 LOG_ERROR("Target not halted");
 937                 return ERROR_TARGET_INVALID;
 938         }
 939         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
 940         return ERROR_OK;
 941 }