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   1 /***************************************************************************
   2  *   Copyright (C) 2007 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm926ejs.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 1
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm926ejs_quit();
  52 int arm926ejs_arch_state(struct target_s *target);
  53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm926ejs_soft_reset_halt(struct target_s *target);
  56 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
  57 static int arm926ejs_mmu(struct target_s *target, int *enabled);
  58
  59 target_type_t arm926ejs_target =
  60 {
  61         .name = "arm926ejs",
  62
  63         .poll = arm7_9_poll,
  64         .arch_state = arm926ejs_arch_state,
  65
  66         .target_request_data = arm7_9_target_request_data,
  67
  68         .halt = arm7_9_halt,
  69         .resume = arm7_9_resume,
  70         .step = arm7_9_step,
  71
  72         .assert_reset = arm7_9_assert_reset,
  73         .deassert_reset = arm7_9_deassert_reset,
  74         .soft_reset_halt = arm926ejs_soft_reset_halt,
  75         .prepare_reset_halt = arm7_9_prepare_reset_halt,
  76
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  78
  79         .read_memory = arm7_9_read_memory,
  80         .write_memory = arm926ejs_write_memory,
  81         .bulk_write_memory = arm7_9_bulk_write_memory,
  82         .checksum_memory = arm7_9_checksum_memory,
  83
  84         .run_algorithm = armv4_5_run_algorithm,
  85
  86         .add_breakpoint = arm7_9_add_breakpoint,
  87         .remove_breakpoint = arm7_9_remove_breakpoint,
  88         .add_watchpoint = arm7_9_add_watchpoint,
  89         .remove_watchpoint = arm7_9_remove_watchpoint,
  90
  91         .register_commands = arm926ejs_register_commands,
  92         .target_command = arm926ejs_target_command,
  93         .init_target = arm926ejs_init_target,
  94         .quit = arm926ejs_quit,
  95         .virt2phys = arm926ejs_virt2phys,
  96         .mmu = arm926ejs_mmu
  97 };
  98
  99
 100 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 101 {
 102         /* The ARM926EJ-S' instruction register is 4 bits wide */
 103         u8 t = *captured & 0xf;
 104         u8 t2 = *field->in_check_value & 0xf;
 105         if (t == t2)
 106         {
 107                 return ERROR_OK;
 108         }
 109         else if ((t == 0x0f) || (t == 0x00))
 110         {
 111                 DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
 112                 return ERROR_OK;
 113         }
 114         return ERROR_JTAG_QUEUE_FAILED;;
 115 }
 116
 117 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
 118
 119 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
 120 {
 121         armv4_5_common_t *armv4_5 = target->arch_info;
 122         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 123         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 124         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 125         scan_field_t fields[4];
 126         u8 address_buf[2];
 127         u8 nr_w_buf = 0;
 128         u8 access = 1;
 129
 130         buf_set_u32(address_buf, 0, 14, address);
 131
 132         jtag_add_end_state(TAP_RTI);
 133         arm_jtag_scann(jtag_info, 0xf);
 134         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 135
 136         fields[0].device = jtag_info->chain_pos;
 137         fields[0].num_bits = 32;
 138         fields[0].out_value = NULL;
 139         fields[0].out_mask = NULL;
 140         fields[0].in_value = NULL;
 141         fields[0].in_check_value = NULL;
 142         fields[0].in_check_mask = NULL;
 143         fields[0].in_handler = NULL;
 144         fields[0].in_handler_priv = NULL;
 145
 146         fields[1].device = jtag_info->chain_pos;
 147         fields[1].num_bits = 1;
 148         fields[1].out_value = &access;
 149         fields[1].out_mask = NULL;
 150         fields[1].in_value = &access;
 151         fields[1].in_check_value = NULL;
 152         fields[1].in_check_mask = NULL;
 153         fields[1].in_handler = NULL;
 154         fields[1].in_handler_priv = NULL;
 155
 156         fields[2].device = jtag_info->chain_pos;
 157         fields[2].num_bits = 14;
 158         fields[2].out_value = address_buf;
 159         fields[2].out_mask = NULL;
 160         fields[2].in_value = NULL;
 161         fields[2].in_check_value = NULL;
 162         fields[2].in_check_mask = NULL;
 163         fields[2].in_handler = NULL;
 164         fields[2].in_handler_priv = NULL;
 165
 166         fields[3].device = jtag_info->chain_pos;
 167         fields[3].num_bits = 1;
 168         fields[3].out_value = &nr_w_buf;
 169         fields[3].out_mask = NULL;
 170         fields[3].in_value = NULL;
 171         fields[3].in_check_value = NULL;
 172         fields[3].in_check_mask = NULL;
 173         fields[3].in_handler = NULL;
 174         fields[3].in_handler_priv = NULL;
 175
 176         jtag_add_dr_scan(4, fields, -1, NULL);
 177
 178         fields[0].in_handler_priv = value;
 179         fields[0].in_handler = arm_jtag_buf_to_u32;
 180
 181         do
 182         {
 183                 /* rescan with NOP, to wait for the access to complete */
 184                 access = 0;
 185                 nr_w_buf = 0;
 186                 jtag_add_dr_scan(4, fields, -1, NULL);
 187                 jtag_execute_queue();
 188         } while (buf_get_u32(&access, 0, 1) != 1);
 189
 190 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 191         DEBUG("addr: 0x%x value: %8.8x", address, *value);
 192 #endif
 193
 194         arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 195
 196         return ERROR_OK;
 197 }
 198
 199 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
 200 {
 201         armv4_5_common_t *armv4_5 = target->arch_info;
 202         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 203         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 204         u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
 205         scan_field_t fields[4];
 206         u8 value_buf[4];
 207         u8 address_buf[2];
 208         u8 nr_w_buf = 1;
 209         u8 access = 1;
 210
 211         buf_set_u32(address_buf, 0, 14, address);
 212         buf_set_u32(value_buf, 0, 32, value);
 213
 214         jtag_add_end_state(TAP_RTI);
 215         arm_jtag_scann(jtag_info, 0xf);
 216         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 217
 218         fields[0].device = jtag_info->chain_pos;
 219         fields[0].num_bits = 32;
 220         fields[0].out_value = value_buf;
 221         fields[0].out_mask = NULL;
 222         fields[0].in_value = NULL;
 223         fields[0].in_check_value = NULL;
 224         fields[0].in_check_mask = NULL;
 225         fields[0].in_handler = NULL;
 226         fields[0].in_handler_priv = NULL;
 227
 228         fields[1].device = jtag_info->chain_pos;
 229         fields[1].num_bits = 1;
 230         fields[1].out_value = &access;
 231         fields[1].out_mask = NULL;
 232         fields[1].in_value = &access;
 233         fields[1].in_check_value = NULL;
 234         fields[1].in_check_mask = NULL;
 235         fields[1].in_handler = NULL;
 236         fields[1].in_handler_priv = NULL;
 237
 238         fields[2].device = jtag_info->chain_pos;
 239         fields[2].num_bits = 14;
 240         fields[2].out_value = address_buf;
 241         fields[2].out_mask = NULL;
 242         fields[2].in_value = NULL;
 243         fields[2].in_check_value = NULL;
 244         fields[2].in_check_mask = NULL;
 245         fields[2].in_handler = NULL;
 246         fields[2].in_handler_priv = NULL;
 247
 248         fields[3].device = jtag_info->chain_pos;
 249         fields[3].num_bits = 1;
 250         fields[3].out_value = &nr_w_buf;
 251         fields[3].out_mask = NULL;
 252         fields[3].in_value = NULL;
 253         fields[3].in_check_value = NULL;
 254         fields[3].in_check_mask = NULL;
 255         fields[3].in_handler = NULL;
 256         fields[3].in_handler_priv = NULL;
 257
 258         jtag_add_dr_scan(4, fields, -1, NULL);
 259
 260         do
 261         {
 262                 /* rescan with NOP, to wait for the access to complete */
 263                 access = 0;
 264                 nr_w_buf = 0;
 265                 jtag_add_dr_scan(4, fields, -1, NULL);
 266                 jtag_execute_queue();
 267         } while (buf_get_u32(&access, 0, 1) != 1);
 268
 269 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 270         DEBUG("addr: 0x%x value: %8.8x", address, value);
 271 #endif
 272
 273         arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 274
 275         return ERROR_OK;
 276 }
 277
 278 int arm926ejs_examine_debug_reason(target_t *target)
 279 {
 280         armv4_5_common_t *armv4_5 = target->arch_info;
 281         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 282         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 283         int debug_reason;
 284         int retval;
 285
 286         embeddedice_read_reg(dbg_stat);
 287         if ((retval = jtag_execute_queue()) != ERROR_OK)
 288                 return retval;
 289
 290         debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
 291
 292         switch (debug_reason)
 293         {
 294                 case 1:
 295                         DEBUG("breakpoint from EICE unit 0");
 296                         target->debug_reason = DBG_REASON_BREAKPOINT;
 297                         break;
 298                 case 2:
 299                         DEBUG("breakpoint from EICE unit 1");
 300                         target->debug_reason = DBG_REASON_BREAKPOINT;
 301                         break;
 302                 case 3:
 303                         DEBUG("soft breakpoint (BKPT instruction)");
 304                         target->debug_reason = DBG_REASON_BREAKPOINT;
 305                         break;
 306                 case 4:
 307                         DEBUG("vector catch breakpoint");
 308                         target->debug_reason = DBG_REASON_BREAKPOINT;
 309                         break;
 310                 case 5:
 311                         DEBUG("external breakpoint");
 312                         target->debug_reason = DBG_REASON_BREAKPOINT;
 313                         break;
 314                 case 6:
 315                         DEBUG("watchpoint from EICE unit 0");
 316                         target->debug_reason = DBG_REASON_WATCHPOINT;
 317                         break;
 318                 case 7:
 319                         DEBUG("watchpoint from EICE unit 1");
 320                         target->debug_reason = DBG_REASON_WATCHPOINT;
 321                         break;
 322                 case 8:
 323                         DEBUG("external watchpoint");
 324                         target->debug_reason = DBG_REASON_WATCHPOINT;
 325                         break;
 326                 case 9:
 327                         DEBUG("internal debug request");
 328                         target->debug_reason = DBG_REASON_DBGRQ;
 329                         break;
 330                 case 10:
 331                         DEBUG("external debug request");
 332                         target->debug_reason = DBG_REASON_DBGRQ;
 333                         break;
 334                 case 11:
 335                         ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
 336                         break;
 337                 default:
 338                         ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
 339                         target->debug_reason = DBG_REASON_DBGRQ;
 340         }
 341
 342         return ERROR_OK;
 343 }
 344
 345 u32 arm926ejs_get_ttb(target_t *target)
 346 {
 347         armv4_5_common_t *armv4_5 = target->arch_info;
 348         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 349         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 350         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 351         int retval;
 352         u32 ttb = 0x0;
 353
 354         if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
 355                 return retval;
 356
 357         return ttb;
 358 }
 359
 360 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 361 {
 362         armv4_5_common_t *armv4_5 = target->arch_info;
 363         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 364         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 365         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 366         u32 cp15_control;
 367
 368         /* read cp15 control register */
 369         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 370         jtag_execute_queue();
 371
 372         if (mmu)
 373         {
 374                 /* invalidate TLB */
 375                 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
 376
 377                 cp15_control &= ~0x1U;
 378         }
 379
 380         if (d_u_cache)
 381         {
 382                 u32 debug_override;
 383                 /* read-modify-write CP15 debug override register
 384                  * to enable "test and clean all" */
 385                 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
 386                 debug_override |= 0x80000;
 387                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 388
 389                 /* clean and invalidate DCache */
 390                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 391
 392                 /* write CP15 debug override register
 393                  * to disable "test and clean all" */
 394                 debug_override &= ~0x80000;
 395                 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
 396
 397                 cp15_control &= ~0x4U;
 398         }
 399
 400         if (i_cache)
 401         {
 402                 /* invalidate ICache */
 403                 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
 404
 405                 cp15_control &= ~0x1000U;
 406         }
 407
 408         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 409 }
 410
 411 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 412 {
 413         armv4_5_common_t *armv4_5 = target->arch_info;
 414         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 415         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 416         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 417         u32 cp15_control;
 418
 419         /* read cp15 control register */
 420         arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
 421         jtag_execute_queue();
 422
 423         if (mmu)
 424                 cp15_control |= 0x1U;
 425
 426         if (d_u_cache)
 427                 cp15_control |= 0x4U;
 428
 429         if (i_cache)
 430                 cp15_control |= 0x1000U;
 431
 432         arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
 433 }
 434
 435 void arm926ejs_post_debug_entry(target_t *target)
 436 {
 437         armv4_5_common_t *armv4_5 = target->arch_info;
 438         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 439         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 440         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 441
 442         /* examine cp15 control reg */
 443         arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 444         jtag_execute_queue();
 445         DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
 446
 447         if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 448         {
 449                 u32 cache_type_reg;
 450                 /* identify caches */
 451                 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
 452                 jtag_execute_queue();
 453                 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 454         }
 455
 456         arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
 457         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 458         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 459
 460         /* save i/d fault status and address register */
 461         arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
 462         arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 463         arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 464
 465         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
 466                 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 467
 468
 469         u32 cache_dbg_ctrl;
 470
 471         /* read-modify-write CP15 cache debug control register
 472          * to disable I/D-cache linefills and force WT */
 473         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 474         cache_dbg_ctrl |= 0x7;
 475         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 476 }
 477
 478 void arm926ejs_pre_restore_context(target_t *target)
 479 {
 480         armv4_5_common_t *armv4_5 = target->arch_info;
 481         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 482         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 483         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 484
 485         /* restore i/d fault status and address register */
 486         arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
 487         arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
 488         arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
 489
 490         u32 cache_dbg_ctrl;
 491
 492         /* read-modify-write CP15 cache debug control register
 493          * to reenable I/D-cache linefills and disable WT */
 494         arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
 495         cache_dbg_ctrl &= ~0x7;
 496         arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
 497 }
 498
 499 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
 500 {
 501         armv4_5_common_t *armv4_5 = target->arch_info;
 502         arm7_9_common_t *arm7_9;
 503         arm9tdmi_common_t *arm9tdmi;
 504         arm926ejs_common_t *arm926ejs;
 505
 506         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 507         {
 508                 return -1;
 509         }
 510
 511         arm7_9 = armv4_5->arch_info;
 512         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 513         {
 514                 return -1;
 515         }
 516
 517         arm9tdmi = arm7_9->arch_info;
 518         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 519         {
 520                 return -1;
 521         }
 522
 523         arm926ejs = arm9tdmi->arch_info;
 524         if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
 525         {
 526                 return -1;
 527         }
 528
 529         *armv4_5_p = armv4_5;
 530         *arm7_9_p = arm7_9;
 531         *arm9tdmi_p = arm9tdmi;
 532         *arm926ejs_p = arm926ejs;
 533
 534         return ERROR_OK;
 535 }
 536
 537 int arm926ejs_arch_state(struct target_s *target)
 538 {
 539         armv4_5_common_t *armv4_5 = target->arch_info;
 540         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 541         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 542         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 543
 544         char *state[] =
 545         {
 546                 "disabled", "enabled"
 547         };
 548
 549         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 550         {
 551                 ERROR("BUG: called for a non-ARMv4/5 target");
 552                 exit(-1);
 553         }
 554
 555         USER(
 556                         "target halted in %s state due to %s, current mode: %s\n"
 557                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 558                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 559                          armv4_5_state_strings[armv4_5->core_state],
 560                          target_debug_reason_strings[target->debug_reason],
 561                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 562                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 563                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 564                          state[arm926ejs->armv4_5_mmu.mmu_enabled],
 565                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 566                          state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 567
 568         return ERROR_OK;
 569 }
 570
 571 int arm926ejs_soft_reset_halt(struct target_s *target)
 572 {
 573         armv4_5_common_t *armv4_5 = target->arch_info;
 574         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 575         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 576         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 577         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 578
 579         if (target->state == TARGET_RUNNING)
 580         {
 581                 target->type->halt(target);
 582         }
 583
 584         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 585         {
 586                 embeddedice_read_reg(dbg_stat);
 587                 jtag_execute_queue();
 588         }
 589
 590         target->state = TARGET_HALTED;
 591
 592         /* SVC, ARM state, IRQ and FIQ disabled */
 593         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 594         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 595         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 596
 597         /* start fetching from 0x0 */
 598         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 599         armv4_5->core_cache->reg_list[15].dirty = 1;
 600         armv4_5->core_cache->reg_list[15].valid = 1;
 601
 602         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 603         armv4_5->core_state = ARMV4_5_STATE_ARM;
 604
 605         arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 606         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 607         arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 608         arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 609
 610         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 611
 612         return ERROR_OK;
 613 }
 614
 615 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 616 {
 617         int retval;
 618         armv4_5_common_t *armv4_5 = target->arch_info;
 619         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 620         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 621         arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
 622
 623         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 624                 return retval;
 625
 626         /* If ICache is enabled, we have to invalidate affected ICache lines
 627          * the DCache is forced to write-through, so we don't have to clean it here
 628          */
 629         if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 630         {
 631                 if (count <= 1)
 632                 {
 633                         /* invalidate ICache single entry with MVA */
 634                         arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
 635                 }
 636                 else
 637                 {
 638                         /* invalidate ICache */
 639                         arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
 640                 }
 641         }
 642
 643         return retval;
 644 }
 645
 646 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 647 {
 648         arm9tdmi_init_target(cmd_ctx, target);
 649
 650         return ERROR_OK;
 651
 652 }
 653
 654 int arm926ejs_quit()
 655 {
 656
 657         return ERROR_OK;
 658 }
 659
 660 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
 661 {
 662         arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
 663         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 664
 665         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 666          */
 667         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 668
 669         arm9tdmi->arch_info = arm926ejs;
 670         arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
 671
 672         arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
 673         arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
 674
 675         arm926ejs->read_cp15 = arm926ejs_cp15_read;
 676         arm926ejs->write_cp15 = arm926ejs_cp15_write;
 677         arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
 678         arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
 679         arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
 680         arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
 681         arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 682         arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 683         arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
 684         arm926ejs->armv4_5_mmu.mmu_enabled = 0;
 685
 686         arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 687
 688         /* The ARM926EJ-S implements the ARMv5TE architecture which
 689          * has the BKPT instruction, so we don't have to use a watchpoint comparator
 690          */
 691         arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
 692         arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
 693
 694         arm7_9->sw_bkpts_use_wp = 0;
 695         arm7_9->sw_bkpts_enabled = 1;
 696
 697         return ERROR_OK;
 698 }
 699
 700 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 701 {
 702         int chain_pos;
 703         char *variant = NULL;
 704         arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
 705
 706         if (argc < 4)
 707         {
 708                 ERROR("'target arm926ejs' requires at least one additional argument");
 709                 exit(-1);
 710         }
 711
 712         chain_pos = strtoul(args[3], NULL, 0);
 713
 714         if (argc >= 5)
 715                 variant = args[4];
 716
 717         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 718
 719         arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
 720
 721         return ERROR_OK;
 722 }
 723
 724 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
 725 {
 726         int retval;
 727         command_t *arm926ejs_cmd;
 728
 729
 730         retval = arm9tdmi_register_commands(cmd_ctx);
 731
 732         arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
 733
 734         register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 735
 736         register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 737         register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 738
 739         register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 740         register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 741         register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 742
 743         register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 744         register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 745         register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 746
 747         return ERROR_OK;
 748 }
 749
 750 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 751 {
 752         int retval;
 753         target_t *target = get_current_target(cmd_ctx);
 754         armv4_5_common_t *armv4_5;
 755         arm7_9_common_t *arm7_9;
 756         arm9tdmi_common_t *arm9tdmi;
 757         arm926ejs_common_t *arm926ejs;
 758         int opcode_1;
 759         int opcode_2;
 760         int CRn;
 761         int CRm;
 762
 763         if ((argc < 4) || (argc > 5))
 764         {
 765                 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
 766                 return ERROR_OK;
 767         }
 768
 769         opcode_1 = strtoul(args[0], NULL, 0);
 770         opcode_2 = strtoul(args[1], NULL, 0);
 771         CRn = strtoul(args[2], NULL, 0);
 772         CRm = strtoul(args[3], NULL, 0);
 773
 774         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 775         {
 776                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 777                 return ERROR_OK;
 778         }
 779
 780         if (target->state != TARGET_HALTED)
 781         {
 782                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 783                 return ERROR_OK;
 784         }
 785
 786         if (argc == 4)
 787         {
 788                 u32 value;
 789                 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
 790                 {
 791                         command_print(cmd_ctx, "couldn't access register");
 792                         return ERROR_OK;
 793                 }
 794                 jtag_execute_queue();
 795
 796                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 797         }
 798         else
 799         {
 800                 u32 value = strtoul(args[4], NULL, 0);
 801                 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
 802                 {
 803                         command_print(cmd_ctx, "couldn't access register");
 804                         return ERROR_OK;
 805                 }
 806                 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
 807         }
 808
 809         return ERROR_OK;
 810 }
 811
 812 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 813 {
 814         target_t *target = get_current_target(cmd_ctx);
 815         armv4_5_common_t *armv4_5;
 816         arm7_9_common_t *arm7_9;
 817         arm9tdmi_common_t *arm9tdmi;
 818         arm926ejs_common_t *arm926ejs;
 819
 820         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 821         {
 822                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 823                 return ERROR_OK;
 824         }
 825
 826         return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 827 }
 828
 829 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 830 {
 831         target_t *target = get_current_target(cmd_ctx);
 832         armv4_5_common_t *armv4_5;
 833         arm7_9_common_t *arm7_9;
 834         arm9tdmi_common_t *arm9tdmi;
 835         arm926ejs_common_t *arm926ejs;
 836         arm_jtag_t *jtag_info;
 837
 838         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 839         {
 840                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 841                 return ERROR_OK;
 842         }
 843
 844         jtag_info = &arm7_9->jtag_info;
 845
 846         if (target->state != TARGET_HALTED)
 847         {
 848                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 849                 return ERROR_OK;
 850         }
 851
 852         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 853 }
 854
 855 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 856 {
 857         target_t *target = get_current_target(cmd_ctx);
 858         armv4_5_common_t *armv4_5;
 859         arm7_9_common_t *arm7_9;
 860         arm9tdmi_common_t *arm9tdmi;
 861         arm926ejs_common_t *arm926ejs;
 862         arm_jtag_t *jtag_info;
 863
 864         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 865         {
 866                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 867                 return ERROR_OK;
 868         }
 869
 870         jtag_info = &arm7_9->jtag_info;
 871
 872         if (target->state != TARGET_HALTED)
 873         {
 874                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 875                 return ERROR_OK;
 876         }
 877
 878         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 879 }
 880
 881 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
 882 {
 883         target_t *target = get_current_target(cmd_ctx);
 884         armv4_5_common_t *armv4_5;
 885         arm7_9_common_t *arm7_9;
 886         arm9tdmi_common_t *arm9tdmi;
 887         arm926ejs_common_t *arm926ejs;
 888         arm_jtag_t *jtag_info;
 889
 890         if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
 891         {
 892                 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
 893                 return ERROR_OK;
 894         }
 895
 896         jtag_info = &arm7_9->jtag_info;
 897
 898         if (target->state != TARGET_HALTED)
 899         {
 900                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
 901                 return ERROR_OK;
 902         }
 903
 904         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
 905 }
 906 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
 907 {
 908         int retval;
 909         int type;
 910         u32 cb;
 911         int domain;
 912         u32 ap;
 913
 914         armv4_5_common_t *armv4_5;
 915         arm7_9_common_t *arm7_9;
 916         arm9tdmi_common_t *arm9tdmi;
 917         arm926ejs_common_t *arm926ejs;
 918         retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
 919         if (retval != ERROR_OK)
 920         {
 921                 return retval;
 922         }
 923         u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
 924         if (type == -1)
 925         {
 926                 return ret;
 927         }
 928         *physical = ret;
 929         return ERROR_OK;
 930 }
 931
 932 static int arm926ejs_mmu(struct target_s *target, int *enabled)
 933 {
 934         armv4_5_common_t *armv4_5 = target->arch_info;
 935         arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
 936
 937         if (target->state != TARGET_HALTED)
 938         {
 939                 ERROR("Target not halted");
 940                 return ERROR_TARGET_INVALID;
 941         }
 942         *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;
 943         return ERROR_OK;
 944 }