1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm926ejs.h"
32 #define _DEBUG_INSTRUCTION_EXECUTION_
36 int arm926ejs_register_commands(struct command_context_s *cmd_ctx);
38 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
42 int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 /* forward declarations */
49 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
50 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
51 int arm926ejs_quit(void);
52 int arm926ejs_arch_state(struct target_s *target);
53 int arm926ejs_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
54 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
55 int arm926ejs_soft_reset_halt(struct target_s *target);
56 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical);
57 static int arm926ejs_mmu(struct target_s *target, int *enabled);
59 target_type_t arm926ejs_target =
64 .arch_state = arm926ejs_arch_state,
66 .target_request_data = arm7_9_target_request_data,
69 .resume = arm7_9_resume,
72 .assert_reset = arm7_9_assert_reset,
73 .deassert_reset = arm7_9_deassert_reset,
74 .soft_reset_halt = arm926ejs_soft_reset_halt,
76 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
78 .read_memory = arm7_9_read_memory,
79 .write_memory = arm926ejs_write_memory,
80 .bulk_write_memory = arm7_9_bulk_write_memory,
81 .checksum_memory = arm7_9_checksum_memory,
82 .blank_check_memory = arm7_9_blank_check_memory,
84 .run_algorithm = armv4_5_run_algorithm,
86 .add_breakpoint = arm7_9_add_breakpoint,
87 .remove_breakpoint = arm7_9_remove_breakpoint,
88 .add_watchpoint = arm7_9_add_watchpoint,
89 .remove_watchpoint = arm7_9_remove_watchpoint,
91 .register_commands = arm926ejs_register_commands,
92 .target_command = arm926ejs_target_command,
93 .init_target = arm926ejs_init_target,
94 .examine = arm9tdmi_examine,
95 .quit = arm926ejs_quit,
96 .virt2phys = arm926ejs_virt2phys,
101 int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
103 /* The ARM926EJ-S' instruction register is 4 bits wide */
104 u8 t = *captured & 0xf;
105 u8 t2 = *field->in_check_value & 0xf;
110 else if ((t == 0x0f) || (t == 0x00))
112 LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
115 return ERROR_JTAG_QUEUE_FAILED;;
118 #define ARM926EJS_CP15_ADDR(opcode_1, opcode_2, CRn, CRm) ((opcode_1 << 11) | (opcode_2 << 8) | (CRn << 4) | (CRm << 0))
120 int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 *value)
122 armv4_5_common_t *armv4_5 = target->arch_info;
123 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
124 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
125 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
126 scan_field_t fields[4];
131 buf_set_u32(address_buf, 0, 14, address);
133 jtag_add_end_state(TAP_RTI);
134 arm_jtag_scann(jtag_info, 0xf);
135 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
137 fields[0].device = jtag_info->chain_pos;
138 fields[0].num_bits = 32;
139 fields[0].out_value = NULL;
140 fields[0].out_mask = NULL;
141 fields[0].in_value = NULL;
142 fields[0].in_check_value = NULL;
143 fields[0].in_check_mask = NULL;
144 fields[0].in_handler = NULL;
145 fields[0].in_handler_priv = NULL;
147 fields[1].device = jtag_info->chain_pos;
148 fields[1].num_bits = 1;
149 fields[1].out_value = &access;
150 fields[1].out_mask = NULL;
151 fields[1].in_value = &access;
152 fields[1].in_check_value = NULL;
153 fields[1].in_check_mask = NULL;
154 fields[1].in_handler = NULL;
155 fields[1].in_handler_priv = NULL;
157 fields[2].device = jtag_info->chain_pos;
158 fields[2].num_bits = 14;
159 fields[2].out_value = address_buf;
160 fields[2].out_mask = NULL;
161 fields[2].in_value = NULL;
162 fields[2].in_check_value = NULL;
163 fields[2].in_check_mask = NULL;
164 fields[2].in_handler = NULL;
165 fields[2].in_handler_priv = NULL;
167 fields[3].device = jtag_info->chain_pos;
168 fields[3].num_bits = 1;
169 fields[3].out_value = &nr_w_buf;
170 fields[3].out_mask = NULL;
171 fields[3].in_value = NULL;
172 fields[3].in_check_value = NULL;
173 fields[3].in_check_mask = NULL;
174 fields[3].in_handler = NULL;
175 fields[3].in_handler_priv = NULL;
177 jtag_add_dr_scan(4, fields, -1);
179 fields[0].in_handler_priv = value;
180 fields[0].in_handler = arm_jtag_buf_to_u32;
182 /*TODO: add timeout*/
185 /* rescan with NOP, to wait for the access to complete */
188 jtag_add_dr_scan(4, fields, -1);
189 jtag_execute_queue();
190 } while (buf_get_u32(&access, 0, 1) != 1);
192 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
193 LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
196 arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
201 int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u32 value)
203 armv4_5_common_t *armv4_5 = target->arch_info;
204 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
205 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
206 u32 address = ARM926EJS_CP15_ADDR(op1, op2, CRn, CRm);
207 scan_field_t fields[4];
213 buf_set_u32(address_buf, 0, 14, address);
214 buf_set_u32(value_buf, 0, 32, value);
216 jtag_add_end_state(TAP_RTI);
217 arm_jtag_scann(jtag_info, 0xf);
218 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
220 fields[0].device = jtag_info->chain_pos;
221 fields[0].num_bits = 32;
222 fields[0].out_value = value_buf;
223 fields[0].out_mask = NULL;
224 fields[0].in_value = NULL;
225 fields[0].in_check_value = NULL;
226 fields[0].in_check_mask = NULL;
227 fields[0].in_handler = NULL;
228 fields[0].in_handler_priv = NULL;
230 fields[1].device = jtag_info->chain_pos;
231 fields[1].num_bits = 1;
232 fields[1].out_value = &access;
233 fields[1].out_mask = NULL;
234 fields[1].in_value = &access;
235 fields[1].in_check_value = NULL;
236 fields[1].in_check_mask = NULL;
237 fields[1].in_handler = NULL;
238 fields[1].in_handler_priv = NULL;
240 fields[2].device = jtag_info->chain_pos;
241 fields[2].num_bits = 14;
242 fields[2].out_value = address_buf;
243 fields[2].out_mask = NULL;
244 fields[2].in_value = NULL;
245 fields[2].in_check_value = NULL;
246 fields[2].in_check_mask = NULL;
247 fields[2].in_handler = NULL;
248 fields[2].in_handler_priv = NULL;
250 fields[3].device = jtag_info->chain_pos;
251 fields[3].num_bits = 1;
252 fields[3].out_value = &nr_w_buf;
253 fields[3].out_mask = NULL;
254 fields[3].in_value = NULL;
255 fields[3].in_check_value = NULL;
256 fields[3].in_check_mask = NULL;
257 fields[3].in_handler = NULL;
258 fields[3].in_handler_priv = NULL;
260 jtag_add_dr_scan(4, fields, -1);
261 /*TODO: add timeout*/
264 /* rescan with NOP, to wait for the access to complete */
267 jtag_add_dr_scan(4, fields, -1);
268 jtag_execute_queue();
269 } while (buf_get_u32(&access, 0, 1) != 1);
271 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
272 LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
275 arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
280 int arm926ejs_examine_debug_reason(target_t *target)
282 armv4_5_common_t *armv4_5 = target->arch_info;
283 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
284 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
288 embeddedice_read_reg(dbg_stat);
289 if ((retval = jtag_execute_queue()) != ERROR_OK)
292 debug_reason = buf_get_u32(dbg_stat->value, 6, 4);
294 switch (debug_reason)
297 LOG_DEBUG("breakpoint from EICE unit 0");
298 target->debug_reason = DBG_REASON_BREAKPOINT;
301 LOG_DEBUG("breakpoint from EICE unit 1");
302 target->debug_reason = DBG_REASON_BREAKPOINT;
305 LOG_DEBUG("soft breakpoint (BKPT instruction)");
306 target->debug_reason = DBG_REASON_BREAKPOINT;
309 LOG_DEBUG("vector catch breakpoint");
310 target->debug_reason = DBG_REASON_BREAKPOINT;
313 LOG_DEBUG("external breakpoint");
314 target->debug_reason = DBG_REASON_BREAKPOINT;
317 LOG_DEBUG("watchpoint from EICE unit 0");
318 target->debug_reason = DBG_REASON_WATCHPOINT;
321 LOG_DEBUG("watchpoint from EICE unit 1");
322 target->debug_reason = DBG_REASON_WATCHPOINT;
325 LOG_DEBUG("external watchpoint");
326 target->debug_reason = DBG_REASON_WATCHPOINT;
329 LOG_DEBUG("internal debug request");
330 target->debug_reason = DBG_REASON_DBGRQ;
333 LOG_DEBUG("external debug request");
334 target->debug_reason = DBG_REASON_DBGRQ;
337 LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
340 LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
341 target->debug_reason = DBG_REASON_DBGRQ;
342 retval = ERROR_TARGET_FAILURE;
349 u32 arm926ejs_get_ttb(target_t *target)
351 armv4_5_common_t *armv4_5 = target->arch_info;
352 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
353 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
354 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
358 if ((retval = arm926ejs->read_cp15(target, 0, 0, 2, 0, &ttb)) != ERROR_OK)
364 void arm926ejs_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
366 armv4_5_common_t *armv4_5 = target->arch_info;
367 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
368 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
369 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
372 /* read cp15 control register */
373 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
374 jtag_execute_queue();
379 arm926ejs->write_cp15(target, 0, 0, 8, 7, 0x0);
381 cp15_control &= ~0x1U;
387 /* read-modify-write CP15 debug override register
388 * to enable "test and clean all" */
389 arm926ejs->read_cp15(target, 0, 0, 15, 0, &debug_override);
390 debug_override |= 0x80000;
391 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
393 /* clean and invalidate DCache */
394 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
396 /* write CP15 debug override register
397 * to disable "test and clean all" */
398 debug_override &= ~0x80000;
399 arm926ejs->write_cp15(target, 0, 0, 15, 0, debug_override);
401 cp15_control &= ~0x4U;
406 /* invalidate ICache */
407 arm926ejs->write_cp15(target, 0, 0, 7, 5, 0x0);
409 cp15_control &= ~0x1000U;
412 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
415 void arm926ejs_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
417 armv4_5_common_t *armv4_5 = target->arch_info;
418 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
419 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
420 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
423 /* read cp15 control register */
424 arm926ejs->read_cp15(target, 0, 0, 1, 0, &cp15_control);
425 jtag_execute_queue();
428 cp15_control |= 0x1U;
431 cp15_control |= 0x4U;
434 cp15_control |= 0x1000U;
436 arm926ejs->write_cp15(target, 0, 0, 1, 0, cp15_control);
439 void arm926ejs_post_debug_entry(target_t *target)
441 armv4_5_common_t *armv4_5 = target->arch_info;
442 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
443 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
444 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
446 /* examine cp15 control reg */
447 arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
448 jtag_execute_queue();
449 LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
451 if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
454 /* identify caches */
455 arm926ejs->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
456 jtag_execute_queue();
457 armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
460 arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
461 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
462 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
464 /* save i/d fault status and address register */
465 arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
466 arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
467 arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
469 LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
470 arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
475 /* read-modify-write CP15 cache debug control register
476 * to disable I/D-cache linefills and force WT */
477 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
478 cache_dbg_ctrl |= 0x7;
479 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
482 void arm926ejs_pre_restore_context(target_t *target)
484 armv4_5_common_t *armv4_5 = target->arch_info;
485 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
486 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
487 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
489 /* restore i/d fault status and address register */
490 arm926ejs->write_cp15(target, 0, 0, 5, 0, arm926ejs->d_fsr);
491 arm926ejs->write_cp15(target, 0, 1, 5, 0, arm926ejs->i_fsr);
492 arm926ejs->write_cp15(target, 0, 0, 6, 0, arm926ejs->d_far);
496 /* read-modify-write CP15 cache debug control register
497 * to reenable I/D-cache linefills and disable WT */
498 arm926ejs->read_cp15(target, 7, 0, 15, 0, &cache_dbg_ctrl);
499 cache_dbg_ctrl &= ~0x7;
500 arm926ejs->write_cp15(target, 7, 0, 15, 0, cache_dbg_ctrl);
503 int arm926ejs_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm926ejs_common_t **arm926ejs_p)
505 armv4_5_common_t *armv4_5 = target->arch_info;
506 arm7_9_common_t *arm7_9;
507 arm9tdmi_common_t *arm9tdmi;
508 arm926ejs_common_t *arm926ejs;
510 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
515 arm7_9 = armv4_5->arch_info;
516 if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
521 arm9tdmi = arm7_9->arch_info;
522 if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
527 arm926ejs = arm9tdmi->arch_info;
528 if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC)
533 *armv4_5_p = armv4_5;
535 *arm9tdmi_p = arm9tdmi;
536 *arm926ejs_p = arm926ejs;
541 int arm926ejs_arch_state(struct target_s *target)
543 armv4_5_common_t *armv4_5 = target->arch_info;
544 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
545 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
546 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
550 "disabled", "enabled"
553 if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
555 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
560 "target halted in %s state due to %s, current mode: %s\n"
561 "cpsr: 0x%8.8x pc: 0x%8.8x\n"
562 "MMU: %s, D-Cache: %s, I-Cache: %s",
563 armv4_5_state_strings[armv4_5->core_state],
564 target_debug_reason_strings[target->debug_reason],
565 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
566 buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
567 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
568 state[arm926ejs->armv4_5_mmu.mmu_enabled],
569 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
570 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
575 int arm926ejs_soft_reset_halt(struct target_s *target)
577 armv4_5_common_t *armv4_5 = target->arch_info;
578 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
579 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
580 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
581 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
588 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
590 embeddedice_read_reg(dbg_stat);
591 jtag_execute_queue();
596 /* do not eat all CPU, time out after 1 se*/
601 LOG_ERROR("Failed to halt CPU after 1 sec");
602 return ERROR_TARGET_TIMEOUT;
605 target->state = TARGET_HALTED;
607 /* SVC, ARM state, IRQ and FIQ disabled */
608 buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
609 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
610 armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
612 /* start fetching from 0x0 */
613 buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
614 armv4_5->core_cache->reg_list[15].dirty = 1;
615 armv4_5->core_cache->reg_list[15].valid = 1;
617 armv4_5->core_mode = ARMV4_5_MODE_SVC;
618 armv4_5->core_state = ARMV4_5_STATE_ARM;
620 arm926ejs_disable_mmu_caches(target, 1, 1, 1);
621 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
622 arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
623 arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
625 target_call_event_callbacks(target, TARGET_EVENT_HALTED);
630 int arm926ejs_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
633 armv4_5_common_t *armv4_5 = target->arch_info;
634 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
635 arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
636 arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
638 if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
641 /* If ICache is enabled, we have to invalidate affected ICache lines
642 * the DCache is forced to write-through, so we don't have to clean it here
644 if (arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
648 /* invalidate ICache single entry with MVA */
649 arm926ejs->write_cp15(target, 0, 1, 7, 5, address);
653 /* invalidate ICache */
654 arm926ejs->write_cp15(target, 0, 0, 7, 5, address);
661 int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
663 arm9tdmi_init_target(cmd_ctx, target);
669 int arm926ejs_quit(void)
675 int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, int chain_pos, char *variant)
677 arm9tdmi_common_t *arm9tdmi = &arm926ejs->arm9tdmi_common;
678 arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
680 /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
682 arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
684 arm9tdmi->arch_info = arm926ejs;
685 arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC;
687 arm7_9->post_debug_entry = arm926ejs_post_debug_entry;
688 arm7_9->pre_restore_context = arm926ejs_pre_restore_context;
690 arm926ejs->read_cp15 = arm926ejs_cp15_read;
691 arm926ejs->write_cp15 = arm926ejs_cp15_write;
692 arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1;
693 arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb;
694 arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory;
695 arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory;
696 arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
697 arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
698 arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
699 arm926ejs->armv4_5_mmu.mmu_enabled = 0;
701 arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
703 /* The ARM926EJ-S implements the ARMv5TE architecture which
704 * has the BKPT instruction, so we don't have to use a watchpoint comparator
706 arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
707 arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
712 int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
715 char *variant = NULL;
716 arm926ejs_common_t *arm926ejs = malloc(sizeof(arm926ejs_common_t));
717 memset(arm926ejs, 0, sizeof(*arm926ejs));
721 LOG_ERROR("'target arm926ejs' requires at least one additional argument");
725 chain_pos = strtoul(args[3], NULL, 0);
730 LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
732 arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
737 int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
740 command_t *arm926ejs_cmd;
743 retval = arm9tdmi_register_commands(cmd_ctx);
745 arm926ejs_cmd = register_command(cmd_ctx, NULL, "arm926ejs", NULL, COMMAND_ANY, "arm926ejs specific commands");
747 register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
749 register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
750 register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
752 register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
753 register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
754 register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
756 register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
757 register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
758 register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
763 int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
766 target_t *target = get_current_target(cmd_ctx);
767 armv4_5_common_t *armv4_5;
768 arm7_9_common_t *arm7_9;
769 arm9tdmi_common_t *arm9tdmi;
770 arm926ejs_common_t *arm926ejs;
776 if ((argc < 4) || (argc > 5))
778 command_print(cmd_ctx, "usage: arm926ejs cp15 <opcode_1> <opcode_2> <CRn> <CRm> [value]");
782 opcode_1 = strtoul(args[0], NULL, 0);
783 opcode_2 = strtoul(args[1], NULL, 0);
784 CRn = strtoul(args[2], NULL, 0);
785 CRm = strtoul(args[3], NULL, 0);
787 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
789 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
793 if (target->state != TARGET_HALTED)
795 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
802 if ((retval = arm926ejs->read_cp15(target, opcode_1, opcode_2, CRn, CRm, &value)) != ERROR_OK)
804 command_print(cmd_ctx, "couldn't access register");
807 jtag_execute_queue();
809 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
813 u32 value = strtoul(args[4], NULL, 0);
814 if ((retval = arm926ejs->write_cp15(target, opcode_1, opcode_2, CRn, CRm, value)) != ERROR_OK)
816 command_print(cmd_ctx, "couldn't access register");
819 command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
825 int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
827 target_t *target = get_current_target(cmd_ctx);
828 armv4_5_common_t *armv4_5;
829 arm7_9_common_t *arm7_9;
830 arm9tdmi_common_t *arm9tdmi;
831 arm926ejs_common_t *arm926ejs;
833 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
835 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
839 return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
842 int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
844 target_t *target = get_current_target(cmd_ctx);
845 armv4_5_common_t *armv4_5;
846 arm7_9_common_t *arm7_9;
847 arm9tdmi_common_t *arm9tdmi;
848 arm926ejs_common_t *arm926ejs;
849 arm_jtag_t *jtag_info;
851 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
853 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
857 jtag_info = &arm7_9->jtag_info;
859 if (target->state != TARGET_HALTED)
861 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
865 return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
868 int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
870 target_t *target = get_current_target(cmd_ctx);
871 armv4_5_common_t *armv4_5;
872 arm7_9_common_t *arm7_9;
873 arm9tdmi_common_t *arm9tdmi;
874 arm926ejs_common_t *arm926ejs;
875 arm_jtag_t *jtag_info;
877 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
879 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
883 jtag_info = &arm7_9->jtag_info;
885 if (target->state != TARGET_HALTED)
887 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
891 return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
894 int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
896 target_t *target = get_current_target(cmd_ctx);
897 armv4_5_common_t *armv4_5;
898 arm7_9_common_t *arm7_9;
899 arm9tdmi_common_t *arm9tdmi;
900 arm926ejs_common_t *arm926ejs;
901 arm_jtag_t *jtag_info;
903 if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
905 command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
909 jtag_info = &arm7_9->jtag_info;
911 if (target->state != TARGET_HALTED)
913 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
917 return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
919 static int arm926ejs_virt2phys(struct target_s *target, u32 virtual, u32 *physical)
927 armv4_5_common_t *armv4_5;
928 arm7_9_common_t *arm7_9;
929 arm9tdmi_common_t *arm9tdmi;
930 arm926ejs_common_t *arm926ejs;
931 retval= arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs);
932 if (retval != ERROR_OK)
936 u32 ret = armv4_5_mmu_translate_va(target, &arm926ejs->armv4_5_mmu, virtual, &type, &cb, &domain, &ap);
945 static int arm926ejs_mmu(struct target_s *target, int *enabled)
947 armv4_5_common_t *armv4_5 = target->arch_info;
948 arm926ejs_common_t *arm926ejs = armv4_5->arch_info;
950 if (target->state != TARGET_HALTED)
952 LOG_ERROR("Target not halted");
953 return ERROR_TARGET_INVALID;
955 *enabled = arm926ejs->armv4_5_mmu.mmu_enabled;