1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_ARM920T_H
9 #define OPENOCD_TARGET_ARM920T_H
12 #include "armv4_5_mmu.h"
14 #define ARM920T_COMMON_MAGIC 0xa920a920
16 struct arm920t_common {
17 struct arm7_9_common arm7_9_common;
18 uint32_t common_magic;
19 struct armv4_5_mmu_common armv4_5_mmu;
20 uint32_t cp15_control_reg;
28 static inline struct arm920t_common *target_to_arm920(struct target *target)
30 return container_of(target->arch_info, struct arm920t_common, arm7_9_common.arm);
33 struct arm920t_cache_line {
38 struct arm920t_tlb_entry {
44 int arm920t_arch_state(struct target *target);
45 int arm920t_soft_reset_halt(struct target *target);
46 int arm920t_read_memory(struct target *target,
47 target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
48 int arm920t_write_memory(struct target *target,
49 target_addr_t address, uint32_t size, uint32_t count, const uint8_t *buffer);
50 int arm920t_post_debug_entry(struct target *target);
51 void arm920t_pre_restore_context(struct target *target);
52 int arm920t_get_ttb(struct target *target, uint32_t *result);
53 int arm920t_disable_mmu_caches(struct target *target,
54 int mmu, int d_u_cache, int i_cache);
55 int arm920t_enable_mmu_caches(struct target *target,
56 int mmu, int d_u_cache, int i_cache);
58 extern const struct command_registration arm920t_command_handlers[];
60 #endif /* OPENOCD_TARGET_ARM920T_H */