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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm920t.h"
  25 #include "jtag.h"
  26 #include "log.h"
  27
  28 #include <stdlib.h>
  29 #include <string.h>
  30
  31 #if 0
  32 #define _DEBUG_INSTRUCTION_EXECUTION_
  33 #endif
  34
  35 /* cli handling */
  36 int arm920t_register_commands(struct command_context_s *cmd_ctx);
  37
  38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  44
  45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  47
  48 /* forward declarations */
  49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
  50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
  51 int arm920t_quit(void);
  52 int arm920t_arch_state(struct target_s *target);
  53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
  55 int arm920t_soft_reset_halt(struct target_s *target);
  56
  57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
  58
  59 target_type_t arm920t_target =
  60 {
  61         .name = "arm920t",
  62
  63         .poll = arm7_9_poll,
  64         .arch_state = arm920t_arch_state,
  65
  66         .target_request_data = arm7_9_target_request_data,
  67
  68         .halt = arm7_9_halt,
  69         .resume = arm7_9_resume,
  70         .step = arm7_9_step,
  71
  72         .assert_reset = arm7_9_assert_reset,
  73         .deassert_reset = arm7_9_deassert_reset,
  74         .soft_reset_halt = arm920t_soft_reset_halt,
  75
  76         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  77
  78         .read_memory = arm920t_read_memory,
  79         .write_memory = arm920t_write_memory,
  80         .bulk_write_memory = arm7_9_bulk_write_memory,
  81         .checksum_memory = arm7_9_checksum_memory,
  82         .blank_check_memory = arm7_9_blank_check_memory,
  83
  84         .run_algorithm = armv4_5_run_algorithm,
  85
  86         .add_breakpoint = arm7_9_add_breakpoint,
  87         .remove_breakpoint = arm7_9_remove_breakpoint,
  88         .add_watchpoint = arm7_9_add_watchpoint,
  89         .remove_watchpoint = arm7_9_remove_watchpoint,
  90
  91         .register_commands = arm920t_register_commands,
  92         .target_command = arm920t_target_command,
  93         .init_target = arm920t_init_target,
  94         .examine = arm9tdmi_examine,
  95         .quit = arm920t_quit
  96 };
  97
  98 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
  99 {
 100         armv4_5_common_t *armv4_5 = target->arch_info;
 101         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 102         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 103         scan_field_t fields[4];
 104         u8 access_type_buf = 1;
 105         u8 reg_addr_buf = reg_addr & 0x3f;
 106         u8 nr_w_buf = 0;
 107
 108         jtag_add_end_state(TAP_RTI);
 109         arm_jtag_scann(jtag_info, 0xf);
 110         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 111
 112         fields[0].device = jtag_info->chain_pos;
 113         fields[0].num_bits = 1;
 114         fields[0].out_value = &access_type_buf;
 115         fields[0].out_mask = NULL;
 116         fields[0].in_value = NULL;
 117         fields[0].in_check_value = NULL;
 118         fields[0].in_check_mask = NULL;
 119         fields[0].in_handler = NULL;
 120         fields[0].in_handler_priv = NULL;
 121
 122         fields[1].device = jtag_info->chain_pos;
 123         fields[1].num_bits = 32;
 124         fields[1].out_value = NULL;
 125         fields[1].out_mask = NULL;
 126         fields[1].in_value = NULL;
 127         fields[1].in_check_value = NULL;
 128         fields[1].in_check_mask = NULL;
 129         fields[1].in_handler = NULL;
 130         fields[1].in_handler_priv = NULL;
 131
 132         fields[2].device = jtag_info->chain_pos;
 133         fields[2].num_bits = 6;
 134         fields[2].out_value = &reg_addr_buf;
 135         fields[2].out_mask = NULL;
 136         fields[2].in_value = NULL;
 137         fields[2].in_check_value = NULL;
 138         fields[2].in_check_mask = NULL;
 139         fields[2].in_handler = NULL;
 140         fields[2].in_handler_priv = NULL;
 141
 142         fields[3].device = jtag_info->chain_pos;
 143         fields[3].num_bits = 1;
 144         fields[3].out_value = &nr_w_buf;
 145         fields[3].out_mask = NULL;
 146         fields[3].in_value = NULL;
 147         fields[3].in_check_value = NULL;
 148         fields[3].in_check_mask = NULL;
 149         fields[3].in_handler = NULL;
 150         fields[3].in_handler_priv = NULL;
 151
 152         jtag_add_dr_scan(4, fields, -1);
 153
 154         fields[1].in_handler_priv = value;
 155         fields[1].in_handler = arm_jtag_buf_to_u32;
 156
 157         jtag_add_dr_scan(4, fields, -1);
 158
 159 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 160         jtag_execute_queue();
 161         LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 162 #endif
 163
 164         return ERROR_OK;
 165 }
 166
 167 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
 168 {
 169         armv4_5_common_t *armv4_5 = target->arch_info;
 170         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 171         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 172         scan_field_t fields[4];
 173         u8 access_type_buf = 1;
 174         u8 reg_addr_buf = reg_addr & 0x3f;
 175         u8 nr_w_buf = 1;
 176         u8 value_buf[4];
 177
 178         buf_set_u32(value_buf, 0, 32, value);
 179
 180         jtag_add_end_state(TAP_RTI);
 181         arm_jtag_scann(jtag_info, 0xf);
 182         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 183
 184         fields[0].device = jtag_info->chain_pos;
 185         fields[0].num_bits = 1;
 186         fields[0].out_value = &access_type_buf;
 187         fields[0].out_mask = NULL;
 188         fields[0].in_value = NULL;
 189         fields[0].in_check_value = NULL;
 190         fields[0].in_check_mask = NULL;
 191         fields[0].in_handler = NULL;
 192         fields[0].in_handler_priv = NULL;
 193
 194         fields[1].device = jtag_info->chain_pos;
 195         fields[1].num_bits = 32;
 196         fields[1].out_value = value_buf;
 197         fields[1].out_mask = NULL;
 198         fields[1].in_value = NULL;
 199         fields[1].in_check_value = NULL;
 200         fields[1].in_check_mask = NULL;
 201         fields[1].in_handler = NULL;
 202         fields[1].in_handler_priv = NULL;
 203
 204         fields[2].device = jtag_info->chain_pos;
 205         fields[2].num_bits = 6;
 206         fields[2].out_value = &reg_addr_buf;
 207         fields[2].out_mask = NULL;
 208         fields[2].in_value = NULL;
 209         fields[2].in_check_value = NULL;
 210         fields[2].in_check_mask = NULL;
 211         fields[2].in_handler = NULL;
 212         fields[2].in_handler_priv = NULL;
 213
 214         fields[3].device = jtag_info->chain_pos;
 215         fields[3].num_bits = 1;
 216         fields[3].out_value = &nr_w_buf;
 217         fields[3].out_mask = NULL;
 218         fields[3].in_value = NULL;
 219         fields[3].in_check_value = NULL;
 220         fields[3].in_check_mask = NULL;
 221         fields[3].in_handler = NULL;
 222         fields[3].in_handler_priv = NULL;
 223
 224         jtag_add_dr_scan(4, fields, -1);
 225
 226 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 227         LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
 228 #endif
 229
 230         return ERROR_OK;
 231 }
 232
 233 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
 234 {
 235         armv4_5_common_t *armv4_5 = target->arch_info;
 236         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 237         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 238         scan_field_t fields[4];
 239         u8 access_type_buf = 0;         /* interpreted access */
 240         u8 reg_addr_buf = 0x0;
 241         u8 nr_w_buf = 0;
 242         u8 cp15_opcode_buf[4];
 243
 244         jtag_add_end_state(TAP_RTI);
 245         arm_jtag_scann(jtag_info, 0xf);
 246         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 247
 248         buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 249
 250         fields[0].device = jtag_info->chain_pos;
 251         fields[0].num_bits = 1;
 252         fields[0].out_value = &access_type_buf;
 253         fields[0].out_mask = NULL;
 254         fields[0].in_value = NULL;
 255         fields[0].in_check_value = NULL;
 256         fields[0].in_check_mask = NULL;
 257         fields[0].in_handler = NULL;
 258         fields[0].in_handler_priv = NULL;
 259
 260         fields[1].device = jtag_info->chain_pos;
 261         fields[1].num_bits = 32;
 262         fields[1].out_value = cp15_opcode_buf;
 263         fields[1].out_mask = NULL;
 264         fields[1].in_value = NULL;
 265         fields[1].in_check_value = NULL;
 266         fields[1].in_check_mask = NULL;
 267         fields[1].in_handler = NULL;
 268         fields[1].in_handler_priv = NULL;
 269
 270         fields[2].device = jtag_info->chain_pos;
 271         fields[2].num_bits = 6;
 272         fields[2].out_value = &reg_addr_buf;
 273         fields[2].out_mask = NULL;
 274         fields[2].in_value = NULL;
 275         fields[2].in_check_value = NULL;
 276         fields[2].in_check_mask = NULL;
 277         fields[2].in_handler = NULL;
 278         fields[2].in_handler_priv = NULL;
 279
 280         fields[3].device = jtag_info->chain_pos;
 281         fields[3].num_bits = 1;
 282         fields[3].out_value = &nr_w_buf;
 283         fields[3].out_mask = NULL;
 284         fields[3].in_value = NULL;
 285         fields[3].in_check_value = NULL;
 286         fields[3].in_check_mask = NULL;
 287         fields[3].in_handler = NULL;
 288         fields[3].in_handler_priv = NULL;
 289
 290         jtag_add_dr_scan(4, fields, -1);
 291
 292         arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 293         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 294         arm7_9_execute_sys_speed(target);
 295
 296         if (jtag_execute_queue() != ERROR_OK)
 297         {
 298                 LOG_ERROR("failed executing JTAG queue, exiting");
 299                 exit(-1);
 300         }
 301
 302         return ERROR_OK;
 303 }
 304
 305 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)
 306 {
 307         armv4_5_common_t *armv4_5 = target->arch_info;
 308         u32* regs_p[1];
 309         u32 regs[2];
 310         u32 cp15c15 = 0x0;
 311
 312         /* load address into R1 */
 313         regs[1] = address;
 314         arm9tdmi_write_core_regs(target, 0x2, regs);
 315
 316         /* read-modify-write CP15 test state register
 317         * to enable interpreted access mode */
 318         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 319         jtag_execute_queue();
 320         cp15c15 |= 1;   /* set interpret mode */
 321         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 322
 323         /* execute CP15 instruction and ARM load (reading from coprocessor) */
 324         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 325
 326         /* disable interpreted access mode */
 327         cp15c15 &= ~1U; /* clear interpret mode */
 328         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 329
 330         /* retrieve value from R0 */
 331         regs_p[0] = value;
 332         arm9tdmi_read_core_regs(target, 0x1, regs_p);
 333         jtag_execute_queue();
 334
 335 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 336         LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 337 #endif
 338
 339         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 340                 return ERROR_FAIL;
 341
 342         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 343         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 344
 345         return ERROR_OK;
 346 }
 347
 348 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)
 349 {
 350         u32 cp15c15 = 0x0;
 351         armv4_5_common_t *armv4_5 = target->arch_info;
 352         u32 regs[2];
 353
 354         /* load value, address into R0, R1 */
 355         regs[0] = value;
 356         regs[1] = address;
 357         arm9tdmi_write_core_regs(target, 0x3, regs);
 358
 359         /* read-modify-write CP15 test state register
 360         * to enable interpreted access mode */
 361         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 362         jtag_execute_queue();
 363         cp15c15 |= 1;   /* set interpret mode */
 364         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 365
 366         /* execute CP15 instruction and ARM store (writing to coprocessor) */
 367         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 368
 369         /* disable interpreted access mode */
 370         cp15c15 &= ~1U; /* set interpret mode */
 371         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 372
 373 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 374         LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 375 #endif
 376
 377         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 378                 return ERROR_FAIL;
 379
 380         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
 381         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;
 382
 383         return ERROR_OK;
 384 }
 385
 386 u32 arm920t_get_ttb(target_t *target)
 387 {
 388         int retval;
 389         u32 ttb = 0x0;
 390
 391         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 392                 return retval;
 393
 394         return ttb;
 395 }
 396
 397 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 398 {
 399         u32 cp15_control;
 400
 401         /* read cp15 control register */
 402         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 403         jtag_execute_queue();
 404
 405         if (mmu)
 406                 cp15_control &= ~0x1U;
 407
 408         if (d_u_cache)
 409                 cp15_control &= ~0x4U;
 410
 411         if (i_cache)
 412                 cp15_control &= ~0x1000U;
 413
 414         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 415 }
 416
 417 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
 418 {
 419         u32 cp15_control;
 420
 421         /* read cp15 control register */
 422         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 423         jtag_execute_queue();
 424
 425         if (mmu)
 426                 cp15_control |= 0x1U;
 427
 428         if (d_u_cache)
 429                 cp15_control |= 0x4U;
 430
 431         if (i_cache)
 432                 cp15_control |= 0x1000U;
 433
 434         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 435 }
 436
 437 void arm920t_post_debug_entry(target_t *target)
 438 {
 439         u32 cp15c15;
 440         armv4_5_common_t *armv4_5 = target->arch_info;
 441         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 442         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 443         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 444
 445         /* examine cp15 control reg */
 446         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 447         jtag_execute_queue();
 448         LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
 449
 450         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 451         {
 452                 u32 cache_type_reg;
 453                 /* identify caches */
 454                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 455                 jtag_execute_queue();
 456                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 457         }
 458
 459         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
 460         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 461         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 462
 463         /* save i/d fault status and address register */
 464         arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 465         arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 466         arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 467         arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 468
 469         LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
 470                 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 471
 472         if (arm920t->preserve_cache)
 473         {
 474                 /* read-modify-write CP15 test state register
 475                  * to disable I/D-cache linefills */
 476                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 477                 jtag_execute_queue();
 478                 cp15c15 |= 0x600;
 479                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 480         }
 481 }
 482
 483 void arm920t_pre_restore_context(target_t *target)
 484 {
 485         u32 cp15c15;
 486         armv4_5_common_t *armv4_5 = target->arch_info;
 487         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 488         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 489         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 490
 491         /* restore i/d fault status and address register */
 492         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
 493         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
 494         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
 495         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
 496
 497         /* read-modify-write CP15 test state register
 498         * to reenable I/D-cache linefills */
 499         if (arm920t->preserve_cache)
 500         {
 501                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 502                 jtag_execute_queue();
 503                 cp15c15 &= ~0x600U;
 504                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 505         }
 506 }
 507
 508 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)
 509 {
 510         armv4_5_common_t *armv4_5 = target->arch_info;
 511         arm7_9_common_t *arm7_9;
 512         arm9tdmi_common_t *arm9tdmi;
 513         arm920t_common_t *arm920t;
 514
 515         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 516         {
 517                 return -1;
 518         }
 519
 520         arm7_9 = armv4_5->arch_info;
 521         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)
 522         {
 523                 return -1;
 524         }
 525
 526         arm9tdmi = arm7_9->arch_info;
 527         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)
 528         {
 529                 return -1;
 530         }
 531
 532         arm920t = arm9tdmi->arch_info;
 533         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
 534         {
 535                 return -1;
 536         }
 537
 538         *armv4_5_p = armv4_5;
 539         *arm7_9_p = arm7_9;
 540         *arm9tdmi_p = arm9tdmi;
 541         *arm920t_p = arm920t;
 542
 543         return ERROR_OK;
 544 }
 545
 546 int arm920t_arch_state(struct target_s *target)
 547 {
 548         armv4_5_common_t *armv4_5 = target->arch_info;
 549         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 550         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 551         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 552
 553         char *state[] =
 554         {
 555                 "disabled", "enabled"
 556         };
 557
 558         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
 559         {
 560                 LOG_ERROR("BUG: called for a non-ARMv4/5 target");
 561                 exit(-1);
 562         }
 563
 564         LOG_USER(       "target halted in %s state due to %s, current mode: %s\n"
 565                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"
 566                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 567                          armv4_5_state_strings[armv4_5->core_state],
 568                          target_debug_reason_strings[target->debug_reason],
 569                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
 570                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 571                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 572                          state[arm920t->armv4_5_mmu.mmu_enabled],
 573                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 574                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 575
 576         return ERROR_OK;
 577 }
 578
 579 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 580 {
 581         int retval;
 582
 583         retval = arm7_9_read_memory(target, address, size, count, buffer);
 584
 585         return retval;
 586 }
 587
 588 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)
 589 {
 590         int retval;
 591         armv4_5_common_t *armv4_5 = target->arch_info;
 592         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 593         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 594         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 595
 596         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 597                 return retval;
 598
 599         if (((size == 4) || (size == 2)) && (count == 1))
 600         {
 601                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 602                 {
 603                         LOG_DEBUG("D-Cache enabled, writing through to main memory");
 604                         u32 pa, cb, ap;
 605                         int type, domain;
 606
 607                         pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);
 608                         if (type == -1)
 609                                 return ERROR_OK;
 610                         /* cacheable & bufferable means write-back region */
 611                         if (cb == 3)
 612                                 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);
 613                 }
 614
 615                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 616                 {
 617                         LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
 618                         arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
 619                 }
 620         }
 621
 622         return retval;
 623 }
 624
 625 int arm920t_soft_reset_halt(struct target_s *target)
 626 {
 627         armv4_5_common_t *armv4_5 = target->arch_info;
 628         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 629         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
 630         arm920t_common_t *arm920t = arm9tdmi->arch_info;
 631         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 632         int i;
 633
 634         target_halt(target);
 635
 636         for (i=0; i<10; i++)
 637         {
 638                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 639                 {
 640                         embeddedice_read_reg(dbg_stat);
 641                         jtag_execute_queue();
 642                 } else
 643                 {
 644                         break;
 645                 }
 646                 /* do not eat all CPU, time out after 1 se*/
 647                 usleep(100*1000);
 648         }
 649         if (i==10)
 650         {
 651                 LOG_ERROR("Failed to halt CPU after 1 sec");
 652                 return ERROR_TARGET_TIMEOUT;
 653         }
 654
 655         target->state = TARGET_HALTED;
 656
 657         /* SVC, ARM state, IRQ and FIQ disabled */
 658         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);
 659         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
 660         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 661
 662         /* start fetching from 0x0 */
 663         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 664         armv4_5->core_cache->reg_list[15].dirty = 1;
 665         armv4_5->core_cache->reg_list[15].valid = 1;
 666
 667         armv4_5->core_mode = ARMV4_5_MODE_SVC;
 668         armv4_5->core_state = ARMV4_5_STATE_ARM;
 669
 670         arm920t_disable_mmu_caches(target, 1, 1, 1);
 671         arm920t->armv4_5_mmu.mmu_enabled = 0;
 672         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 673         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 674
 675         target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 676
 677         return ERROR_OK;
 678 }
 679
 680 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 681 {
 682         arm9tdmi_init_target(cmd_ctx, target);
 683
 684         return ERROR_OK;
 685
 686 }
 687
 688 int arm920t_quit(void)
 689 {
 690
 691         return ERROR_OK;
 692 }
 693
 694 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)
 695 {
 696         arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;
 697         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
 698
 699         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)
 700          */
 701         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
 702
 703         arm9tdmi->arch_info = arm920t;
 704         arm920t->common_magic = ARM920T_COMMON_MAGIC;
 705
 706         arm7_9->post_debug_entry = arm920t_post_debug_entry;
 707         arm7_9->pre_restore_context = arm920t_pre_restore_context;
 708
 709         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 710         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
 711         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 712         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 713         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 714         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 715         arm920t->armv4_5_mmu.has_tiny_pages = 1;
 716         arm920t->armv4_5_mmu.mmu_enabled = 0;
 717
 718         /* disabling linefills leads to lockups, so keep them enabled for now
 719          * this doesn't affect correctness, but might affect timing issues, if
 720          * important data is evicted from the cache during the debug session
 721          * */
 722         arm920t->preserve_cache = 0;
 723
 724         /* override hw single-step capability from ARM9TDMI */
 725         arm7_9->has_single_step = 1;
 726
 727         return ERROR_OK;
 728 }
 729
 730 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
 731 {
 732         int chain_pos;
 733         char *variant = NULL;
 734         arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));
 735         memset(arm920t, 0, sizeof(*arm920t));
 736
 737         if (argc < 4)
 738         {
 739                 LOG_ERROR("'target arm920t' requires at least one additional argument");
 740                 exit(-1);
 741         }
 742
 743         chain_pos = strtoul(args[3], NULL, 0);
 744
 745         if (argc >= 5)
 746                 variant = args[4];
 747
 748         LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
 749
 750         arm920t_init_arch_info(target, arm920t, chain_pos, variant);
 751
 752         return ERROR_OK;
 753 }
 754
 755 int arm920t_register_commands(struct command_context_s *cmd_ctx)
 756 {
 757         int retval;
 758         command_t *arm920t_cmd;
 759
 760
 761         retval = arm9tdmi_register_commands(cmd_ctx);
 762
 763         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");
 764
 765         register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
 766         register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
 767         register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
 768         register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
 769
 770         register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
 771         register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
 772         register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
 773
 774         register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
 775         register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
 776         register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
 777
 778         register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
 779         register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
 780
 781         return ERROR_OK;
 782 }
 783
 784 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 785 {
 786         target_t *target = get_current_target(cmd_ctx);
 787         armv4_5_common_t *armv4_5;
 788         arm7_9_common_t *arm7_9;
 789         arm9tdmi_common_t *arm9tdmi;
 790         arm920t_common_t *arm920t;
 791         arm_jtag_t *jtag_info;
 792         u32 cp15c15;
 793         u32 cp15_ctrl, cp15_ctrl_saved;
 794         u32 regs[16];
 795         u32 *regs_p[16];
 796         u32 C15_C_D_Ind, C15_C_I_Ind;
 797         int i;
 798         FILE *output;
 799         arm920t_cache_line_t d_cache[8][64], i_cache[8][64];
 800         int segment, index;
 801
 802         if (argc != 1)
 803         {
 804                 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");
 805                 return ERROR_OK;
 806         }
 807
 808         if ((output = fopen(args[0], "w")) == NULL)
 809         {
 810                 LOG_DEBUG("error opening cache content file");
 811                 return ERROR_OK;
 812         }
 813
 814         for (i = 0; i < 16; i++)
 815                 regs_p[i] = &regs[i];
 816
 817         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
 818         {
 819                 command_print(cmd_ctx, "current target isn't an ARM920t target");
 820                 return ERROR_OK;
 821         }
 822
 823         jtag_info = &arm7_9->jtag_info;
 824
 825         /* disable MMU and Caches */
 826         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
 827         jtag_execute_queue();
 828         cp15_ctrl_saved = cp15_ctrl;
 829         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 830         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 831
 832         /* read CP15 test state register */
 833         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
 834         jtag_execute_queue();
 835
 836         /* read DCache content */
 837         fprintf(output, "DCache:\n");
 838
 839         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 840         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 841         {
 842                 fprintf(output, "\nsegment: %i\n----------", segment);
 843
 844                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 845                 regs[0] = 0x0 | (segment << 5);
 846                 arm9tdmi_write_core_regs(target, 0x1, regs);
 847
 848                 /* set interpret mode */
 849                 cp15c15 |= 0x1;
 850                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 851
 852                 /* D CAM Read, loads current victim into C15.C.D.Ind */
 853                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 854
 855                 /* read current victim */
 856                 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
 857
 858                 /* clear interpret mode */
 859                 cp15c15 &= ~0x1;
 860                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 861
 862                 for (index = 0; index < 64; index++)
 863                 {
 864                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 865                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 866                         arm9tdmi_write_core_regs(target, 0x1, regs);
 867
 868                         /* set interpret mode */
 869                         cp15c15 |= 0x1;
 870                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 871
 872                         /* Write DCache victim */
 873                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 874
 875                         /* Read D RAM */
 876                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 877
 878                         /* Read D CAM */
 879                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
 880
 881                         /* clear interpret mode */
 882                         cp15c15 &= ~0x1;
 883                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 884
 885                         /* read D RAM and CAM content */
 886                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 887                         jtag_execute_queue();
 888
 889                         d_cache[segment][index].cam = regs[9];
 890
 891                         /* mask LFSR[6] */
 892                         regs[9] &= 0xfffffffe;
 893                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 894
 895                         for (i = 1; i < 9; i++)
 896                         {
 897                                  d_cache[segment][index].data[i] = regs[i];
 898                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 899                         }
 900
 901                 }
 902
 903                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 904                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 905                 arm9tdmi_write_core_regs(target, 0x1, regs);
 906
 907                 /* set interpret mode */
 908                 cp15c15 |= 0x1;
 909                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 910
 911                 /* Write DCache victim */
 912                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 913
 914                 /* clear interpret mode */
 915                 cp15c15 &= ~0x1;
 916                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 917         }
 918
 919         /* read ICache content */
 920         fprintf(output, "ICache:\n");
 921
 922         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 923         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 924         {
 925                 fprintf(output, "segment: %i\n----------", segment);
 926
 927                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 928                 regs[0] = 0x0 | (segment << 5);
 929                 arm9tdmi_write_core_regs(target, 0x1, regs);
 930
 931                 /* set interpret mode */
 932                 cp15c15 |= 0x1;
 933                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 934
 935                 /* I CAM Read, loads current victim into C15.C.I.Ind */
 936                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 937
 938                 /* read current victim */
 939                 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
 940
 941                 /* clear interpret mode */
 942                 cp15c15 &= ~0x1;
 943                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 944
 945                 for (index = 0; index < 64; index++)
 946                 {
 947                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 948                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 949                         arm9tdmi_write_core_regs(target, 0x1, regs);
 950
 951                         /* set interpret mode */
 952                         cp15c15 |= 0x1;
 953                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 954
 955                         /* Write ICache victim */
 956                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 957
 958                         /* Read I RAM */
 959                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 960
 961                         /* Read I CAM */
 962                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
 963
 964                         /* clear interpret mode */
 965                         cp15c15 &= ~0x1;
 966                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 967
 968                         /* read I RAM and CAM content */
 969                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 970                         jtag_execute_queue();
 971
 972                         i_cache[segment][index].cam = regs[9];
 973
 974                         /* mask LFSR[6] */
 975                         regs[9] &= 0xfffffffe;
 976                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 977
 978                         for (i = 1; i < 9; i++)
 979                         {
 980                                  i_cache[segment][index].data[i] = regs[i];
 981                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
 982                         }
 983
 984                 }
 985
 986
 987                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 988                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 989                 arm9tdmi_write_core_regs(target, 0x1, regs);
 990
 991                 /* set interpret mode */
 992                 cp15c15 |= 0x1;
 993                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 994
 995                 /* Write ICache victim */
 996                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 997
 998                 /* clear interpret mode */
 999                 cp15c15 &= ~0x1;
1000                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1001         }
1002
1003         /* restore CP15 MMU and Cache settings */
1004         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1005
1006         command_print(cmd_ctx, "cache content successfully output to %s", args[0]);
1007
1008         fclose(output);
1009
1010         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1011                 return ERROR_FAIL;
1012
1013         /* mark registers dirty. */
1014         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1015         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1016         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1017         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1018         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1019         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1020         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1021         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1022         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1023         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1024
1025         return ERROR_OK;
1026 }
1027
1028 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1029 {
1030         target_t *target = get_current_target(cmd_ctx);
1031         armv4_5_common_t *armv4_5;
1032         arm7_9_common_t *arm7_9;
1033         arm9tdmi_common_t *arm9tdmi;
1034         arm920t_common_t *arm920t;
1035         arm_jtag_t *jtag_info;
1036         u32 cp15c15;
1037         u32 cp15_ctrl, cp15_ctrl_saved;
1038         u32 regs[16];
1039         u32 *regs_p[16];
1040         int i;
1041         FILE *output;
1042         u32 Dlockdown, Ilockdown;
1043         arm920t_tlb_entry_t d_tlb[64], i_tlb[64];
1044         int victim;
1045
1046         if (argc != 1)
1047         {
1048                 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");
1049                 return ERROR_OK;
1050         }
1051
1052         if ((output = fopen(args[0], "w")) == NULL)
1053         {
1054                 LOG_DEBUG("error opening mmu content file");
1055                 return ERROR_OK;
1056         }
1057
1058         for (i = 0; i < 16; i++)
1059                 regs_p[i] = &regs[i];
1060
1061         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1062         {
1063                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1064                 return ERROR_OK;
1065         }
1066
1067         jtag_info = &arm7_9->jtag_info;
1068
1069         /* disable MMU and Caches */
1070         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
1071         jtag_execute_queue();
1072         cp15_ctrl_saved = cp15_ctrl;
1073         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
1074         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
1075
1076         /* read CP15 test state register */
1077         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
1078         jtag_execute_queue();
1079
1080         /* prepare reading D TLB content
1081          * */
1082
1083         /* set interpret mode */
1084         cp15c15 |= 0x1;
1085         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1086
1087         /* Read D TLB lockdown */
1088         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
1089
1090         /* clear interpret mode */
1091         cp15c15 &= ~0x1;
1092         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1093
1094         /* read D TLB lockdown stored to r1 */
1095         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1096         jtag_execute_queue();
1097         Dlockdown = regs[1];
1098
1099         for (victim = 0; victim < 64; victim += 8)
1100         {
1101                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1102                  * base remains unchanged, victim goes through entries 0 to 63 */
1103                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1104                 arm9tdmi_write_core_regs(target, 0x2, regs);
1105
1106                 /* set interpret mode */
1107                 cp15c15 |= 0x1;
1108                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1109
1110                 /* Write D TLB lockdown */
1111                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1112
1113                 /* Read D TLB CAM */
1114                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1115
1116                 /* clear interpret mode */
1117                 cp15c15 &= ~0x1;
1118                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1119
1120                 /* read D TLB CAM content stored to r2-r9 */
1121                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1122                 jtag_execute_queue();
1123
1124                 for (i = 0; i < 8; i++)
1125                         d_tlb[victim + i].cam = regs[i + 2];
1126         }
1127
1128         for (victim = 0; victim < 64; victim++)
1129         {
1130                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1131                  * base remains unchanged, victim goes through entries 0 to 63 */
1132                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1133                 arm9tdmi_write_core_regs(target, 0x2, regs);
1134
1135                 /* set interpret mode */
1136                 cp15c15 |= 0x1;
1137                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1138
1139                 /* Write D TLB lockdown */
1140                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1141
1142                 /* Read D TLB RAM1 */
1143                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1144
1145                 /* Read D TLB RAM2 */
1146                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1147
1148                 /* clear interpret mode */
1149                 cp15c15 &= ~0x1;
1150                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1151
1152                 /* read D TLB RAM content stored to r2 and r3 */
1153                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1154                 jtag_execute_queue();
1155
1156                 d_tlb[victim].ram1 = regs[2];
1157                 d_tlb[victim].ram2 = regs[3];
1158         }
1159
1160         /* restore D TLB lockdown */
1161         regs[1] = Dlockdown;
1162         arm9tdmi_write_core_regs(target, 0x2, regs);
1163
1164         /* Write D TLB lockdown */
1165         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1166
1167         /* prepare reading I TLB content
1168          * */
1169
1170         /* set interpret mode */
1171         cp15c15 |= 0x1;
1172         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1173
1174         /* Read I TLB lockdown */
1175         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1176
1177         /* clear interpret mode */
1178         cp15c15 &= ~0x1;
1179         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1180
1181         /* read I TLB lockdown stored to r1 */
1182         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1183         jtag_execute_queue();
1184         Ilockdown = regs[1];
1185
1186         for (victim = 0; victim < 64; victim += 8)
1187         {
1188                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1189                  * base remains unchanged, victim goes through entries 0 to 63 */
1190                 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1191                 arm9tdmi_write_core_regs(target, 0x2, regs);
1192
1193                 /* set interpret mode */
1194                 cp15c15 |= 0x1;
1195                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1196
1197                 /* Write I TLB lockdown */
1198                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1199
1200                 /* Read I TLB CAM */
1201                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1202
1203                 /* clear interpret mode */
1204                 cp15c15 &= ~0x1;
1205                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1206
1207                 /* read I TLB CAM content stored to r2-r9 */
1208                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1209                 jtag_execute_queue();
1210
1211                 for (i = 0; i < 8; i++)
1212                         i_tlb[i + victim].cam = regs[i + 2];
1213         }
1214
1215         for (victim = 0; victim < 64; victim++)
1216         {
1217                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1218                  * base remains unchanged, victim goes through entries 0 to 63 */
1219                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1220                 arm9tdmi_write_core_regs(target, 0x2, regs);
1221
1222                 /* set interpret mode */
1223                 cp15c15 |= 0x1;
1224                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1225
1226                 /* Write I TLB lockdown */
1227                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1228
1229                 /* Read I TLB RAM1 */
1230                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1231
1232                 /* Read I TLB RAM2 */
1233                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1234
1235                 /* clear interpret mode */
1236                 cp15c15 &= ~0x1;
1237                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1238
1239                 /* read I TLB RAM content stored to r2 and r3 */
1240                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1241                 jtag_execute_queue();
1242
1243                 i_tlb[victim].ram1 = regs[2];
1244                 i_tlb[victim].ram2 = regs[3];
1245         }
1246
1247         /* restore I TLB lockdown */
1248         regs[1] = Ilockdown;
1249         arm9tdmi_write_core_regs(target, 0x2, regs);
1250
1251         /* Write I TLB lockdown */
1252         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1253
1254         /* restore CP15 MMU and Cache settings */
1255         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1256
1257         /* output data to file */
1258         fprintf(output, "D TLB content:\n");
1259         for (i = 0; i < 64; i++)
1260         {
1261                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1262         }
1263
1264         fprintf(output, "\n\nI TLB content:\n");
1265         for (i = 0; i < 64; i++)
1266         {
1267                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1268         }
1269
1270         command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
1271
1272         fclose(output);
1273
1274         if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
1275                 return ERROR_FAIL;
1276
1277         /* mark registers dirty */
1278         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
1279         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;
1280         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;
1281         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;
1282         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;
1283         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;
1284         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;
1285         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;
1286         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;
1287         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;
1288
1289         return ERROR_OK;
1290 }
1291 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1292 {
1293         int retval;
1294         target_t *target = get_current_target(cmd_ctx);
1295         armv4_5_common_t *armv4_5;
1296         arm7_9_common_t *arm7_9;
1297         arm9tdmi_common_t *arm9tdmi;
1298         arm920t_common_t *arm920t;
1299         arm_jtag_t *jtag_info;
1300
1301         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1302         {
1303                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1304                 return ERROR_OK;
1305         }
1306
1307         jtag_info = &arm7_9->jtag_info;
1308
1309         if (target->state != TARGET_HALTED)
1310         {
1311                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1312                 return ERROR_OK;
1313         }
1314
1315         /* one or more argument, access a single register (write if second argument is given */
1316         if (argc >= 1)
1317         {
1318                 int address = strtoul(args[0], NULL, 0);
1319
1320                 if (argc == 1)
1321                 {
1322                         u32 value;
1323                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1324                         {
1325                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1326                                 return ERROR_OK;
1327                         }
1328                         jtag_execute_queue();
1329
1330                         command_print(cmd_ctx, "%i: %8.8x", address, value);
1331                 }
1332                 else if (argc == 2)
1333                 {
1334                         u32 value = strtoul(args[1], NULL, 0);
1335                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1336                         {
1337                                 command_print(cmd_ctx, "couldn't access reg %i", address);
1338                                 return ERROR_OK;
1339                         }
1340                         command_print(cmd_ctx, "%i: %8.8x", address, value);
1341                 }
1342         }
1343
1344         return ERROR_OK;
1345 }
1346
1347 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1348 {
1349         int retval;
1350         target_t *target = get_current_target(cmd_ctx);
1351         armv4_5_common_t *armv4_5;
1352         arm7_9_common_t *arm7_9;
1353         arm9tdmi_common_t *arm9tdmi;
1354         arm920t_common_t *arm920t;
1355         arm_jtag_t *jtag_info;
1356
1357         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1358         {
1359                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1360                 return ERROR_OK;
1361         }
1362
1363         jtag_info = &arm7_9->jtag_info;
1364
1365         if (target->state != TARGET_HALTED)
1366         {
1367                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1368                 return ERROR_OK;
1369         }
1370
1371         /* one or more argument, access a single register (write if second argument is given */
1372         if (argc >= 1)
1373         {
1374                 u32 opcode = strtoul(args[0], NULL, 0);
1375
1376                 if (argc == 1)
1377                 {
1378                         u32 value;
1379                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1380                         {
1381                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1382                                 return ERROR_OK;
1383                         }
1384
1385                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1386                 }
1387                 else if (argc == 2)
1388                 {
1389                         u32 value = strtoul(args[1], NULL, 0);
1390                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1391                         {
1392                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1393                                 return ERROR_OK;
1394                         }
1395                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
1396                 }
1397                 else if (argc == 3)
1398                 {
1399                         u32 value = strtoul(args[1], NULL, 0);
1400                         u32 address = strtoul(args[2], NULL, 0);
1401                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1402                         {
1403                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
1404                                 return ERROR_OK;
1405                         }
1406                         command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
1407                 }
1408         }
1409         else
1410         {
1411                 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");
1412         }
1413
1414         return ERROR_OK;
1415 }
1416
1417 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1418 {
1419         target_t *target = get_current_target(cmd_ctx);
1420         armv4_5_common_t *armv4_5;
1421         arm7_9_common_t *arm7_9;
1422         arm9tdmi_common_t *arm9tdmi;
1423         arm920t_common_t *arm920t;
1424
1425         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1426         {
1427                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1428                 return ERROR_OK;
1429         }
1430
1431         return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
1432 }
1433
1434 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1435 {
1436         target_t *target = get_current_target(cmd_ctx);
1437         armv4_5_common_t *armv4_5;
1438         arm7_9_common_t *arm7_9;
1439         arm9tdmi_common_t *arm9tdmi;
1440         arm920t_common_t *arm920t;
1441         arm_jtag_t *jtag_info;
1442
1443         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1444         {
1445                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1446                 return ERROR_OK;
1447         }
1448
1449         jtag_info = &arm7_9->jtag_info;
1450
1451         if (target->state != TARGET_HALTED)
1452         {
1453                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1454                 return ERROR_OK;
1455         }
1456
1457         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1458 }
1459
1460 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1461 {
1462         target_t *target = get_current_target(cmd_ctx);
1463         armv4_5_common_t *armv4_5;
1464         arm7_9_common_t *arm7_9;
1465         arm9tdmi_common_t *arm9tdmi;
1466         arm920t_common_t *arm920t;
1467         arm_jtag_t *jtag_info;
1468
1469         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1470         {
1471                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1472                 return ERROR_OK;
1473         }
1474
1475         jtag_info = &arm7_9->jtag_info;
1476
1477         if (target->state != TARGET_HALTED)
1478         {
1479                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1480                 return ERROR_OK;
1481         }
1482
1483         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1484 }
1485
1486 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
1487 {
1488         target_t *target = get_current_target(cmd_ctx);
1489         armv4_5_common_t *armv4_5;
1490         arm7_9_common_t *arm7_9;
1491         arm9tdmi_common_t *arm9tdmi;
1492         arm920t_common_t *arm920t;
1493         arm_jtag_t *jtag_info;
1494
1495         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
1496         {
1497                 command_print(cmd_ctx, "current target isn't an ARM920t target");
1498                 return ERROR_OK;
1499         }
1500
1501         jtag_info = &arm7_9->jtag_info;
1502
1503         if (target->state != TARGET_HALTED)
1504         {
1505                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
1506                 return ERROR_OK;
1507         }
1508
1509         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
1510 }