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   1 /***************************************************************************\r
   2  *   Copyright (C) 2005 by Dominic Rath                                    *\r
   3  *   Dominic.Rath@gmx.de                                                   *\r
   4  *                                                                         *\r
   5  *   This program is free software; you can redistribute it and/or modify  *\r
   6  *   it under the terms of the GNU General Public License as published by  *\r
   7  *   the Free Software Foundation; either version 2 of the License, or     *\r
   8  *   (at your option) any later version.                                   *\r
   9  *                                                                         *\r
  10  *   This program is distributed in the hope that it will be useful,       *\r
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *\r
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *\r
  13  *   GNU General Public License for more details.                          *\r
  14  *                                                                         *\r
  15  *   You should have received a copy of the GNU General Public License     *\r
  16  *   along with this program; if not, write to the                         *\r
  17  *   Free Software Foundation, Inc.,                                       *\r
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *\r
  19  ***************************************************************************/\r
  20 #ifdef HAVE_CONFIG_H\r
  21 #include "config.h"\r
  22 #endif\r
  23 \r
  24 #include "arm920t.h"\r
  25 #include "jtag.h"\r
  26 #include "log.h"\r
  27 \r
  28 #include <stdlib.h>\r
  29 #include <string.h>\r
  30 \r
  31 #if 0\r
  32 #define _DEBUG_INSTRUCTION_EXECUTION_\r
  33 #endif\r
  34 \r
  35 /* cli handling */\r
  36 int arm920t_register_commands(struct command_context_s *cmd_ctx);\r
  37 \r
  38 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  39 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  40 int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  41 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  42 int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  43 int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  44 \r
  45 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  46 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);\r
  47 \r
  48 /* forward declarations */\r
  49 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);\r
  50 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target);\r
  51 int arm920t_quit();\r
  52 int arm920t_arch_state(struct target_s *target);\r
  53 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
  54 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);\r
  55 int arm920t_soft_reset_halt(struct target_s *target);\r
  56 \r
  57 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))\r
  58 \r
  59 target_type_t arm920t_target =\r
  60 {\r
  61         .name = "arm920t",\r
  62 \r
  63         .poll = arm7_9_poll,\r
  64         .arch_state = arm920t_arch_state,\r
  65 \r
  66         .target_request_data = arm7_9_target_request_data,\r
  67 \r
  68         .halt = arm7_9_halt,\r
  69         .resume = arm7_9_resume,\r
  70         .step = arm7_9_step,\r
  71 \r
  72         .assert_reset = arm7_9_assert_reset,\r
  73         .deassert_reset = arm7_9_deassert_reset,\r
  74         .soft_reset_halt = arm920t_soft_reset_halt,\r
  75         .prepare_reset_halt = arm7_9_prepare_reset_halt,\r
  76         \r
  77         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,\r
  78 \r
  79         .read_memory = arm920t_read_memory,\r
  80         .write_memory = arm920t_write_memory,\r
  81         .bulk_write_memory = arm7_9_bulk_write_memory,\r
  82         .checksum_memory = arm7_9_checksum_memory,\r
  83         \r
  84         .run_algorithm = armv4_5_run_algorithm,\r
  85 \r
  86         .add_breakpoint = arm7_9_add_breakpoint,\r
  87         .remove_breakpoint = arm7_9_remove_breakpoint,\r
  88         .add_watchpoint = arm7_9_add_watchpoint,\r
  89         .remove_watchpoint = arm7_9_remove_watchpoint,\r
  90 \r
  91         .register_commands = arm920t_register_commands,\r
  92         .target_command = arm920t_target_command,\r
  93         .init_target = arm920t_init_target,\r
  94         .quit = arm920t_quit\r
  95 };\r
  96 \r
  97 int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)\r
  98 {\r
  99         armv4_5_common_t *armv4_5 = target->arch_info;\r
 100         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 101         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 102         scan_field_t fields[4];\r
 103         u8 access_type_buf = 1;\r
 104         u8 reg_addr_buf = reg_addr & 0x3f;\r
 105         u8 nr_w_buf = 0;\r
 106         \r
 107         jtag_add_end_state(TAP_RTI);\r
 108         arm_jtag_scann(jtag_info, 0xf);\r
 109         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 110 \r
 111         fields[0].device = jtag_info->chain_pos;\r
 112         fields[0].num_bits = 1;\r
 113         fields[0].out_value = &access_type_buf;\r
 114         fields[0].out_mask = NULL;\r
 115         fields[0].in_value = NULL;\r
 116         fields[0].in_check_value = NULL;\r
 117         fields[0].in_check_mask = NULL;\r
 118         fields[0].in_handler = NULL;\r
 119         fields[0].in_handler_priv = NULL;\r
 120 \r
 121         fields[1].device = jtag_info->chain_pos;\r
 122         fields[1].num_bits = 32;\r
 123         fields[1].out_value = NULL;\r
 124         fields[1].out_mask = NULL;\r
 125         fields[1].in_value = NULL;\r
 126         fields[1].in_check_value = NULL;\r
 127         fields[1].in_check_mask = NULL;\r
 128         fields[1].in_handler = NULL;\r
 129         fields[1].in_handler_priv = NULL;\r
 130 \r
 131         fields[2].device = jtag_info->chain_pos;\r
 132         fields[2].num_bits = 6;\r
 133         fields[2].out_value = &reg_addr_buf;\r
 134         fields[2].out_mask = NULL;\r
 135         fields[2].in_value = NULL;\r
 136         fields[2].in_check_value = NULL;\r
 137         fields[2].in_check_mask = NULL;\r
 138         fields[2].in_handler = NULL;\r
 139         fields[2].in_handler_priv = NULL;\r
 140 \r
 141         fields[3].device = jtag_info->chain_pos;\r
 142         fields[3].num_bits = 1;\r
 143         fields[3].out_value = &nr_w_buf;\r
 144         fields[3].out_mask = NULL;\r
 145         fields[3].in_value = NULL;\r
 146         fields[3].in_check_value = NULL;\r
 147         fields[3].in_check_mask = NULL;\r
 148         fields[3].in_handler = NULL;\r
 149         fields[3].in_handler_priv = NULL;\r
 150         \r
 151         jtag_add_dr_scan(4, fields, -1);\r
 152 \r
 153         fields[1].in_handler_priv = value;\r
 154         fields[1].in_handler = arm_jtag_buf_to_u32;\r
 155 \r
 156         jtag_add_dr_scan(4, fields, -1);\r
 157 \r
 158 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 159         jtag_execute_queue();\r
 160         DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);\r
 161 #endif\r
 162 \r
 163         return ERROR_OK;\r
 164 }\r
 165 \r
 166 int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)\r
 167 {\r
 168         armv4_5_common_t *armv4_5 = target->arch_info;\r
 169         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 170         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 171         scan_field_t fields[4];\r
 172         u8 access_type_buf = 1;\r
 173         u8 reg_addr_buf = reg_addr & 0x3f;\r
 174         u8 nr_w_buf = 1;\r
 175         u8 value_buf[4];\r
 176         \r
 177         buf_set_u32(value_buf, 0, 32, value);\r
 178         \r
 179         jtag_add_end_state(TAP_RTI);\r
 180         arm_jtag_scann(jtag_info, 0xf);\r
 181         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 182 \r
 183         fields[0].device = jtag_info->chain_pos;\r
 184         fields[0].num_bits = 1;\r
 185         fields[0].out_value = &access_type_buf;\r
 186         fields[0].out_mask = NULL;\r
 187         fields[0].in_value = NULL;\r
 188         fields[0].in_check_value = NULL;\r
 189         fields[0].in_check_mask = NULL;\r
 190         fields[0].in_handler = NULL;\r
 191         fields[0].in_handler_priv = NULL;\r
 192 \r
 193         fields[1].device = jtag_info->chain_pos;\r
 194         fields[1].num_bits = 32;\r
 195         fields[1].out_value = value_buf;\r
 196         fields[1].out_mask = NULL;\r
 197         fields[1].in_value = NULL;\r
 198         fields[1].in_check_value = NULL;\r
 199         fields[1].in_check_mask = NULL;\r
 200         fields[1].in_handler = NULL;\r
 201         fields[1].in_handler_priv = NULL;\r
 202 \r
 203         fields[2].device = jtag_info->chain_pos;\r
 204         fields[2].num_bits = 6;\r
 205         fields[2].out_value = &reg_addr_buf;\r
 206         fields[2].out_mask = NULL;\r
 207         fields[2].in_value = NULL;\r
 208         fields[2].in_check_value = NULL;\r
 209         fields[2].in_check_mask = NULL;\r
 210         fields[2].in_handler = NULL;\r
 211         fields[2].in_handler_priv = NULL;\r
 212 \r
 213         fields[3].device = jtag_info->chain_pos;\r
 214         fields[3].num_bits = 1;\r
 215         fields[3].out_value = &nr_w_buf;\r
 216         fields[3].out_mask = NULL;\r
 217         fields[3].in_value = NULL;\r
 218         fields[3].in_check_value = NULL;\r
 219         fields[3].in_check_mask = NULL;\r
 220         fields[3].in_handler = NULL;\r
 221         fields[3].in_handler_priv = NULL;\r
 222         \r
 223         jtag_add_dr_scan(4, fields, -1);\r
 224 \r
 225 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 226         DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);\r
 227 #endif\r
 228 \r
 229         return ERROR_OK;\r
 230 }\r
 231 \r
 232 int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)\r
 233 {\r
 234         armv4_5_common_t *armv4_5 = target->arch_info;\r
 235         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 236         arm_jtag_t *jtag_info = &arm7_9->jtag_info;\r
 237         scan_field_t fields[4];\r
 238         u8 access_type_buf = 0;         /* interpreted access */\r
 239         u8 reg_addr_buf = 0x0;\r
 240         u8 nr_w_buf = 0;\r
 241         u8 cp15_opcode_buf[4];\r
 242         \r
 243         jtag_add_end_state(TAP_RTI);\r
 244         arm_jtag_scann(jtag_info, 0xf);\r
 245         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);\r
 246         \r
 247         buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);\r
 248 \r
 249         fields[0].device = jtag_info->chain_pos;\r
 250         fields[0].num_bits = 1;\r
 251         fields[0].out_value = &access_type_buf;\r
 252         fields[0].out_mask = NULL;\r
 253         fields[0].in_value = NULL;\r
 254         fields[0].in_check_value = NULL;\r
 255         fields[0].in_check_mask = NULL;\r
 256         fields[0].in_handler = NULL;\r
 257         fields[0].in_handler_priv = NULL;\r
 258 \r
 259         fields[1].device = jtag_info->chain_pos;\r
 260         fields[1].num_bits = 32;\r
 261         fields[1].out_value = cp15_opcode_buf;\r
 262         fields[1].out_mask = NULL;\r
 263         fields[1].in_value = NULL;\r
 264         fields[1].in_check_value = NULL;\r
 265         fields[1].in_check_mask = NULL;\r
 266         fields[1].in_handler = NULL;\r
 267         fields[1].in_handler_priv = NULL;\r
 268 \r
 269         fields[2].device = jtag_info->chain_pos;\r
 270         fields[2].num_bits = 6;\r
 271         fields[2].out_value = &reg_addr_buf;\r
 272         fields[2].out_mask = NULL;\r
 273         fields[2].in_value = NULL;\r
 274         fields[2].in_check_value = NULL;\r
 275         fields[2].in_check_mask = NULL;\r
 276         fields[2].in_handler = NULL;\r
 277         fields[2].in_handler_priv = NULL;\r
 278 \r
 279         fields[3].device = jtag_info->chain_pos;\r
 280         fields[3].num_bits = 1;\r
 281         fields[3].out_value = &nr_w_buf;\r
 282         fields[3].out_mask = NULL;\r
 283         fields[3].in_value = NULL;\r
 284         fields[3].in_check_value = NULL;\r
 285         fields[3].in_check_mask = NULL;\r
 286         fields[3].in_handler = NULL;\r
 287         fields[3].in_handler_priv = NULL;\r
 288 \r
 289         jtag_add_dr_scan(4, fields, -1);\r
 290 \r
 291         arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);\r
 292         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);\r
 293         arm7_9_execute_sys_speed(target);\r
 294         \r
 295         if (jtag_execute_queue() != ERROR_OK)\r
 296         {\r
 297                 ERROR("failed executing JTAG queue, exiting");\r
 298                 exit(-1);\r
 299         }\r
 300         \r
 301         return ERROR_OK;\r
 302 }\r
 303 \r
 304 int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address, u32 *value)\r
 305 {\r
 306         armv4_5_common_t *armv4_5 = target->arch_info;\r
 307         u32* regs_p[1];\r
 308         u32 regs[2];\r
 309         u32 cp15c15 = 0x0;\r
 310 \r
 311         /* load address into R1 */\r
 312         regs[1] = address;\r
 313         arm9tdmi_write_core_regs(target, 0x2, regs); \r
 314         \r
 315         /* read-modify-write CP15 test state register \r
 316         * to enable interpreted access mode */\r
 317         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);     \r
 318         jtag_execute_queue();\r
 319         cp15c15 |= 1;   /* set interpret mode */\r
 320         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 321 \r
 322         /* execute CP15 instruction and ARM load (reading from coprocessor) */\r
 323         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));\r
 324         \r
 325         /* disable interpreted access mode */\r
 326         cp15c15 &= ~1U; /* clear interpret mode */\r
 327         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 328 \r
 329         /* retrieve value from R0 */\r
 330         regs_p[0] = value;\r
 331         arm9tdmi_read_core_regs(target, 0x1, regs_p);\r
 332         jtag_execute_queue();\r
 333         \r
 334 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 335         DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);\r
 336 #endif\r
 337 \r
 338         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;\r
 339         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;\r
 340 \r
 341         return ERROR_OK;\r
 342 }\r
 343 \r
 344 int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value, u32 address)\r
 345 {\r
 346         u32 cp15c15 = 0x0;\r
 347         armv4_5_common_t *armv4_5 = target->arch_info;\r
 348         u32 regs[2];\r
 349 \r
 350         /* load value, address into R0, R1 */\r
 351         regs[0] = value;\r
 352         regs[1] = address;\r
 353         arm9tdmi_write_core_regs(target, 0x3, regs);\r
 354 \r
 355         /* read-modify-write CP15 test state register \r
 356         * to enable interpreted access mode */\r
 357         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);\r
 358         jtag_execute_queue();\r
 359         cp15c15 |= 1;   /* set interpret mode */\r
 360         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 361 \r
 362         /* execute CP15 instruction and ARM store (writing to coprocessor) */\r
 363         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));\r
 364 \r
 365         /* disable interpreted access mode */\r
 366         cp15c15 &= ~1U; /* set interpret mode */\r
 367         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 368 \r
 369 #ifdef _DEBUG_INSTRUCTION_EXECUTION_\r
 370         DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);\r
 371 #endif\r
 372 \r
 373         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;\r
 374         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = 1;\r
 375         \r
 376         return ERROR_OK;\r
 377 }\r
 378 \r
 379 u32 arm920t_get_ttb(target_t *target)\r
 380 {\r
 381         int retval;\r
 382         u32 ttb = 0x0;\r
 383 \r
 384         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)\r
 385                 return retval;\r
 386 \r
 387         return ttb;\r
 388 }\r
 389 \r
 390 void arm920t_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)\r
 391 {\r
 392         u32 cp15_control;\r
 393 \r
 394         /* read cp15 control register */\r
 395         arm920t_read_cp15_physical(target, 0x2, &cp15_control);\r
 396         jtag_execute_queue();\r
 397                 \r
 398         if (mmu)\r
 399                 cp15_control &= ~0x1U;\r
 400         \r
 401         if (d_u_cache)\r
 402                 cp15_control &= ~0x4U;\r
 403         \r
 404         if (i_cache)\r
 405                 cp15_control &= ~0x1000U;\r
 406 \r
 407         arm920t_write_cp15_physical(target, 0x2, cp15_control);\r
 408 }\r
 409 \r
 410 void arm920t_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)\r
 411 {\r
 412         u32 cp15_control;\r
 413 \r
 414         /* read cp15 control register */\r
 415         arm920t_read_cp15_physical(target, 0x2, &cp15_control);\r
 416         jtag_execute_queue();\r
 417                 \r
 418         if (mmu)\r
 419                 cp15_control |= 0x1U;\r
 420         \r
 421         if (d_u_cache)\r
 422                 cp15_control |= 0x4U;\r
 423         \r
 424         if (i_cache)\r
 425                 cp15_control |= 0x1000U;\r
 426         \r
 427         arm920t_write_cp15_physical(target, 0x2, cp15_control);\r
 428 }\r
 429 \r
 430 void arm920t_post_debug_entry(target_t *target)\r
 431 {\r
 432         u32 cp15c15;\r
 433         armv4_5_common_t *armv4_5 = target->arch_info;\r
 434         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 435         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;\r
 436         arm920t_common_t *arm920t = arm9tdmi->arch_info;\r
 437         \r
 438         /* examine cp15 control reg */\r
 439         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);\r
 440         jtag_execute_queue();\r
 441         DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);\r
 442 \r
 443         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)\r
 444         {\r
 445                 u32 cache_type_reg;\r
 446                 /* identify caches */\r
 447                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);\r
 448                 jtag_execute_queue();\r
 449                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);\r
 450         }\r
 451 \r
 452         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;\r
 453         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;\r
 454         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;\r
 455 \r
 456         /* save i/d fault status and address register */\r
 457         arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);\r
 458         arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);\r
 459         arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);\r
 460         arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);\r
 461         \r
 462         DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",\r
 463                 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);  \r
 464 \r
 465         if (arm920t->preserve_cache)\r
 466         {\r
 467                 /* read-modify-write CP15 test state register \r
 468                  * to disable I/D-cache linefills */\r
 469                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);\r
 470                 jtag_execute_queue();\r
 471                 cp15c15 |= 0x600;\r
 472                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 473         }\r
 474 }\r
 475 \r
 476 void arm920t_pre_restore_context(target_t *target)\r
 477 {\r
 478         u32 cp15c15;\r
 479         armv4_5_common_t *armv4_5 = target->arch_info;\r
 480         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 481         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;\r
 482         arm920t_common_t *arm920t = arm9tdmi->arch_info;\r
 483         \r
 484         /* restore i/d fault status and address register */\r
 485         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);\r
 486         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);\r
 487         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);\r
 488         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);\r
 489         \r
 490         /* read-modify-write CP15 test state register \r
 491         * to reenable I/D-cache linefills */\r
 492         if (arm920t->preserve_cache)\r
 493         {\r
 494                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);\r
 495                 jtag_execute_queue();\r
 496                 cp15c15 &= ~0x600U;\r
 497                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 498         }\r
 499 }\r
 500 \r
 501 int arm920t_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p, arm9tdmi_common_t **arm9tdmi_p, arm920t_common_t **arm920t_p)\r
 502 {\r
 503         armv4_5_common_t *armv4_5 = target->arch_info;\r
 504         arm7_9_common_t *arm7_9;\r
 505         arm9tdmi_common_t *arm9tdmi;\r
 506         arm920t_common_t *arm920t;\r
 507         \r
 508         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)\r
 509         {\r
 510                 return -1;\r
 511         }\r
 512         \r
 513         arm7_9 = armv4_5->arch_info;\r
 514         if (arm7_9->common_magic != ARM7_9_COMMON_MAGIC)\r
 515         {\r
 516                 return -1;\r
 517         }\r
 518         \r
 519         arm9tdmi = arm7_9->arch_info;\r
 520         if (arm9tdmi->common_magic != ARM9TDMI_COMMON_MAGIC)\r
 521         {\r
 522                 return -1;\r
 523         }\r
 524         \r
 525         arm920t = arm9tdmi->arch_info;\r
 526         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)\r
 527         {\r
 528                 return -1;\r
 529         }\r
 530         \r
 531         *armv4_5_p = armv4_5;\r
 532         *arm7_9_p = arm7_9;\r
 533         *arm9tdmi_p = arm9tdmi;\r
 534         *arm920t_p = arm920t;\r
 535         \r
 536         return ERROR_OK;\r
 537 }\r
 538 \r
 539 int arm920t_arch_state(struct target_s *target)\r
 540 {\r
 541         armv4_5_common_t *armv4_5 = target->arch_info;\r
 542         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 543         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;\r
 544         arm920t_common_t *arm920t = arm9tdmi->arch_info;\r
 545         \r
 546         char *state[] = \r
 547         {\r
 548                 "disabled", "enabled"\r
 549         };\r
 550         \r
 551         if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)\r
 552         {\r
 553                 ERROR("BUG: called for a non-ARMv4/5 target");\r
 554                 exit(-1);\r
 555         }\r
 556         \r
 557         USER(   "target halted in %s state due to %s, current mode: %s\n"\r
 558                         "cpsr: 0x%8.8x pc: 0x%8.8x\n"\r
 559                         "MMU: %s, D-Cache: %s, I-Cache: %s",\r
 560                          armv4_5_state_strings[armv4_5->core_state],\r
 561                          target_debug_reason_strings[target->debug_reason],\r
 562                          armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],\r
 563                          buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),\r
 564                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),\r
 565                          state[arm920t->armv4_5_mmu.mmu_enabled],\r
 566                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled], \r
 567                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);\r
 568         \r
 569         return ERROR_OK;\r
 570 }\r
 571 \r
 572 int arm920t_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
 573 {\r
 574         int retval;\r
 575         \r
 576         retval = arm7_9_read_memory(target, address, size, count, buffer);\r
 577         \r
 578         return retval;\r
 579 }\r
 580 \r
 581 int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer)\r
 582 {\r
 583         int retval;\r
 584         armv4_5_common_t *armv4_5 = target->arch_info;\r
 585         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 586         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;\r
 587         arm920t_common_t *arm920t = arm9tdmi->arch_info;\r
 588         \r
 589         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)\r
 590                 return retval;\r
 591 \r
 592         if (((size == 4) || (size == 2)) && (count == 1))\r
 593         {\r
 594                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)\r
 595                 {\r
 596                         DEBUG("D-Cache enabled, writing through to main memory");\r
 597                         u32 pa, cb, ap;\r
 598                         int type, domain;\r
 599 \r
 600                         pa = armv4_5_mmu_translate_va(target, &arm920t->armv4_5_mmu, address, &type, &cb, &domain, &ap);\r
 601                         if (type == -1)\r
 602                                 return ERROR_OK;\r
 603                         /* cacheable & bufferable means write-back region */\r
 604                         if (cb == 3)\r
 605                                 armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, pa, size, count, buffer);\r
 606                 }\r
 607                 \r
 608                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)\r
 609                 {\r
 610                         DEBUG("I-Cache enabled, invalidating affected I-Cache line");\r
 611                         arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);\r
 612                 }\r
 613         }\r
 614 \r
 615         return retval;\r
 616 }\r
 617 \r
 618 int arm920t_soft_reset_halt(struct target_s *target)\r
 619 {\r
 620         armv4_5_common_t *armv4_5 = target->arch_info;\r
 621         arm7_9_common_t *arm7_9 = armv4_5->arch_info;\r
 622         arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;\r
 623         arm920t_common_t *arm920t = arm9tdmi->arch_info;\r
 624         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];\r
 625         \r
 626         if (target->state == TARGET_RUNNING)\r
 627         {\r
 628                 target->type->halt(target);\r
 629         }\r
 630         \r
 631         while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)\r
 632         {\r
 633                 embeddedice_read_reg(dbg_stat);\r
 634                 jtag_execute_queue();\r
 635         }\r
 636         \r
 637         target->state = TARGET_HALTED;\r
 638         \r
 639         /* SVC, ARM state, IRQ and FIQ disabled */\r
 640         buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8, 0xd3);\r
 641         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;\r
 642         armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;\r
 643         \r
 644         /* start fetching from 0x0 */\r
 645         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);\r
 646         armv4_5->core_cache->reg_list[15].dirty = 1;\r
 647         armv4_5->core_cache->reg_list[15].valid = 1;\r
 648         \r
 649         armv4_5->core_mode = ARMV4_5_MODE_SVC;\r
 650         armv4_5->core_state = ARMV4_5_STATE_ARM;\r
 651         \r
 652         arm920t_disable_mmu_caches(target, 1, 1, 1);\r
 653         arm920t->armv4_5_mmu.mmu_enabled = 0;\r
 654         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;\r
 655         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;\r
 656 \r
 657         target_call_event_callbacks(target, TARGET_EVENT_HALTED);\r
 658         \r
 659         return ERROR_OK;\r
 660 }\r
 661 \r
 662 int arm920t_init_target(struct command_context_s *cmd_ctx, struct target_s *target)\r
 663 {\r
 664         arm9tdmi_init_target(cmd_ctx, target);\r
 665                 \r
 666         return ERROR_OK;\r
 667         \r
 668 }\r
 669 \r
 670 int arm920t_quit()\r
 671 {\r
 672         \r
 673         return ERROR_OK;\r
 674 }\r
 675 \r
 676 int arm920t_init_arch_info(target_t *target, arm920t_common_t *arm920t, int chain_pos, char *variant)\r
 677 {\r
 678         arm9tdmi_common_t *arm9tdmi = &arm920t->arm9tdmi_common;\r
 679         arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;\r
 680         \r
 681         /* initialize arm9tdmi specific info (including arm7_9 and armv4_5)\r
 682          */\r
 683         arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);\r
 684 \r
 685         arm9tdmi->arch_info = arm920t;\r
 686         arm920t->common_magic = ARM920T_COMMON_MAGIC;\r
 687         \r
 688         arm7_9->post_debug_entry = arm920t_post_debug_entry;\r
 689         arm7_9->pre_restore_context = arm920t_pre_restore_context;\r
 690         \r
 691         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;\r
 692         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;\r
 693         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;\r
 694         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;\r
 695         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;\r
 696         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;\r
 697         arm920t->armv4_5_mmu.has_tiny_pages = 1;\r
 698         arm920t->armv4_5_mmu.mmu_enabled = 0;\r
 699         \r
 700         /* disabling linefills leads to lockups, so keep them enabled for now\r
 701          * this doesn't affect correctness, but might affect timing issues, if\r
 702          * important data is evicted from the cache during the debug session\r
 703          * */\r
 704         arm920t->preserve_cache = 0;\r
 705         \r
 706         /* override hw single-step capability from ARM9TDMI */\r
 707         arm7_9->has_single_step = 1;\r
 708         \r
 709         return ERROR_OK;\r
 710 }\r
 711 \r
 712 int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)\r
 713 {\r
 714         int chain_pos;\r
 715         char *variant = NULL;\r
 716         arm920t_common_t *arm920t = malloc(sizeof(arm920t_common_t));\r
 717         \r
 718         if (argc < 4)\r
 719         {\r
 720                 ERROR("'target arm920t' requires at least one additional argument");\r
 721                 exit(-1);\r
 722         }\r
 723         \r
 724         chain_pos = strtoul(args[3], NULL, 0);\r
 725         \r
 726         if (argc >= 5)\r
 727                 variant = args[4];\r
 728         \r
 729         DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);\r
 730         \r
 731         arm920t_init_arch_info(target, arm920t, chain_pos, variant);\r
 732 \r
 733         return ERROR_OK;\r
 734 }\r
 735 \r
 736 int arm920t_register_commands(struct command_context_s *cmd_ctx)\r
 737 {\r
 738         int retval;\r
 739         command_t *arm920t_cmd;\r
 740         \r
 741                 \r
 742         retval = arm9tdmi_register_commands(cmd_ctx);\r
 743         \r
 744         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t", NULL, COMMAND_ANY, "arm920t specific commands");\r
 745 \r
 746         register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");\r
 747         register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");\r
 748         register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");\r
 749         register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");\r
 750 \r
 751         register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");\r
 752         register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");\r
 753         register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");\r
 754 \r
 755         register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");\r
 756         register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");\r
 757         register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");\r
 758 \r
 759         register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");\r
 760         register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");\r
 761 \r
 762         return ERROR_OK;\r
 763 }\r
 764 \r
 765 int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
 766 {\r
 767         target_t *target = get_current_target(cmd_ctx);\r
 768         armv4_5_common_t *armv4_5;\r
 769         arm7_9_common_t *arm7_9;\r
 770         arm9tdmi_common_t *arm9tdmi;\r
 771         arm920t_common_t *arm920t;\r
 772         arm_jtag_t *jtag_info;\r
 773         u32 cp15c15;\r
 774         u32 cp15_ctrl, cp15_ctrl_saved;\r
 775         u32 regs[16];\r
 776         u32 *regs_p[16];\r
 777         u32 C15_C_D_Ind, C15_C_I_Ind;\r
 778         int i;\r
 779         FILE *output;\r
 780         arm920t_cache_line_t d_cache[8][64], i_cache[8][64];\r
 781         int segment, index;\r
 782         \r
 783         if (argc != 1)\r
 784         {\r
 785                 command_print(cmd_ctx, "usage: arm920t read_cache <filename>");\r
 786                 return ERROR_OK;\r
 787         }\r
 788         \r
 789         if ((output = fopen(args[0], "w")) == NULL)\r
 790         {\r
 791                 DEBUG("error opening cache content file");\r
 792                 return ERROR_OK;\r
 793         }\r
 794         \r
 795         for (i = 0; i < 16; i++)\r
 796                 regs_p[i] = &regs[i];\r
 797                 \r
 798         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
 799         {\r
 800                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
 801                 return ERROR_OK;\r
 802         }\r
 803         \r
 804         jtag_info = &arm7_9->jtag_info;\r
 805         \r
 806         /* disable MMU and Caches */\r
 807         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);\r
 808         jtag_execute_queue();\r
 809         cp15_ctrl_saved = cp15_ctrl;\r
 810         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);\r
 811         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);\r
 812 \r
 813         /* read CP15 test state register */ \r
 814         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);\r
 815         jtag_execute_queue();\r
 816         \r
 817         /* read DCache content */\r
 818         fprintf(output, "DCache:\n");\r
 819         \r
 820         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ \r
 821         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)\r
 822         {\r
 823                 fprintf(output, "\nsegment: %i\n----------", segment);\r
 824                 \r
 825                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */\r
 826                 regs[0] = 0x0 | (segment << 5);\r
 827                 arm9tdmi_write_core_regs(target, 0x1, regs);\r
 828                 \r
 829                 /* set interpret mode */\r
 830                 cp15c15 |= 0x1;\r
 831                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
 832                 \r
 833                 /* D CAM Read, loads current victim into C15.C.D.Ind */\r
 834                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));\r
 835         \r
 836                 /* read current victim */\r
 837                 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);\r
 838 \r
 839                 /* clear interpret mode */\r
 840                 cp15c15 &= ~0x1;\r
 841                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 842 \r
 843                 for (index = 0; index < 64; index++)\r
 844                 {\r
 845                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */\r
 846                         regs[0] = 0x0 | (segment << 5) | (index << 26);\r
 847                         arm9tdmi_write_core_regs(target, 0x1, regs);\r
 848 \r
 849                         /* set interpret mode */\r
 850                         cp15c15 |= 0x1;\r
 851                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
 852         \r
 853                         /* Write DCache victim */\r
 854                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));\r
 855         \r
 856                         /* Read D RAM */\r
 857                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));\r
 858                         \r
 859                         /* Read D CAM */\r
 860                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));\r
 861                         \r
 862                         /* clear interpret mode */\r
 863                         cp15c15 &= ~0x1;\r
 864                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 865 \r
 866                         /* read D RAM and CAM content */\r
 867                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);\r
 868                         jtag_execute_queue();\r
 869 \r
 870                         d_cache[segment][index].cam = regs[9];\r
 871                         \r
 872                         /* mask LFSR[6] */\r
 873                         regs[9] &= 0xfffffffe;\r
 874                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");\r
 875                         \r
 876                         for (i = 1; i < 9; i++)\r
 877                         {\r
 878                                  d_cache[segment][index].data[i] = regs[i];\r
 879                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);\r
 880                         }\r
 881         \r
 882                 }\r
 883                 \r
 884                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */\r
 885                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);\r
 886                 arm9tdmi_write_core_regs(target, 0x1, regs);\r
 887 \r
 888                 /* set interpret mode */\r
 889                 cp15c15 |= 0x1;\r
 890                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
 891         \r
 892                 /* Write DCache victim */\r
 893                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));\r
 894         \r
 895                 /* clear interpret mode */\r
 896                 cp15c15 &= ~0x1;\r
 897                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 898         }\r
 899 \r
 900         /* read ICache content */\r
 901         fprintf(output, "ICache:\n");\r
 902         \r
 903         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */ \r
 904         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)\r
 905         {\r
 906                 fprintf(output, "segment: %i\n----------", segment);\r
 907                 \r
 908                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */\r
 909                 regs[0] = 0x0 | (segment << 5);\r
 910                 arm9tdmi_write_core_regs(target, 0x1, regs);\r
 911                 \r
 912                 /* set interpret mode */\r
 913                 cp15c15 |= 0x1;\r
 914                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
 915                 \r
 916                 /* I CAM Read, loads current victim into C15.C.I.Ind */\r
 917                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));\r
 918         \r
 919                 /* read current victim */\r
 920                 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);\r
 921 \r
 922                 /* clear interpret mode */\r
 923                 cp15c15 &= ~0x1;\r
 924                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 925 \r
 926                 for (index = 0; index < 64; index++)\r
 927                 {\r
 928                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */\r
 929                         regs[0] = 0x0 | (segment << 5) | (index << 26);\r
 930                         arm9tdmi_write_core_regs(target, 0x1, regs);\r
 931 \r
 932                         /* set interpret mode */\r
 933                         cp15c15 |= 0x1;\r
 934                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
 935         \r
 936                         /* Write ICache victim */\r
 937                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));\r
 938         \r
 939                         /* Read I RAM */\r
 940                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));\r
 941                         \r
 942                         /* Read I CAM */\r
 943                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));\r
 944                         \r
 945                         /* clear interpret mode */\r
 946                         cp15c15 &= ~0x1;\r
 947                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 948 \r
 949                         /* read I RAM and CAM content */\r
 950                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);\r
 951                         jtag_execute_queue();\r
 952 \r
 953                         i_cache[segment][index].cam = regs[9];\r
 954                         \r
 955                         /* mask LFSR[6] */\r
 956                         regs[9] &= 0xfffffffe;\r
 957                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");\r
 958                         \r
 959                         for (i = 1; i < 9; i++)\r
 960                         {\r
 961                                  i_cache[segment][index].data[i] = regs[i];\r
 962                                  fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);\r
 963                         }\r
 964         \r
 965                 }\r
 966                 \r
 967         \r
 968                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */\r
 969                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);\r
 970                 arm9tdmi_write_core_regs(target, 0x1, regs);\r
 971 \r
 972                 /* set interpret mode */\r
 973                 cp15c15 |= 0x1;\r
 974                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
 975         \r
 976                 /* Write ICache victim */\r
 977                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));\r
 978         \r
 979                 /* clear interpret mode */\r
 980                 cp15c15 &= ~0x1;\r
 981                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
 982         }\r
 983         \r
 984         /* restore CP15 MMU and Cache settings */\r
 985         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);\r
 986         \r
 987         command_print(cmd_ctx, "cache content successfully output to %s", args[0]);\r
 988         \r
 989         fclose(output);\r
 990         \r
 991         /* mark registers dirty. */\r
 992         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;\r
 993         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;\r
 994         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;\r
 995         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;\r
 996         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;\r
 997         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;\r
 998         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;\r
 999         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;\r
1000         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;\r
1001         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;\r
1002         \r
1003         return ERROR_OK;\r
1004 }\r
1005 \r
1006 int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
1007 {\r
1008         target_t *target = get_current_target(cmd_ctx);\r
1009         armv4_5_common_t *armv4_5;\r
1010         arm7_9_common_t *arm7_9;\r
1011         arm9tdmi_common_t *arm9tdmi;\r
1012         arm920t_common_t *arm920t;\r
1013         arm_jtag_t *jtag_info;\r
1014         u32 cp15c15;\r
1015         u32 cp15_ctrl, cp15_ctrl_saved;\r
1016         u32 regs[16];\r
1017         u32 *regs_p[16];\r
1018         int i;\r
1019         FILE *output;\r
1020         u32 Dlockdown, Ilockdown;\r
1021         arm920t_tlb_entry_t d_tlb[64], i_tlb[64];\r
1022         int victim;\r
1023         \r
1024         if (argc != 1)\r
1025         {\r
1026                 command_print(cmd_ctx, "usage: arm920t read_mmu <filename>");\r
1027                 return ERROR_OK;\r
1028         }\r
1029         \r
1030         if ((output = fopen(args[0], "w")) == NULL)\r
1031         {\r
1032                 DEBUG("error opening mmu content file");\r
1033                 return ERROR_OK;\r
1034         }\r
1035         \r
1036         for (i = 0; i < 16; i++)\r
1037                 regs_p[i] = &regs[i];\r
1038                 \r
1039         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1040         {\r
1041                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1042                 return ERROR_OK;\r
1043         }\r
1044         \r
1045         jtag_info = &arm7_9->jtag_info;\r
1046         \r
1047         /* disable MMU and Caches */\r
1048         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);\r
1049         jtag_execute_queue();\r
1050         cp15_ctrl_saved = cp15_ctrl;\r
1051         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);\r
1052         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);\r
1053 \r
1054         /* read CP15 test state register */ \r
1055         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);\r
1056         jtag_execute_queue();\r
1057 \r
1058         /* prepare reading D TLB content \r
1059          * */\r
1060         \r
1061         /* set interpret mode */\r
1062         cp15c15 |= 0x1;\r
1063         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
1064         \r
1065         /* Read D TLB lockdown */\r
1066         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));\r
1067         \r
1068         /* clear interpret mode */\r
1069         cp15c15 &= ~0x1;\r
1070         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
1071         \r
1072         /* read D TLB lockdown stored to r1 */\r
1073         arm9tdmi_read_core_regs(target, 0x2, regs_p);\r
1074         jtag_execute_queue();\r
1075         Dlockdown = regs[1];\r
1076         \r
1077         for (victim = 0; victim < 64; victim += 8)\r
1078         {\r
1079                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] \r
1080                  * base remains unchanged, victim goes through entries 0 to 63 */\r
1081                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);\r
1082                 arm9tdmi_write_core_regs(target, 0x2, regs);\r
1083                 \r
1084                 /* set interpret mode */\r
1085                 cp15c15 |= 0x1;\r
1086                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
1087                 \r
1088                 /* Write D TLB lockdown */\r
1089                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));\r
1090         \r
1091                 /* Read D TLB CAM */\r
1092                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));\r
1093                 \r
1094                 /* clear interpret mode */\r
1095                 cp15c15 &= ~0x1;\r
1096                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
1097                 \r
1098                 /* read D TLB CAM content stored to r2-r9 */\r
1099                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);\r
1100                 jtag_execute_queue();\r
1101                 \r
1102                 for (i = 0; i < 8; i++)\r
1103                         d_tlb[victim + i].cam = regs[i + 2]; \r
1104         }\r
1105 \r
1106         for (victim = 0; victim < 64; victim++)\r
1107         {\r
1108                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] \r
1109                  * base remains unchanged, victim goes through entries 0 to 63 */\r
1110                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);\r
1111                 arm9tdmi_write_core_regs(target, 0x2, regs);\r
1112                 \r
1113                 /* set interpret mode */\r
1114                 cp15c15 |= 0x1;\r
1115                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
1116                 \r
1117                 /* Write D TLB lockdown */\r
1118                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));\r
1119         \r
1120                 /* Read D TLB RAM1 */\r
1121                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));\r
1122 \r
1123                 /* Read D TLB RAM2 */\r
1124                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));\r
1125                 \r
1126                 /* clear interpret mode */\r
1127                 cp15c15 &= ~0x1;\r
1128                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
1129                 \r
1130                 /* read D TLB RAM content stored to r2 and r3 */\r
1131                 arm9tdmi_read_core_regs(target, 0xc, regs_p);\r
1132                 jtag_execute_queue();\r
1133 \r
1134                 d_tlb[victim].ram1 = regs[2]; \r
1135                 d_tlb[victim].ram2 = regs[3]; \r
1136         }\r
1137                 \r
1138         /* restore D TLB lockdown */\r
1139         regs[1] = Dlockdown;\r
1140         arm9tdmi_write_core_regs(target, 0x2, regs);\r
1141         \r
1142         /* Write D TLB lockdown */\r
1143         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));\r
1144 \r
1145         /* prepare reading I TLB content \r
1146          * */\r
1147         \r
1148         /* set interpret mode */\r
1149         cp15c15 |= 0x1;\r
1150         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
1151         \r
1152         /* Read I TLB lockdown */\r
1153         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));\r
1154         \r
1155         /* clear interpret mode */\r
1156         cp15c15 &= ~0x1;\r
1157         arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
1158         \r
1159         /* read I TLB lockdown stored to r1 */\r
1160         arm9tdmi_read_core_regs(target, 0x2, regs_p);\r
1161         jtag_execute_queue();\r
1162         Ilockdown = regs[1];\r
1163         \r
1164         for (victim = 0; victim < 64; victim += 8)\r
1165         {\r
1166                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] \r
1167                  * base remains unchanged, victim goes through entries 0 to 63 */\r
1168                 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);\r
1169                 arm9tdmi_write_core_regs(target, 0x2, regs);\r
1170                 \r
1171                 /* set interpret mode */\r
1172                 cp15c15 |= 0x1;\r
1173                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
1174                 \r
1175                 /* Write I TLB lockdown */\r
1176                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));\r
1177         \r
1178                 /* Read I TLB CAM */\r
1179                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));\r
1180                 \r
1181                 /* clear interpret mode */\r
1182                 cp15c15 &= ~0x1;\r
1183                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
1184                 \r
1185                 /* read I TLB CAM content stored to r2-r9 */\r
1186                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);\r
1187                 jtag_execute_queue();\r
1188                 \r
1189                 for (i = 0; i < 8; i++)\r
1190                         i_tlb[i + victim].cam = regs[i + 2]; \r
1191         }\r
1192 \r
1193         for (victim = 0; victim < 64; victim++)\r
1194         {\r
1195                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0] \r
1196                  * base remains unchanged, victim goes through entries 0 to 63 */\r
1197                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);\r
1198                 arm9tdmi_write_core_regs(target, 0x2, regs);\r
1199                 \r
1200                 /* set interpret mode */\r
1201                 cp15c15 |= 0x1;\r
1202                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);\r
1203                 \r
1204                 /* Write I TLB lockdown */\r
1205                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));\r
1206         \r
1207                 /* Read I TLB RAM1 */\r
1208                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));\r
1209 \r
1210                 /* Read I TLB RAM2 */\r
1211                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));\r
1212                 \r
1213                 /* clear interpret mode */\r
1214                 cp15c15 &= ~0x1;\r
1215                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);\r
1216                 \r
1217                 /* read I TLB RAM content stored to r2 and r3 */\r
1218                 arm9tdmi_read_core_regs(target, 0xc, regs_p);\r
1219                 jtag_execute_queue();\r
1220 \r
1221                 i_tlb[victim].ram1 = regs[2]; \r
1222                 i_tlb[victim].ram2 = regs[3]; \r
1223         }\r
1224                 \r
1225         /* restore I TLB lockdown */\r
1226         regs[1] = Ilockdown;\r
1227         arm9tdmi_write_core_regs(target, 0x2, regs);\r
1228         \r
1229         /* Write I TLB lockdown */\r
1230         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));\r
1231         \r
1232         /* restore CP15 MMU and Cache settings */\r
1233         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);\r
1234 \r
1235         /* output data to file */       \r
1236         fprintf(output, "D TLB content:\n");\r
1237         for (i = 0; i < 64; i++)\r
1238         {\r
1239                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");\r
1240         }\r
1241 \r
1242         fprintf(output, "\n\nI TLB content:\n");\r
1243         for (i = 0; i < 64; i++)\r
1244         {\r
1245                 fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");\r
1246         }\r
1247         \r
1248         command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);\r
1249         \r
1250         fclose(output);\r
1251         \r
1252         /* mark registers dirty */\r
1253         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;\r
1254         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 1).valid;\r
1255         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 2).valid;\r
1256         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 3).valid;\r
1257         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 4).valid;\r
1258         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 5).valid;\r
1259         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 6).valid;\r
1260         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 7).valid;\r
1261         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 8).valid;\r
1262         ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 9).valid;\r
1263         \r
1264         return ERROR_OK;\r
1265 }\r
1266 int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
1267 {\r
1268         int retval;\r
1269         target_t *target = get_current_target(cmd_ctx);\r
1270         armv4_5_common_t *armv4_5;\r
1271         arm7_9_common_t *arm7_9;\r
1272         arm9tdmi_common_t *arm9tdmi;\r
1273         arm920t_common_t *arm920t;\r
1274         arm_jtag_t *jtag_info;\r
1275 \r
1276         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1277         {\r
1278                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1279                 return ERROR_OK;\r
1280         }\r
1281         \r
1282         jtag_info = &arm7_9->jtag_info;\r
1283         \r
1284         if (target->state != TARGET_HALTED)\r
1285         {\r
1286                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
1287                 return ERROR_OK;\r
1288         }\r
1289 \r
1290         /* one or more argument, access a single register (write if second argument is given */\r
1291         if (argc >= 1)\r
1292         {\r
1293                 int address = strtoul(args[0], NULL, 0);\r
1294 \r
1295                 if (argc == 1)\r
1296                 {\r
1297                         u32 value;\r
1298                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)\r
1299                         {\r
1300                                 command_print(cmd_ctx, "couldn't access reg %i", address);\r
1301                                 return ERROR_OK;\r
1302                         }\r
1303                         jtag_execute_queue();\r
1304                         \r
1305                         command_print(cmd_ctx, "%i: %8.8x", address, value);\r
1306                 }\r
1307                 else if (argc == 2)\r
1308                 {\r
1309                         u32 value = strtoul(args[1], NULL, 0);\r
1310                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)\r
1311                         {\r
1312                                 command_print(cmd_ctx, "couldn't access reg %i", address);\r
1313                                 return ERROR_OK;\r
1314                         }\r
1315                         command_print(cmd_ctx, "%i: %8.8x", address, value);\r
1316                 }\r
1317         }\r
1318 \r
1319         return ERROR_OK;\r
1320 }\r
1321 \r
1322 int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
1323 {\r
1324         int retval;\r
1325         target_t *target = get_current_target(cmd_ctx);\r
1326         armv4_5_common_t *armv4_5;\r
1327         arm7_9_common_t *arm7_9;\r
1328         arm9tdmi_common_t *arm9tdmi;\r
1329         arm920t_common_t *arm920t;\r
1330         arm_jtag_t *jtag_info;\r
1331 \r
1332         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1333         {\r
1334                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1335                 return ERROR_OK;\r
1336         }\r
1337         \r
1338         jtag_info = &arm7_9->jtag_info;\r
1339         \r
1340         if (target->state != TARGET_HALTED)\r
1341         {\r
1342                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
1343                 return ERROR_OK;\r
1344         }\r
1345 \r
1346         /* one or more argument, access a single register (write if second argument is given */\r
1347         if (argc >= 1)\r
1348         {\r
1349                 u32 opcode = strtoul(args[0], NULL, 0);\r
1350 \r
1351                 if (argc == 1)\r
1352                 {\r
1353                         u32 value;\r
1354                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)\r
1355                         {\r
1356                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);\r
1357                                 return ERROR_OK;\r
1358                         }\r
1359                         \r
1360                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);\r
1361                 }\r
1362                 else if (argc == 2)\r
1363                 {\r
1364                         u32 value = strtoul(args[1], NULL, 0);\r
1365                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)\r
1366                         {\r
1367                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);\r
1368                                 return ERROR_OK;\r
1369                         }\r
1370                         command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);\r
1371                 }\r
1372                 else if (argc == 3)\r
1373                 {\r
1374                         u32 value = strtoul(args[1], NULL, 0);\r
1375                         u32 address = strtoul(args[2], NULL, 0);\r
1376                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)\r
1377                         {\r
1378                                 command_print(cmd_ctx, "couldn't execute %8.8x", opcode);\r
1379                                 return ERROR_OK;\r
1380                         }\r
1381                         command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);\r
1382                 }\r
1383         }\r
1384         else\r
1385         {\r
1386                 command_print(cmd_ctx, "usage: arm920t cp15i <opcode> [value] [address]");\r
1387         }\r
1388 \r
1389         return ERROR_OK;\r
1390 }\r
1391 \r
1392 int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)\r
1393 {\r
1394         target_t *target = get_current_target(cmd_ctx);\r
1395         armv4_5_common_t *armv4_5;\r
1396         arm7_9_common_t *arm7_9;\r
1397         arm9tdmi_common_t *arm9tdmi;\r
1398         arm920t_common_t *arm920t;\r
1399         \r
1400         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1401         {\r
1402                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1403                 return ERROR_OK;\r
1404         }\r
1405         \r
1406         return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);\r
1407 }\r
1408 \r
1409 int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
1410 {       \r
1411         target_t *target = get_current_target(cmd_ctx);\r
1412         armv4_5_common_t *armv4_5;\r
1413         arm7_9_common_t *arm7_9;\r
1414         arm9tdmi_common_t *arm9tdmi;\r
1415         arm920t_common_t *arm920t;\r
1416         arm_jtag_t *jtag_info;\r
1417 \r
1418         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1419         {\r
1420                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1421                 return ERROR_OK;\r
1422         }\r
1423         \r
1424         jtag_info = &arm7_9->jtag_info;\r
1425         \r
1426         if (target->state != TARGET_HALTED)\r
1427         {\r
1428                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
1429                 return ERROR_OK;\r
1430         }\r
1431                 \r
1432         return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);\r
1433 }\r
1434 \r
1435 int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
1436 {       \r
1437         target_t *target = get_current_target(cmd_ctx);\r
1438         armv4_5_common_t *armv4_5;\r
1439         arm7_9_common_t *arm7_9;\r
1440         arm9tdmi_common_t *arm9tdmi;\r
1441         arm920t_common_t *arm920t;\r
1442         arm_jtag_t *jtag_info;\r
1443 \r
1444         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1445         {\r
1446                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1447                 return ERROR_OK;\r
1448         }\r
1449         \r
1450         jtag_info = &arm7_9->jtag_info;\r
1451         \r
1452         if (target->state != TARGET_HALTED)\r
1453         {\r
1454                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
1455                 return ERROR_OK;\r
1456         }\r
1457         \r
1458         return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);\r
1459 }\r
1460 \r
1461 int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)\r
1462 {       \r
1463         target_t *target = get_current_target(cmd_ctx);\r
1464         armv4_5_common_t *armv4_5;\r
1465         arm7_9_common_t *arm7_9;\r
1466         arm9tdmi_common_t *arm9tdmi;\r
1467         arm920t_common_t *arm920t;\r
1468         arm_jtag_t *jtag_info;\r
1469 \r
1470         if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)\r
1471         {\r
1472                 command_print(cmd_ctx, "current target isn't an ARM920t target");\r
1473                 return ERROR_OK;\r
1474         }\r
1475         \r
1476         jtag_info = &arm7_9->jtag_info;\r
1477         \r
1478         if (target->state != TARGET_HALTED)\r
1479         {\r
1480                 command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);\r
1481                 return ERROR_OK;\r
1482         }\r
1483         \r
1484         return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);\r
1485 }\r