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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "arm920t.h"
  25 #include "time_support.h"
  26 #include "target_type.h"
  27 #include "register.h"
  28
  29
  30 /*
  31  * For information about the ARM920T, see ARM DDI 0151C especially
  32  * Chapter 9 about debug support, which shows how to manipulate each
  33  * of the different scan chains:
  34  *
  35  *   0 ... ARM920 signals, e.g. to rest of SOC (unused here)
  36  *   1 ... debugging; watchpoint and breakpoint status, etc; also
  37  *      MMU and cache access in conjunction with scan chain 15
  38  *   2 ... EmbeddedICE
  39  *   3 ... external boundary scan (SoC-specific, unused here)
  40  *   4 ... access to cache tag RAM
  41  *   6 ... ETM9
  42  *   15 ... access coprocessor 15, "physical" or "interpreted" modes
  43  *      "interpreted" works with a few actual MRC/MCR instructions
  44  *      "physical" provides register-like behaviors.
  45  *
  46  * The ARM922T is similar, but with smaller caches (8K each, vs 16K).
  47  */
  48
  49 #if 0
  50 #define _DEBUG_INSTRUCTION_EXECUTION_
  51 #endif
  52
  53 #define ARM920T_CP15_PHYS_ADDR(x, y, z) ((x << 5) | (y << 1) << (z))
  54
  55 static int arm920t_read_cp15_physical(struct target *target,
  56                 int reg_addr, uint32_t *value)
  57 {
  58         struct arm920t_common *arm920t = target_to_arm920(target);
  59         struct arm_jtag *jtag_info;
  60         struct scan_field fields[4];
  61         uint8_t access_type_buf = 1;
  62         uint8_t reg_addr_buf = reg_addr & 0x3f;
  63         uint8_t nr_w_buf = 0;
  64
  65         jtag_info = &arm920t->arm7_9_common.jtag_info;
  66
  67         jtag_set_end_state(TAP_IDLE);
  68         arm_jtag_scann(jtag_info, 0xf);
  69         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
  70
  71         fields[0].tap = jtag_info->tap;
  72         fields[0].num_bits = 1;
  73         fields[0].out_value = &access_type_buf;
  74         fields[0].in_value = NULL;
  75
  76         fields[1].tap = jtag_info->tap;
  77         fields[1].num_bits = 32;
  78         fields[1].out_value = NULL;
  79         fields[1].in_value = NULL;
  80
  81         fields[2].tap = jtag_info->tap;
  82         fields[2].num_bits = 6;
  83         fields[2].out_value = &reg_addr_buf;
  84         fields[2].in_value = NULL;
  85
  86         fields[3].tap = jtag_info->tap;
  87         fields[3].num_bits = 1;
  88         fields[3].out_value = &nr_w_buf;
  89         fields[3].in_value = NULL;
  90
  91         jtag_add_dr_scan(4, fields, jtag_get_end_state());
  92
  93         fields[1].in_value = (uint8_t *)value;
  94
  95         jtag_add_dr_scan(4, fields, jtag_get_end_state());
  96
  97         jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
  98
  99 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 100         jtag_execute_queue();
 101         LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
 102 #endif
 103
 104         return ERROR_OK;
 105 }
 106
 107 static int arm920t_write_cp15_physical(struct target *target,
 108                 int reg_addr, uint32_t value)
 109 {
 110         struct arm920t_common *arm920t = target_to_arm920(target);
 111         struct arm_jtag *jtag_info;
 112         struct scan_field fields[4];
 113         uint8_t access_type_buf = 1;
 114         uint8_t reg_addr_buf = reg_addr & 0x3f;
 115         uint8_t nr_w_buf = 1;
 116         uint8_t value_buf[4];
 117
 118         jtag_info = &arm920t->arm7_9_common.jtag_info;
 119
 120         buf_set_u32(value_buf, 0, 32, value);
 121
 122         jtag_set_end_state(TAP_IDLE);
 123         arm_jtag_scann(jtag_info, 0xf);
 124         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 125
 126         fields[0].tap = jtag_info->tap;
 127         fields[0].num_bits = 1;
 128         fields[0].out_value = &access_type_buf;
 129         fields[0].in_value = NULL;
 130
 131         fields[1].tap = jtag_info->tap;
 132         fields[1].num_bits = 32;
 133         fields[1].out_value = value_buf;
 134         fields[1].in_value = NULL;
 135
 136         fields[2].tap = jtag_info->tap;
 137         fields[2].num_bits = 6;
 138         fields[2].out_value = &reg_addr_buf;
 139         fields[2].in_value = NULL;
 140
 141         fields[3].tap = jtag_info->tap;
 142         fields[3].num_bits = 1;
 143         fields[3].out_value = &nr_w_buf;
 144         fields[3].in_value = NULL;
 145
 146         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 147
 148 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 149         LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
 150 #endif
 151
 152         return ERROR_OK;
 153 }
 154
 155 static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 156                 uint32_t arm_opcode)
 157 {
 158         int retval;
 159         struct arm920t_common *arm920t = target_to_arm920(target);
 160         struct arm_jtag *jtag_info;
 161         struct scan_field fields[4];
 162         uint8_t access_type_buf = 0;            /* interpreted access */
 163         uint8_t reg_addr_buf = 0x0;
 164         uint8_t nr_w_buf = 0;
 165         uint8_t cp15_opcode_buf[4];
 166
 167         jtag_info = &arm920t->arm7_9_common.jtag_info;
 168
 169         jtag_set_end_state(TAP_IDLE);
 170         arm_jtag_scann(jtag_info, 0xf);
 171         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 172
 173         buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 174
 175         fields[0].tap = jtag_info->tap;
 176         fields[0].num_bits = 1;
 177         fields[0].out_value = &access_type_buf;
 178         fields[0].in_value = NULL;
 179
 180         fields[1].tap = jtag_info->tap;
 181         fields[1].num_bits = 32;
 182         fields[1].out_value = cp15_opcode_buf;
 183         fields[1].in_value = NULL;
 184
 185         fields[2].tap = jtag_info->tap;
 186         fields[2].num_bits = 6;
 187         fields[2].out_value = &reg_addr_buf;
 188         fields[2].in_value = NULL;
 189
 190         fields[3].tap = jtag_info->tap;
 191         fields[3].num_bits = 1;
 192         fields[3].out_value = &nr_w_buf;
 193         fields[3].in_value = NULL;
 194
 195         jtag_add_dr_scan(4, fields, jtag_get_end_state());
 196
 197         arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 198         arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
 199         retval = arm7_9_execute_sys_speed(target);
 200         if (retval != ERROR_OK)
 201                 return retval;
 202
 203         if ((retval = jtag_execute_queue()) != ERROR_OK)
 204         {
 205                 LOG_ERROR("failed executing JTAG queue");
 206                 return retval;
 207         }
 208
 209         return ERROR_OK;
 210 }
 211
 212 static int arm920t_read_cp15_interpreted(struct target *target,
 213                 uint32_t cp15_opcode, uint32_t address, uint32_t *value)
 214 {
 215         struct arm *armv4_5 = target_to_armv4_5(target);
 216         uint32_t* regs_p[1];
 217         uint32_t regs[2];
 218         uint32_t cp15c15 = 0x0;
 219         struct reg *r = armv4_5->core_cache->reg_list;
 220
 221         /* load address into R1 */
 222         regs[1] = address;
 223         arm9tdmi_write_core_regs(target, 0x2, regs);
 224
 225         /* read-modify-write CP15 test state register
 226         * to enable interpreted access mode */
 227         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 228         jtag_execute_queue();
 229         cp15c15 |= 1;   /* set interpret mode */
 230         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 231
 232         /* execute CP15 instruction and ARM load (reading from coprocessor) */
 233         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_LDR(0, 1));
 234
 235         /* disable interpreted access mode */
 236         cp15c15 &= ~1U; /* clear interpret mode */
 237         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 238
 239         /* retrieve value from R0 */
 240         regs_p[0] = value;
 241         arm9tdmi_read_core_regs(target, 0x1, regs_p);
 242         jtag_execute_queue();
 243
 244 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 245         LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
 246 #endif
 247
 248         if (!is_arm_mode(armv4_5->core_mode))
 249                 return ERROR_FAIL;
 250
 251         r[0].dirty = 1;
 252         r[1].dirty = 1;
 253
 254         return ERROR_OK;
 255 }
 256
 257 static
 258 int arm920t_write_cp15_interpreted(struct target *target,
 259                 uint32_t cp15_opcode, uint32_t value, uint32_t address)
 260 {
 261         uint32_t cp15c15 = 0x0;
 262         struct arm *armv4_5 = target_to_armv4_5(target);
 263         uint32_t regs[2];
 264         struct reg *r = armv4_5->core_cache->reg_list;
 265
 266         /* load value, address into R0, R1 */
 267         regs[0] = value;
 268         regs[1] = address;
 269         arm9tdmi_write_core_regs(target, 0x3, regs);
 270
 271         /* read-modify-write CP15 test state register
 272         * to enable interpreted access mode */
 273         arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 274         jtag_execute_queue();
 275         cp15c15 |= 1;   /* set interpret mode */
 276         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 277
 278         /* execute CP15 instruction and ARM store (writing to coprocessor) */
 279         arm920t_execute_cp15(target, cp15_opcode, ARMV4_5_STR(0, 1));
 280
 281         /* disable interpreted access mode */
 282         cp15c15 &= ~1U; /* set interpret mode */
 283         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 284
 285 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 286         LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
 287 #endif
 288
 289         if (!is_arm_mode(armv4_5->core_mode))
 290                 return ERROR_FAIL;
 291
 292         r[0].dirty = 1;
 293         r[1].dirty = 1;
 294
 295         return ERROR_OK;
 296 }
 297
 298 // EXPORTED to FA256
 299 uint32_t arm920t_get_ttb(struct target *target)
 300 {
 301         int retval;
 302         uint32_t ttb = 0x0;
 303
 304         if ((retval = arm920t_read_cp15_interpreted(target, 0xeebf0f51, 0x0, &ttb)) != ERROR_OK)
 305                 return retval;
 306
 307         return ttb;
 308 }
 309
 310 // EXPORTED to FA256
 311 void arm920t_disable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
 312 {
 313         uint32_t cp15_control;
 314
 315         /* read cp15 control register */
 316         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 317         jtag_execute_queue();
 318
 319         if (mmu)
 320                 cp15_control &= ~0x1U;
 321
 322         if (d_u_cache)
 323                 cp15_control &= ~0x4U;
 324
 325         if (i_cache)
 326                 cp15_control &= ~0x1000U;
 327
 328         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 329 }
 330
 331 // EXPORTED to FA256
 332 void arm920t_enable_mmu_caches(struct target *target, int mmu, int d_u_cache, int i_cache)
 333 {
 334         uint32_t cp15_control;
 335
 336         /* read cp15 control register */
 337         arm920t_read_cp15_physical(target, 0x2, &cp15_control);
 338         jtag_execute_queue();
 339
 340         if (mmu)
 341                 cp15_control |= 0x1U;
 342
 343         if (d_u_cache)
 344                 cp15_control |= 0x4U;
 345
 346         if (i_cache)
 347                 cp15_control |= 0x1000U;
 348
 349         arm920t_write_cp15_physical(target, 0x2, cp15_control);
 350 }
 351
 352 // EXPORTED to FA256
 353 void arm920t_post_debug_entry(struct target *target)
 354 {
 355         uint32_t cp15c15;
 356         struct arm920t_common *arm920t = target_to_arm920(target);
 357
 358         /* examine cp15 control reg */
 359         arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 360         jtag_execute_queue();
 361         LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
 362
 363         if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 364         {
 365                 uint32_t cache_type_reg;
 366                 /* identify caches */
 367                 arm920t_read_cp15_physical(target, 0x1, &cache_type_reg);
 368                 jtag_execute_queue();
 369                 armv4_5_identify_cache(cache_type_reg, &arm920t->armv4_5_mmu.armv4_5_cache);
 370         }
 371
 372         arm920t->armv4_5_mmu.mmu_enabled = (arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
 373         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 374         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
 375
 376         /* save i/d fault status and address register */
 377         arm920t_read_cp15_interpreted(target, 0xee150f10, 0x0, &arm920t->d_fsr);
 378         arm920t_read_cp15_interpreted(target, 0xee150f30, 0x0, &arm920t->i_fsr);
 379         arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 380         arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 381
 382         LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
 383                 arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 384
 385         if (arm920t->preserve_cache)
 386         {
 387                 /* read-modify-write CP15 test state register
 388                  * to disable I/D-cache linefills */
 389                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 390                 jtag_execute_queue();
 391                 cp15c15 |= 0x600;
 392                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 393         }
 394 }
 395
 396 // EXPORTED to FA256
 397 void arm920t_pre_restore_context(struct target *target)
 398 {
 399         uint32_t cp15c15;
 400         struct arm920t_common *arm920t = target_to_arm920(target);
 401
 402         /* restore i/d fault status and address register */
 403         arm920t_write_cp15_interpreted(target, 0xee050f10, arm920t->d_fsr, 0x0);
 404         arm920t_write_cp15_interpreted(target, 0xee050f30, arm920t->i_fsr, 0x0);
 405         arm920t_write_cp15_interpreted(target, 0xee060f10, arm920t->d_far, 0x0);
 406         arm920t_write_cp15_interpreted(target, 0xee060f30, arm920t->i_far, 0x0);
 407
 408         /* read-modify-write CP15 test state register
 409         * to reenable I/D-cache linefills */
 410         if (arm920t->preserve_cache)
 411         {
 412                 arm920t_read_cp15_physical(target, 0x1e, &cp15c15);
 413                 jtag_execute_queue();
 414                 cp15c15 &= ~0x600U;
 415                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 416         }
 417 }
 418
 419 static const char arm920_not[] = "target is not an ARM920";
 420
 421 static int arm920t_verify_pointer(struct command_context *cmd_ctx,
 422                 struct arm920t_common *arm920t)
 423 {
 424         if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
 425                 command_print(cmd_ctx, arm920_not);
 426                 return ERROR_TARGET_INVALID;
 427         }
 428
 429         return ERROR_OK;
 430 }
 431
 432 /** Logs summary of ARM920 state for a halted target. */
 433 int arm920t_arch_state(struct target *target)
 434 {
 435         static const char *state[] =
 436         {
 437                 "disabled", "enabled"
 438         };
 439
 440         struct arm920t_common *arm920t = target_to_arm920(target);
 441         struct arm *armv4_5;
 442
 443         if (arm920t->common_magic != ARM920T_COMMON_MAGIC)
 444         {
 445                 LOG_ERROR("BUG: %s", arm920_not);
 446                 return ERROR_TARGET_INVALID;
 447         }
 448
 449         armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
 450
 451         LOG_USER("target halted in %s state due to %s, current mode: %s\n"
 452                         "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 453                         "MMU: %s, D-Cache: %s, I-Cache: %s",
 454                          armv4_5_state_strings[armv4_5->core_state],
 455                          Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
 456                          arm_mode_name(armv4_5->core_mode),
 457                          buf_get_u32(armv4_5->cpsr->value, 0, 32),
 458                          buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
 459                          state[arm920t->armv4_5_mmu.mmu_enabled],
 460                          state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 461                          state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
 462
 463         return ERROR_OK;
 464 }
 465
 466 static int arm920_mmu(struct target *target, int *enabled)
 467 {
 468         if (target->state != TARGET_HALTED) {
 469                 LOG_ERROR("%s: target not halted", __func__);
 470                 return ERROR_TARGET_INVALID;
 471         }
 472
 473         *enabled = target_to_arm920(target)->armv4_5_mmu.mmu_enabled;
 474         return ERROR_OK;
 475 }
 476
 477 static int arm920_virt2phys(struct target *target,
 478                 uint32_t virt, uint32_t *phys)
 479 {
 480         /** @todo Implement this!  */
 481         LOG_ERROR("%s: not implemented", __func__);
 482         return ERROR_FAIL;
 483 }
 484
 485 /** Reads a buffer, in the specified word size, with current MMU settings. */
 486 int arm920t_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 487 {
 488         int retval;
 489
 490         retval = arm7_9_read_memory(target, address, size, count, buffer);
 491
 492         return retval;
 493 }
 494
 495
 496 static int arm920t_read_phys_memory(struct target *target,
 497                 uint32_t address, uint32_t size,
 498                 uint32_t count, uint8_t *buffer)
 499 {
 500         struct arm920t_common *arm920t = target_to_arm920(target);
 501
 502         return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu,
 503                         address, size, count, buffer);
 504 }
 505
 506 static int arm920t_write_phys_memory(struct target *target,
 507                 uint32_t address, uint32_t size,
 508                 uint32_t count, uint8_t *buffer)
 509 {
 510         struct arm920t_common *arm920t = target_to_arm920(target);
 511
 512         return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu,
 513                         address, size, count, buffer);
 514 }
 515
 516
 517 /** Writes a buffer, in the specified word size, with current MMU settings. */
 518 int arm920t_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
 519 {
 520         int retval;
 521
 522         if ((retval = arm7_9_write_memory(target, address, size, count, buffer)) != ERROR_OK)
 523                 return retval;
 524
 525         /* This fn is used to write breakpoints, so we need to make sure
 526          * that the data cache is flushed and the instruction cache is
 527          * invalidated
 528          */
 529         if (((size == 4) || (size == 2)) && (count == 1))
 530         {
 531                 struct arm920t_common *arm920t = target_to_arm920(target);
 532
 533                 if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
 534                 {
 535                         LOG_DEBUG("D-Cache enabled, flush and invalidate cache line");
 536                         /* MCR p15,0,Rd,c7,c10,2 */
 537                         retval = arm920t_write_cp15_interpreted(target, 0xee070f5e, 0x0, address);
 538                         if (retval != ERROR_OK)
 539                                 return retval;
 540                 }
 541
 542                 if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
 543                 {
 544                         LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
 545                         retval = arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
 546                         if (retval != ERROR_OK)
 547                                 return retval;
 548                 }
 549         }
 550
 551         return retval;
 552 }
 553
 554 // EXPORTED to FA256
 555 int arm920t_soft_reset_halt(struct target *target)
 556 {
 557         int retval = ERROR_OK;
 558         struct arm920t_common *arm920t = target_to_arm920(target);
 559         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 560         struct arm *armv4_5 = &arm7_9->armv4_5_common;
 561         struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 562
 563         if ((retval = target_halt(target)) != ERROR_OK)
 564         {
 565                 return retval;
 566         }
 567
 568         long long then = timeval_ms();
 569         int timeout;
 570         while (!(timeout = ((timeval_ms()-then) > 1000)))
 571         {
 572                 if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
 573                 {
 574                         embeddedice_read_reg(dbg_stat);
 575                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 576                         {
 577                                 return retval;
 578                         }
 579                 } else
 580                 {
 581                         break;
 582                 }
 583                 if (debug_level >= 3)
 584                 {
 585                         /* do not eat all CPU, time out after 1 se*/
 586                         alive_sleep(100);
 587                 } else
 588                 {
 589                         keep_alive();
 590                 }
 591         }
 592         if (timeout)
 593         {
 594                 LOG_ERROR("Failed to halt CPU after 1 sec");
 595                 return ERROR_TARGET_TIMEOUT;
 596         }
 597
 598         target->state = TARGET_HALTED;
 599
 600         /* SVC, ARM state, IRQ and FIQ disabled */
 601         uint32_t cpsr;
 602
 603         cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32);
 604         cpsr &= ~0xff;
 605         cpsr |= 0xd3;
 606         arm_set_cpsr(armv4_5, cpsr);
 607         armv4_5->cpsr->dirty = 1;
 608
 609         /* start fetching from 0x0 */
 610         buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, 0x0);
 611         armv4_5->core_cache->reg_list[15].dirty = 1;
 612         armv4_5->core_cache->reg_list[15].valid = 1;
 613
 614         arm920t_disable_mmu_caches(target, 1, 1, 1);
 615         arm920t->armv4_5_mmu.mmu_enabled = 0;
 616         arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 617         arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 618
 619         if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
 620         {
 621                 return retval;
 622         }
 623
 624         return ERROR_OK;
 625 }
 626
 627 int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap)
 628 {
 629         struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common;
 630
 631         /* initialize arm7/arm9 specific info (including armv4_5) */
 632         arm9tdmi_init_arch_info(target, arm7_9, tap);
 633
 634         arm920t->common_magic = ARM920T_COMMON_MAGIC;
 635
 636         arm7_9->post_debug_entry = arm920t_post_debug_entry;
 637         arm7_9->pre_restore_context = arm920t_pre_restore_context;
 638
 639         arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1;
 640         arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb;
 641         arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory;
 642         arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory;
 643         arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 644         arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 645         arm920t->armv4_5_mmu.has_tiny_pages = 1;
 646         arm920t->armv4_5_mmu.mmu_enabled = 0;
 647
 648         /* disabling linefills leads to lockups, so keep them enabled for now
 649          * this doesn't affect correctness, but might affect timing issues, if
 650          * important data is evicted from the cache during the debug session
 651          * */
 652         arm920t->preserve_cache = 0;
 653
 654         /* override hw single-step capability from ARM9TDMI */
 655         arm7_9->has_single_step = 1;
 656
 657         return ERROR_OK;
 658 }
 659
 660 static int arm920t_target_create(struct target *target, Jim_Interp *interp)
 661 {
 662         struct arm920t_common *arm920t = calloc(1,sizeof(struct arm920t_common));
 663
 664         return arm920t_init_arch_info(target, arm920t, target->tap);
 665 }
 666
 667 COMMAND_HANDLER(arm920t_handle_read_cache_command)
 668 {
 669         int retval = ERROR_OK;
 670         struct target *target = get_current_target(CMD_CTX);
 671         struct arm920t_common *arm920t = target_to_arm920(target);
 672         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 673         struct arm *armv4_5 = &arm7_9->armv4_5_common;
 674         uint32_t cp15c15;
 675         uint32_t cp15_ctrl, cp15_ctrl_saved;
 676         uint32_t regs[16];
 677         uint32_t *regs_p[16];
 678         uint32_t C15_C_D_Ind, C15_C_I_Ind;
 679         int i;
 680         FILE *output;
 681         struct arm920t_cache_line d_cache[8][64], i_cache[8][64];
 682         int segment, index;
 683         struct reg *r;
 684
 685         retval = arm920t_verify_pointer(CMD_CTX, arm920t);
 686         if (retval != ERROR_OK)
 687                 return retval;
 688
 689         if (CMD_ARGC != 1)
 690         {
 691                 command_print(CMD_CTX, "usage: arm920t read_cache <filename>");
 692                 return ERROR_OK;
 693         }
 694
 695         if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
 696         {
 697                 LOG_DEBUG("error opening cache content file");
 698                 return ERROR_OK;
 699         }
 700
 701         for (i = 0; i < 16; i++)
 702                 regs_p[i] = &regs[i];
 703
 704         /* disable MMU and Caches */
 705         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
 706         if ((retval = jtag_execute_queue()) != ERROR_OK)
 707         {
 708                 return retval;
 709         }
 710         cp15_ctrl_saved = cp15_ctrl;
 711         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 712         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 713
 714         /* read CP15 test state register */
 715         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
 716         jtag_execute_queue();
 717
 718         /* read DCache content */
 719         fprintf(output, "DCache:\n");
 720
 721         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 722         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 723         {
 724                 fprintf(output, "\nsegment: %i\n----------", segment);
 725
 726                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 727                 regs[0] = 0x0 | (segment << 5);
 728                 arm9tdmi_write_core_regs(target, 0x1, regs);
 729
 730                 /* set interpret mode */
 731                 cp15c15 |= 0x1;
 732                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 733
 734                 /* D CAM Read, loads current victim into C15.C.D.Ind */
 735                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(1, 0));
 736
 737                 /* read current victim */
 738                 arm920t_read_cp15_physical(target, 0x3d, &C15_C_D_Ind);
 739
 740                 /* clear interpret mode */
 741                 cp15c15 &= ~0x1;
 742                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 743
 744                 for (index = 0; index < 64; index++)
 745                 {
 746                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 747                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 748                         arm9tdmi_write_core_regs(target, 0x1, regs);
 749
 750                         /* set interpret mode */
 751                         cp15c15 |= 0x1;
 752                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 753
 754                         /* Write DCache victim */
 755                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 756
 757                         /* Read D RAM */
 758                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,10,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 759
 760                         /* Read D CAM */
 761                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,6,2), ARMV4_5_LDR(9, 0));
 762
 763                         /* clear interpret mode */
 764                         cp15c15 &= ~0x1;
 765                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 766
 767                         /* read D RAM and CAM content */
 768                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 769                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 770                         {
 771                                 return retval;
 772                         }
 773
 774                         d_cache[segment][index].cam = regs[9];
 775
 776                         /* mask LFSR[6] */
 777                         regs[9] &= 0xfffffffe;
 778                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 779
 780                         for (i = 1; i < 9; i++)
 781                         {
 782                                  d_cache[segment][index].data[i] = regs[i];
 783                                  fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
 784                         }
 785
 786                 }
 787
 788                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 789                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 790                 arm9tdmi_write_core_regs(target, 0x1, regs);
 791
 792                 /* set interpret mode */
 793                 cp15c15 |= 0x1;
 794                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 795
 796                 /* Write DCache victim */
 797                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,0), ARMV4_5_LDR(1, 0));
 798
 799                 /* clear interpret mode */
 800                 cp15c15 &= ~0x1;
 801                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 802         }
 803
 804         /* read ICache content */
 805         fprintf(output, "ICache:\n");
 806
 807         /* go through segments 0 to nsets (8 on ARM920T, 4 on ARM922T) */
 808         for (segment = 0; segment < arm920t->armv4_5_mmu.armv4_5_cache.d_u_size.nsets; segment++)
 809         {
 810                 fprintf(output, "segment: %i\n----------", segment);
 811
 812                 /* Ra: r0 = SBZ(31:8):segment(7:5):SBZ(4:0) */
 813                 regs[0] = 0x0 | (segment << 5);
 814                 arm9tdmi_write_core_regs(target, 0x1, regs);
 815
 816                 /* set interpret mode */
 817                 cp15c15 |= 0x1;
 818                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 819
 820                 /* I CAM Read, loads current victim into C15.C.I.Ind */
 821                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(1, 0));
 822
 823                 /* read current victim */
 824                 arm920t_read_cp15_physical(target, 0x3b, &C15_C_I_Ind);
 825
 826                 /* clear interpret mode */
 827                 cp15c15 &= ~0x1;
 828                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 829
 830                 for (index = 0; index < 64; index++)
 831                 {
 832                         /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 833                         regs[0] = 0x0 | (segment << 5) | (index << 26);
 834                         arm9tdmi_write_core_regs(target, 0x1, regs);
 835
 836                         /* set interpret mode */
 837                         cp15c15 |= 0x1;
 838                         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 839
 840                         /* Write ICache victim */
 841                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 842
 843                         /* Read I RAM */
 844                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,9,2), ARMV4_5_LDMIA(0, 0x1fe, 0, 0));
 845
 846                         /* Read I CAM */
 847                         arm920t_execute_cp15(target, ARMV4_5_MCR(15,2,0,15,5,2), ARMV4_5_LDR(9, 0));
 848
 849                         /* clear interpret mode */
 850                         cp15c15 &= ~0x1;
 851                         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 852
 853                         /* read I RAM and CAM content */
 854                         arm9tdmi_read_core_regs(target, 0x3fe, regs_p);
 855                         if ((retval = jtag_execute_queue()) != ERROR_OK)
 856                         {
 857                                 return retval;
 858                         }
 859
 860                         i_cache[segment][index].cam = regs[9];
 861
 862                         /* mask LFSR[6] */
 863                         regs[9] &= 0xfffffffe;
 864                         fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 865
 866                         for (i = 1; i < 9; i++)
 867                         {
 868                                  i_cache[segment][index].data[i] = regs[i];
 869                                  fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
 870                         }
 871                 }
 872
 873                 /* Ra: r0 = index(31:26):SBZ(25:8):segment(7:5):SBZ(4:0) */
 874                 regs[0] = 0x0 | (segment << 5) | (C15_C_D_Ind << 26);
 875                 arm9tdmi_write_core_regs(target, 0x1, regs);
 876
 877                 /* set interpret mode */
 878                 cp15c15 |= 0x1;
 879                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 880
 881                 /* Write ICache victim */
 882                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,9,1,1), ARMV4_5_LDR(1, 0));
 883
 884                 /* clear interpret mode */
 885                 cp15c15 &= ~0x1;
 886                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 887         }
 888
 889         /* restore CP15 MMU and Cache settings */
 890         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
 891
 892         command_print(CMD_CTX, "cache content successfully output to %s", CMD_ARGV[0]);
 893
 894         fclose(output);
 895
 896         if (!is_arm_mode(armv4_5->core_mode))
 897                 return ERROR_FAIL;
 898
 899         /* force writeback of the valid data */
 900         r = armv4_5->core_cache->reg_list;
 901         r[0].dirty = r[0].valid;
 902         r[1].dirty = r[1].valid;
 903         r[2].dirty = r[2].valid;
 904         r[3].dirty = r[3].valid;
 905         r[4].dirty = r[4].valid;
 906         r[5].dirty = r[5].valid;
 907         r[6].dirty = r[6].valid;
 908         r[7].dirty = r[7].valid;
 909
 910         r = arm_reg_current(armv4_5, 8);
 911         r->dirty = r->valid;
 912
 913         r = arm_reg_current(armv4_5, 9);
 914         r->dirty = r->valid;
 915
 916         return ERROR_OK;
 917 }
 918
 919 COMMAND_HANDLER(arm920t_handle_read_mmu_command)
 920 {
 921         int retval = ERROR_OK;
 922         struct target *target = get_current_target(CMD_CTX);
 923         struct arm920t_common *arm920t = target_to_arm920(target);
 924         struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 925         struct arm *armv4_5 = &arm7_9->armv4_5_common;
 926         uint32_t cp15c15;
 927         uint32_t cp15_ctrl, cp15_ctrl_saved;
 928         uint32_t regs[16];
 929         uint32_t *regs_p[16];
 930         int i;
 931         FILE *output;
 932         uint32_t Dlockdown, Ilockdown;
 933         struct arm920t_tlb_entry d_tlb[64], i_tlb[64];
 934         int victim;
 935         struct reg *r;
 936
 937         retval = arm920t_verify_pointer(CMD_CTX, arm920t);
 938         if (retval != ERROR_OK)
 939                 return retval;
 940
 941         if (CMD_ARGC != 1)
 942         {
 943                 command_print(CMD_CTX, "usage: arm920t read_mmu <filename>");
 944                 return ERROR_OK;
 945         }
 946
 947         if ((output = fopen(CMD_ARGV[0], "w")) == NULL)
 948         {
 949                 LOG_DEBUG("error opening mmu content file");
 950                 return ERROR_OK;
 951         }
 952
 953         for (i = 0; i < 16; i++)
 954                 regs_p[i] = &regs[i];
 955
 956         /* disable MMU and Caches */
 957         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), &cp15_ctrl);
 958         if ((retval = jtag_execute_queue()) != ERROR_OK)
 959         {
 960                 return retval;
 961         }
 962         cp15_ctrl_saved = cp15_ctrl;
 963         cp15_ctrl &= ~(ARMV4_5_MMU_ENABLED | ARMV4_5_D_U_CACHE_ENABLED | ARMV4_5_I_CACHE_ENABLED);
 964         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl);
 965
 966         /* read CP15 test state register */
 967         arm920t_read_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), &cp15c15);
 968         if ((retval = jtag_execute_queue()) != ERROR_OK)
 969         {
 970                 return retval;
 971         }
 972
 973         /* prepare reading D TLB content
 974          * */
 975
 976         /* set interpret mode */
 977         cp15c15 |= 0x1;
 978         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
 979
 980         /* Read D TLB lockdown */
 981         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,0), ARMV4_5_LDR(1, 0));
 982
 983         /* clear interpret mode */
 984         cp15c15 &= ~0x1;
 985         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
 986
 987         /* read D TLB lockdown stored to r1 */
 988         arm9tdmi_read_core_regs(target, 0x2, regs_p);
 989         if ((retval = jtag_execute_queue()) != ERROR_OK)
 990         {
 991                 return retval;
 992         }
 993         Dlockdown = regs[1];
 994
 995         for (victim = 0; victim < 64; victim += 8)
 996         {
 997                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
 998                  * base remains unchanged, victim goes through entries 0 to 63 */
 999                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1000                 arm9tdmi_write_core_regs(target, 0x2, regs);
1001
1002                 /* set interpret mode */
1003                 cp15c15 |= 0x1;
1004                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1005
1006                 /* Write D TLB lockdown */
1007                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1008
1009                 /* Read D TLB CAM */
1010                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,6,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1011
1012                 /* clear interpret mode */
1013                 cp15c15 &= ~0x1;
1014                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1015
1016                 /* read D TLB CAM content stored to r2-r9 */
1017                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1018                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1019                 {
1020                         return retval;
1021                 }
1022
1023                 for (i = 0; i < 8; i++)
1024                         d_tlb[victim + i].cam = regs[i + 2];
1025         }
1026
1027         for (victim = 0; victim < 64; victim++)
1028         {
1029                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1030                  * base remains unchanged, victim goes through entries 0 to 63 */
1031                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1032                 arm9tdmi_write_core_regs(target, 0x2, regs);
1033
1034                 /* set interpret mode */
1035                 cp15c15 |= 0x1;
1036                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1037
1038                 /* Write D TLB lockdown */
1039                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1040
1041                 /* Read D TLB RAM1 */
1042                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,10,4), ARMV4_5_LDR(2,0));
1043
1044                 /* Read D TLB RAM2 */
1045                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,2,5), ARMV4_5_LDR(3,0));
1046
1047                 /* clear interpret mode */
1048                 cp15c15 &= ~0x1;
1049                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1050
1051                 /* read D TLB RAM content stored to r2 and r3 */
1052                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1053                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1054                 {
1055                         return retval;
1056                 }
1057
1058                 d_tlb[victim].ram1 = regs[2];
1059                 d_tlb[victim].ram2 = regs[3];
1060         }
1061
1062         /* restore D TLB lockdown */
1063         regs[1] = Dlockdown;
1064         arm9tdmi_write_core_regs(target, 0x2, regs);
1065
1066         /* Write D TLB lockdown */
1067         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,0), ARMV4_5_STR(1, 0));
1068
1069         /* prepare reading I TLB content
1070          * */
1071
1072         /* set interpret mode */
1073         cp15c15 |= 0x1;
1074         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1075
1076         /* Read I TLB lockdown */
1077         arm920t_execute_cp15(target, ARMV4_5_MRC(15,0,0,10,0,1), ARMV4_5_LDR(1, 0));
1078
1079         /* clear interpret mode */
1080         cp15c15 &= ~0x1;
1081         arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1082
1083         /* read I TLB lockdown stored to r1 */
1084         arm9tdmi_read_core_regs(target, 0x2, regs_p);
1085         if ((retval = jtag_execute_queue()) != ERROR_OK)
1086         {
1087                 return retval;
1088         }
1089         Ilockdown = regs[1];
1090
1091         for (victim = 0; victim < 64; victim += 8)
1092         {
1093                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1094                  * base remains unchanged, victim goes through entries 0 to 63 */
1095                 regs[1] = (Ilockdown & 0xfc000000) | (victim << 20);
1096                 arm9tdmi_write_core_regs(target, 0x2, regs);
1097
1098                 /* set interpret mode */
1099                 cp15c15 |= 0x1;
1100                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1101
1102                 /* Write I TLB lockdown */
1103                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1104
1105                 /* Read I TLB CAM */
1106                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,5,4), ARMV4_5_LDMIA(0, 0x3fc, 0, 0));
1107
1108                 /* clear interpret mode */
1109                 cp15c15 &= ~0x1;
1110                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1111
1112                 /* read I TLB CAM content stored to r2-r9 */
1113                 arm9tdmi_read_core_regs(target, 0x3fc, regs_p);
1114                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1115                 {
1116                         return retval;
1117                 }
1118
1119                 for (i = 0; i < 8; i++)
1120                         i_tlb[i + victim].cam = regs[i + 2];
1121         }
1122
1123         for (victim = 0; victim < 64; victim++)
1124         {
1125                 /* new lockdown value: base[31:26]:victim[25:20]:SBZ[19:1]:p[0]
1126                  * base remains unchanged, victim goes through entries 0 to 63 */
1127                 regs[1] = (Dlockdown & 0xfc000000) | (victim << 20);
1128                 arm9tdmi_write_core_regs(target, 0x2, regs);
1129
1130                 /* set interpret mode */
1131                 cp15c15 |= 0x1;
1132                 arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0xf, 0), cp15c15);
1133
1134                 /* Write I TLB lockdown */
1135                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1136
1137                 /* Read I TLB RAM1 */
1138                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,9,4), ARMV4_5_LDR(2,0));
1139
1140                 /* Read I TLB RAM2 */
1141                 arm920t_execute_cp15(target, ARMV4_5_MCR(15,4,0,15,1,5), ARMV4_5_LDR(3,0));
1142
1143                 /* clear interpret mode */
1144                 cp15c15 &= ~0x1;
1145                 arm920t_write_cp15_physical(target, 0x1e, cp15c15);
1146
1147                 /* read I TLB RAM content stored to r2 and r3 */
1148                 arm9tdmi_read_core_regs(target, 0xc, regs_p);
1149                 if ((retval = jtag_execute_queue()) != ERROR_OK)
1150                 {
1151                         return retval;
1152                 }
1153
1154                 i_tlb[victim].ram1 = regs[2];
1155                 i_tlb[victim].ram2 = regs[3];
1156         }
1157
1158         /* restore I TLB lockdown */
1159         regs[1] = Ilockdown;
1160         arm9tdmi_write_core_regs(target, 0x2, regs);
1161
1162         /* Write I TLB lockdown */
1163         arm920t_execute_cp15(target, ARMV4_5_MCR(15,0,0,10,0,1), ARMV4_5_STR(1, 0));
1164
1165         /* restore CP15 MMU and Cache settings */
1166         arm920t_write_cp15_physical(target, ARM920T_CP15_PHYS_ADDR(0, 0x1, 0), cp15_ctrl_saved);
1167
1168         /* output data to file */
1169         fprintf(output, "D TLB content:\n");
1170         for (i = 0; i < 64; i++)
1171         {
1172                 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1173         }
1174
1175         fprintf(output, "\n\nI TLB content:\n");
1176         for (i = 0; i < 64; i++)
1177         {
1178                 fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
1179         }
1180
1181         command_print(CMD_CTX, "mmu content successfully output to %s", CMD_ARGV[0]);
1182
1183         fclose(output);
1184
1185         if (!is_arm_mode(armv4_5->core_mode))
1186                 return ERROR_FAIL;
1187
1188         /* force writeback of the valid data */
1189         r = armv4_5->core_cache->reg_list;
1190         r[0].dirty = r[0].valid;
1191         r[1].dirty = r[1].valid;
1192         r[2].dirty = r[2].valid;
1193         r[3].dirty = r[3].valid;
1194         r[4].dirty = r[4].valid;
1195         r[5].dirty = r[5].valid;
1196         r[6].dirty = r[6].valid;
1197         r[7].dirty = r[7].valid;
1198
1199         r = arm_reg_current(armv4_5, 8);
1200         r->dirty = r->valid;
1201
1202         r = arm_reg_current(armv4_5, 9);
1203         r->dirty = r->valid;
1204
1205         return ERROR_OK;
1206 }
1207
1208 COMMAND_HANDLER(arm920t_handle_cp15_command)
1209 {
1210         int retval;
1211         struct target *target = get_current_target(CMD_CTX);
1212         struct arm920t_common *arm920t = target_to_arm920(target);
1213
1214         retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1215         if (retval != ERROR_OK)
1216                 return retval;
1217
1218         if (target->state != TARGET_HALTED)
1219         {
1220                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1221                 return ERROR_OK;
1222         }
1223
1224         /* one or more argument, access a single register (write if second argument is given */
1225         if (CMD_ARGC >= 1)
1226         {
1227                 int address;
1228                 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
1229
1230                 if (CMD_ARGC == 1)
1231                 {
1232                         uint32_t value;
1233                         if ((retval = arm920t_read_cp15_physical(target, address, &value)) != ERROR_OK)
1234                         {
1235                                 command_print(CMD_CTX, "couldn't access reg %i", address);
1236                                 return ERROR_OK;
1237                         }
1238                         if ((retval = jtag_execute_queue()) != ERROR_OK)
1239                         {
1240                                 return retval;
1241                         }
1242
1243                         command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1244                 }
1245                 else if (CMD_ARGC == 2)
1246                 {
1247                         uint32_t value;
1248                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1249                         if ((retval = arm920t_write_cp15_physical(target, address, value)) != ERROR_OK)
1250                         {
1251                                 command_print(CMD_CTX, "couldn't access reg %i", address);
1252                                 return ERROR_OK;
1253                         }
1254                         command_print(CMD_CTX, "%i: %8.8" PRIx32 "", address, value);
1255                 }
1256         }
1257
1258         return ERROR_OK;
1259 }
1260
1261 COMMAND_HANDLER(arm920t_handle_cp15i_command)
1262 {
1263         int retval;
1264         struct target *target = get_current_target(CMD_CTX);
1265         struct arm920t_common *arm920t = target_to_arm920(target);
1266
1267         retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1268         if (retval != ERROR_OK)
1269                 return retval;
1270
1271
1272         if (target->state != TARGET_HALTED)
1273         {
1274                 command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
1275                 return ERROR_OK;
1276         }
1277
1278         /* one or more argument, access a single register (write if second argument is given */
1279         if (CMD_ARGC >= 1)
1280         {
1281                 uint32_t opcode;
1282                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
1283
1284                 if (CMD_ARGC == 1)
1285                 {
1286                         uint32_t value;
1287                         if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
1288                         {
1289                                 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1290                                 return ERROR_OK;
1291                         }
1292
1293                         command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1294                 }
1295                 else if (CMD_ARGC == 2)
1296                 {
1297                         uint32_t value;
1298                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1299                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
1300                         {
1301                                 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1302                                 return ERROR_OK;
1303                         }
1304                         command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
1305                 }
1306                 else if (CMD_ARGC == 3)
1307                 {
1308                         uint32_t value;
1309                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
1310                         uint32_t address;
1311                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], address);
1312                         if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
1313                         {
1314                                 command_print(CMD_CTX, "couldn't execute %8.8" PRIx32 "", opcode);
1315                                 return ERROR_OK;
1316                         }
1317                         command_print(CMD_CTX, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
1318                 }
1319         }
1320         else
1321         {
1322                 command_print(CMD_CTX, "usage: arm920t cp15i <opcode> [value] [address]");
1323         }
1324
1325         return ERROR_OK;
1326 }
1327
1328 COMMAND_HANDLER(arm920t_handle_cache_info_command)
1329 {
1330         int retval;
1331         struct target *target = get_current_target(CMD_CTX);
1332         struct arm920t_common *arm920t = target_to_arm920(target);
1333
1334         retval = arm920t_verify_pointer(CMD_CTX, arm920t);
1335         if (retval != ERROR_OK)
1336                 return retval;
1337
1338         return armv4_5_handle_cache_info_command(CMD_CTX, &arm920t->armv4_5_mmu.armv4_5_cache);
1339 }
1340
1341
1342 static int arm920t_mrc(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
1343 {
1344         if (cpnum!=15)
1345         {
1346                 LOG_ERROR("Only cp15 is supported");
1347                 return ERROR_FAIL;
1348         }
1349
1350         return arm920t_read_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
1351 }
1352
1353 static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
1354 {
1355         if (cpnum!=15)
1356         {
1357                 LOG_ERROR("Only cp15 is supported");
1358                 return ERROR_FAIL;
1359         }
1360
1361         return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
1362 }
1363
1364 /** Registers commands to access coprocessor, cache, and MMU resources. */
1365 int arm920t_register_commands(struct command_context *cmd_ctx)
1366 {
1367         int retval;
1368         struct command *arm920t_cmd;
1369
1370         retval = arm9tdmi_register_commands(cmd_ctx);
1371
1372         arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t",
1373                         NULL, COMMAND_ANY,
1374                         "arm920t specific commands");
1375
1376         register_command(cmd_ctx, arm920t_cmd, "cp15",
1377                         arm920t_handle_cp15_command, COMMAND_EXEC,
1378                         "display/modify cp15 register <num> [value]");
1379         register_command(cmd_ctx, arm920t_cmd, "cp15i",
1380                         arm920t_handle_cp15i_command, COMMAND_EXEC,
1381                         "display/modify cp15 (interpreted access) "
1382                                 "<opcode> [value] [address]");
1383         register_command(cmd_ctx, arm920t_cmd, "cache_info",
1384                         arm920t_handle_cache_info_command, COMMAND_EXEC,
1385                         "display information about target caches");
1386         register_command(cmd_ctx, arm920t_cmd, "read_cache",
1387                         arm920t_handle_read_cache_command, COMMAND_EXEC,
1388                         "display I/D cache content");
1389         register_command(cmd_ctx, arm920t_cmd, "read_mmu",
1390                         arm920t_handle_read_mmu_command, COMMAND_EXEC,
1391                         "display I/D mmu content");
1392
1393         return retval;
1394 }
1395
1396 /** Holds methods for ARM920 targets. */
1397 struct target_type arm920t_target =
1398 {
1399         .name = "arm920t",
1400
1401         .poll = arm7_9_poll,
1402         .arch_state = arm920t_arch_state,
1403
1404         .target_request_data = arm7_9_target_request_data,
1405
1406         .halt = arm7_9_halt,
1407         .resume = arm7_9_resume,
1408         .step = arm7_9_step,
1409
1410         .assert_reset = arm7_9_assert_reset,
1411         .deassert_reset = arm7_9_deassert_reset,
1412         .soft_reset_halt = arm920t_soft_reset_halt,
1413
1414         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
1415
1416         .read_memory = arm920t_read_memory,
1417         .write_memory = arm920t_write_memory,
1418         .read_phys_memory = arm920t_read_phys_memory,
1419         .write_phys_memory = arm920t_write_phys_memory,
1420         .mmu = arm920_mmu,
1421         .virt2phys = arm920_virt2phys,
1422
1423         .bulk_write_memory = arm7_9_bulk_write_memory,
1424
1425         .checksum_memory = arm_checksum_memory,
1426         .blank_check_memory = arm_blank_check_memory,
1427
1428         .run_algorithm = armv4_5_run_algorithm,
1429
1430         .add_breakpoint = arm7_9_add_breakpoint,
1431         .remove_breakpoint = arm7_9_remove_breakpoint,
1432         .add_watchpoint = arm7_9_add_watchpoint,
1433         .remove_watchpoint = arm7_9_remove_watchpoint,
1434
1435         .register_commands = arm920t_register_commands,
1436         .target_create = arm920t_target_create,
1437         .init_target = arm9tdmi_init_target,
1438         .examine = arm7_9_examine,
1439         .mrc = arm920t_mrc,
1440         .mcr = arm920t_mcr,
1441 };