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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm7tdmi.h"
  31
  32 #include "arm7_9_common.h"
  33 #include "register.h"
  34 #include "target.h"
  35 #include "armv4_5.h"
  36 #include "embeddedice.h"
  37 #include "etm.h"
  38 #include "log.h"
  39 #include "jtag.h"
  40 #include "arm_jtag.h"
  41
  42 #include <stdlib.h>
  43 #include <string.h>
  44
  45 #if 0
  46 #define _DEBUG_INSTRUCTION_EXECUTION_
  47 #endif
  48
  49 /* forward declarations */
  50
  51 int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp);
  52 int arm7tdmi_quit(void);
  53
  54 /* target function declarations */
  55 int arm7tdmi_poll(struct target_s *target);
  56 int arm7tdmi_halt(target_t *target);
  57
  58 target_type_t arm7tdmi_target =
  59 {
  60         .name = "arm7tdmi",
  61
  62         .poll = arm7_9_poll,
  63         .arch_state = armv4_5_arch_state,
  64
  65         .target_request_data = arm7_9_target_request_data,
  66
  67         .halt = arm7_9_halt,
  68         .resume = arm7_9_resume,
  69         .step = arm7_9_step,
  70
  71         .assert_reset = arm7_9_assert_reset,
  72         .deassert_reset = arm7_9_deassert_reset,
  73         .soft_reset_halt = arm7_9_soft_reset_halt,
  74
  75         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  76
  77         .read_memory = arm7_9_read_memory,
  78         .write_memory = arm7_9_write_memory,
  79         .bulk_write_memory = arm7_9_bulk_write_memory,
  80         .checksum_memory = arm7_9_checksum_memory,
  81         .blank_check_memory = arm7_9_blank_check_memory,
  82
  83         .run_algorithm = armv4_5_run_algorithm,
  84
  85         .add_breakpoint = arm7_9_add_breakpoint,
  86         .remove_breakpoint = arm7_9_remove_breakpoint,
  87         .add_watchpoint = arm7_9_add_watchpoint,
  88         .remove_watchpoint = arm7_9_remove_watchpoint,
  89
  90         .register_commands  = arm7tdmi_register_commands,
  91         .target_create  = arm7tdmi_target_create,
  92         .init_target = arm7tdmi_init_target,
  93         .examine = arm7tdmi_examine,
  94         .quit = arm7tdmi_quit
  95 };
  96
  97 int arm7tdmi_examine_debug_reason(target_t *target)
  98 {
  99         int retval = ERROR_OK;
 100         /* get pointers to arch-specific information */
 101         armv4_5_common_t *armv4_5 = target->arch_info;
 102         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 103
 104         /* only check the debug reason if we don't know it already */
 105         if ((target->debug_reason != DBG_REASON_DBGRQ)
 106                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 107         {
 108                 scan_field_t fields[2];
 109                 u8 databus[4];
 110                 u8 breakpoint;
 111
 112                 jtag_add_end_state(TAP_DRPAUSE);
 113
 114                 fields[0].tap = arm7_9->jtag_info.tap;
 115                 fields[0].num_bits = 1;
 116                 fields[0].out_value = NULL;
 117                 fields[0].in_value = &breakpoint;
 118                 fields[0].in_handler = NULL;
 119
 120                 fields[1].tap = arm7_9->jtag_info.tap;
 121                 fields[1].num_bits = 32;
 122                 fields[1].out_value = NULL;
 123                 fields[1].in_value = databus;
 124                 fields[1].in_handler = NULL;
 125
 126                 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 127                 {
 128                         return retval;
 129                 }
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 131
 132                 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
 133                 if((retval = jtag_execute_queue()) != ERROR_OK)
 134                 {
 135                         return retval;
 136                 }
 137
 138                 fields[0].in_value = NULL;
 139                 fields[0].out_value = &breakpoint;
 140                 fields[1].in_value = NULL;
 141                 fields[1].out_value = databus;
 142
 143                 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
 144
 145                 if (breakpoint & 1)
 146                         target->debug_reason = DBG_REASON_WATCHPOINT;
 147                 else
 148                         target->debug_reason = DBG_REASON_BREAKPOINT;
 149         }
 150
 151         return ERROR_OK;
 152 }
 153
 154 static int arm7tdmi_num_bits[]={1, 32};
 155 static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
 156 {
 157         u32 values[2]={breakpoint, flip_u32(out, 32)};
 158
 159         jtag_add_dr_out(jtag_info->tap,
 160                         2,
 161                         arm7tdmi_num_bits,
 162                         values,
 163                         TAP_INVALID);
 164
 165         jtag_add_runtest(0, TAP_INVALID);
 166
 167         return ERROR_OK;
 168 }
 169
 170 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
 171 static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
 172 {
 173         jtag_add_end_state(TAP_DRPAUSE);
 174         arm_jtag_scann(jtag_info, 0x1);
 175         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 176
 177         return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 178 }
 179
 180 /* clock the target, reading the databus */
 181 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 182 {
 183         int retval = ERROR_OK;
 184         scan_field_t fields[2];
 185
 186         jtag_add_end_state(TAP_DRPAUSE);
 187         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 188         {
 189                 return retval;
 190         }
 191         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 192
 193         fields[0].tap = jtag_info->tap;
 194         fields[0].num_bits = 1;
 195         fields[0].out_value = NULL;
 196         fields[0].in_value = NULL;
 197         fields[0].in_handler = NULL;
 198
 199
 200         fields[1].tap = jtag_info->tap;
 201         fields[1].num_bits = 32;
 202         fields[1].out_value = NULL;
 203         u8 tmp[4];
 204         fields[1].in_value = tmp;
 205         fields[1].in_handler = NULL;
 206
 207         jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 208
 209         if (jtag_error==ERROR_OK)
 210         {
 211                 *in=flip_u32(le_to_h_u32(tmp), 32);
 212         }
 213
 214         jtag_add_runtest(0, TAP_INVALID);
 215
 216 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 217 {
 218                 if((retval = jtag_execute_queue()) != ERROR_OK)
 219                 {
 220                         return retval;
 221                 }
 222
 223                 if (in)
 224                 {
 225                         LOG_DEBUG("in: 0x%8.8x", *in);
 226                 }
 227                 else
 228                 {
 229                         LOG_ERROR("BUG: called with in == NULL");
 230                 }
 231 }
 232 #endif
 233
 234         return ERROR_OK;
 235 }
 236
 237 void arm_endianness(u8 *tmp, void *in, int size, int be, int flip)
 238 {
 239         u32 readback=le_to_h_u32(tmp);
 240         if (flip)
 241                 readback=flip_u32(readback, 32);
 242         switch (size)
 243         {
 244                 case 4:
 245                         if (be)
 246                         {
 247                                 h_u32_to_be(((u8*)in), readback);
 248                         } else
 249                         {
 250                                  h_u32_to_le(((u8*)in), readback);
 251                         }
 252                         break;
 253                 case 2:
 254                         if (be)
 255                         {
 256                                 h_u16_to_be(((u8*)in), readback & 0xffff);
 257                         } else
 258                         {
 259                                 h_u16_to_le(((u8*)in), readback & 0xffff);
 260                         }
 261                         break;
 262                 case 1:
 263                         *((u8 *)in)= readback & 0xff;
 264                         break;
 265         }
 266
 267 }
 268
 269 /* clock the target, and read the databus
 270  * the *in pointer points to a buffer where elements of 'size' bytes
 271  * are stored in big (be==1) or little (be==0) endianness
 272  */
 273 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 274 {
 275         int retval = ERROR_OK;
 276         scan_field_t fields[2];
 277
 278         jtag_add_end_state(TAP_DRPAUSE);
 279         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 280         {
 281                 return retval;
 282         }
 283         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 284
 285         fields[0].tap = jtag_info->tap;
 286         fields[0].num_bits = 1;
 287         fields[0].out_value = NULL;
 288         fields[0].in_value = NULL;
 289         fields[0].in_handler = NULL;
 290
 291         fields[1].tap = jtag_info->tap;
 292         fields[1].num_bits = 32;
 293         fields[1].out_value = NULL;
 294         u8 tmp[4];
 295         fields[1].in_value = tmp;
 296         fields[1].in_handler = NULL;
 297
 298         jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 299
 300         arm_endianness(tmp, in, size, be, 1);
 301
 302         jtag_add_runtest(0, TAP_INVALID);
 303
 304 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 305 {
 306                 if((retval = jtag_execute_queue()) != ERROR_OK)
 307                 {
 308                         return retval;
 309                 }
 310
 311                 if (in)
 312                 {
 313                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 314                 }
 315                 else
 316                 {
 317                         LOG_ERROR("BUG: called with in == NULL");
 318                 }
 319 }
 320 #endif
 321
 322         return ERROR_OK;
 323 }
 324
 325 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 326 {
 327         /* get pointers to arch-specific information */
 328         armv4_5_common_t *armv4_5 = target->arch_info;
 329         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 330         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 331
 332         /* save r0 before using it and put system in ARM state
 333          * to allow common handling of ARM and THUMB debugging */
 334
 335         /* fetch STR r0, [r0] */
 336         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 337         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 338         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 339         /* nothing fetched, STR r0, [r0] in Execute (2) */
 340         arm7tdmi_clock_data_in(jtag_info, r0);
 341
 342         /* MOV r0, r15 fetched, STR in Decode */
 343         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
 344         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 345         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 346         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 347         /* nothing fetched, STR r0, [r0] in Execute (2) */
 348         arm7tdmi_clock_data_in(jtag_info, pc);
 349
 350         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 351         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 352         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 353         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 354         /* nothing fetched, data for LDR r0, [PC, #0] */
 355         arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
 356         /* nothing fetched, data from previous cycle is written to register */
 357         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 358
 359         /* fetch BX */
 360         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
 361         /* NOP fetched, BX in Decode, MOV in Execute */
 362         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 363         /* NOP fetched, BX in Execute (1) */
 364         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 365
 366         jtag_execute_queue();
 367
 368         /* fix program counter:
 369          * MOV r0, r15 was the 4th instruction (+6)
 370          * reading PC in Thumb state gives address of instruction + 4
 371          */
 372         *pc -= 0xa;
 373 }
 374
 375 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 376 {
 377         int i;
 378         /* get pointers to arch-specific information */
 379         armv4_5_common_t *armv4_5 = target->arch_info;
 380         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 381         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 382
 383         /* STMIA r0-15, [r0] at debug speed
 384          * register values will start to appear on 4th DCLK
 385          */
 386         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 387
 388         /* fetch NOP, STM in DECODE stage */
 389         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 390         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 391         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 392
 393         for (i = 0; i <= 15; i++)
 394         {
 395                 if (mask & (1 << i))
 396                         /* nothing fetched, STM still in EXECUTE (1+i cycle) */
 397                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 398         }
 399 }
 400
 401 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 402 {
 403         int i;
 404         /* get pointers to arch-specific information */
 405         armv4_5_common_t *armv4_5 = target->arch_info;
 406         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 407         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 408         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 409         u32 *buf_u32 = buffer;
 410         u16 *buf_u16 = buffer;
 411         u8 *buf_u8 = buffer;
 412
 413         /* STMIA r0-15, [r0] at debug speed
 414          * register values will start to appear on 4th DCLK
 415          */
 416         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 417
 418         /* fetch NOP, STM in DECODE stage */
 419         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 420         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 421         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 422
 423         for (i = 0; i <= 15; i++)
 424         {
 425                 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
 426                 if (mask & (1 << i))
 427                 {
 428                         switch (size)
 429                         {
 430                                 case 4:
 431                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 432                                         break;
 433                                 case 2:
 434                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 435                                         break;
 436                                 case 1:
 437                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 438                                         break;
 439                         }
 440                 }
 441         }
 442 }
 443
 444 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 445 {
 446         /* get pointers to arch-specific information */
 447         armv4_5_common_t *armv4_5 = target->arch_info;
 448         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 449         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 450
 451         /* MRS r0, cpsr */
 452         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
 453
 454         /* STR r0, [r15] */
 455         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
 456         /* fetch NOP, STR in DECODE stage */
 457         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 458         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 459         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 460         /* nothing fetched, STR still in EXECUTE (2nd cycle) */
 461         arm7tdmi_clock_data_in(jtag_info, xpsr);
 462 }
 463
 464 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 465 {
 466         /* get pointers to arch-specific information */
 467         armv4_5_common_t *armv4_5 = target->arch_info;
 468         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 469         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 470
 471         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 472
 473         /* MSR1 fetched */
 474         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
 475         /* MSR2 fetched, MSR1 in DECODE */
 476         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
 477         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 478         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
 479         /* nothing fetched, MSR1 in EXECUTE (2) */
 480         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 481         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 482         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
 483         /* nothing fetched, MSR2 in EXECUTE (2) */
 484         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 485         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 486         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 487         /* nothing fetched, MSR3 in EXECUTE (2) */
 488         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 489         /* NOP fetched, MSR4 in EXECUTE (1) */
 490         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 491         /* nothing fetched, MSR4 in EXECUTE (2) */
 492         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 493 }
 494
 495 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 496 {
 497         /* get pointers to arch-specific information */
 498         armv4_5_common_t *armv4_5 = target->arch_info;
 499         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 500         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 501
 502         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 503
 504         /* MSR fetched */
 505         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
 506         /* NOP fetched, MSR in DECODE */
 507         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 508         /* NOP fetched, MSR in EXECUTE (1) */
 509         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 510         /* nothing fetched, MSR in EXECUTE (2) */
 511         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 512 }
 513
 514 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 515 {
 516         int i;
 517         /* get pointers to arch-specific information */
 518         armv4_5_common_t *armv4_5 = target->arch_info;
 519         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 520         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 521
 522         /* LDMIA r0-15, [r0] at debug speed
 523         * register values will start to appear on 4th DCLK
 524         */
 525         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 526
 527         /* fetch NOP, LDM in DECODE stage */
 528         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 529         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 530         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 531
 532         for (i = 0; i <= 15; i++)
 533         {
 534                 if (mask & (1 << i))
 535                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 536                         arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 537         }
 538         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 539 }
 540
 541 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
 542 {
 543         /* get pointers to arch-specific information */
 544         armv4_5_common_t *armv4_5 = target->arch_info;
 545         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 546         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 547
 548         /* put system-speed load-multiple into the pipeline */
 549         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 550         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 551         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
 552 }
 553
 554 void arm7tdmi_load_hword_reg(target_t *target, int num)
 555 {
 556         /* get pointers to arch-specific information */
 557         armv4_5_common_t *armv4_5 = target->arch_info;
 558         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 559         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 560
 561         /* put system-speed load half-word into the pipeline */
 562         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 563         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 564         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
 565 }
 566
 567 void arm7tdmi_load_byte_reg(target_t *target, int num)
 568 {
 569         /* get pointers to arch-specific information */
 570         armv4_5_common_t *armv4_5 = target->arch_info;
 571         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 572         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 573
 574         /* put system-speed load byte into the pipeline */
 575         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 576         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 577         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 578 }
 579
 580 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
 581 {
 582         /* get pointers to arch-specific information */
 583         armv4_5_common_t *armv4_5 = target->arch_info;
 584         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 585         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 586
 587         /* put system-speed store-multiple into the pipeline */
 588         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 589         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 590         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
 591 }
 592
 593 void arm7tdmi_store_hword_reg(target_t *target, int num)
 594 {
 595         /* get pointers to arch-specific information */
 596         armv4_5_common_t *armv4_5 = target->arch_info;
 597         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 598         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 599
 600         /* put system-speed store half-word into the pipeline */
 601         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 602         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 603         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
 604 }
 605
 606 void arm7tdmi_store_byte_reg(target_t *target, int num)
 607 {
 608         /* get pointers to arch-specific information */
 609         armv4_5_common_t *armv4_5 = target->arch_info;
 610         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 611         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 612
 613         /* put system-speed store byte into the pipeline */
 614         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 615         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 616         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 617 }
 618
 619 void arm7tdmi_write_pc(target_t *target, u32 pc)
 620 {
 621         /* get pointers to arch-specific information */
 622         armv4_5_common_t *armv4_5 = target->arch_info;
 623         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 624         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 625
 626         /* LDMIA r0-15, [r0] at debug speed
 627          * register values will start to appear on 4th DCLK
 628          */
 629         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
 630         /* fetch NOP, LDM in DECODE stage */
 631         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 632         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 633         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 634         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
 635         arm7tdmi_clock_out_inner(jtag_info, pc, 0);
 636         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
 637         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 638         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
 639         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 640         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 641         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 642         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 643         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 644 }
 645
 646 void arm7tdmi_branch_resume(target_t *target)
 647 {
 648         /* get pointers to arch-specific information */
 649         armv4_5_common_t *armv4_5 = target->arch_info;
 650         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 651         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 652
 653         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 654         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
 655 }
 656
 657 void arm7tdmi_branch_resume_thumb(target_t *target)
 658 {
 659         LOG_DEBUG("-");
 660
 661         /* get pointers to arch-specific information */
 662         armv4_5_common_t *armv4_5 = target->arch_info;
 663         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 664         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 665         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 666
 667         /* LDMIA r0, [r0] at debug speed
 668          * register values will start to appear on 4th DCLK
 669          */
 670         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
 671
 672         /* fetch NOP, LDM in DECODE stage */
 673         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 674         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 675         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 676         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 677         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 678         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 679         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 680
 681         /* Branch and eXchange */
 682         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
 683
 684         embeddedice_read_reg(dbg_stat);
 685
 686         /* fetch NOP, BX in DECODE stage */
 687         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 688
 689         /* target is now in Thumb state */
 690         embeddedice_read_reg(dbg_stat);
 691
 692         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 693         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 694
 695         /* target is now in Thumb state */
 696         embeddedice_read_reg(dbg_stat);
 697
 698         /* load r0 value */
 699         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 700         /* fetch NOP, LDR in Decode */
 701         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 702         /* fetch NOP, LDR in Execute */
 703         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 704         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 705         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 706         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 707         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 708
 709         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 710         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 711
 712         embeddedice_read_reg(dbg_stat);
 713
 714         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 715         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
 716 }
 717
 718 void arm7tdmi_build_reg_cache(target_t *target)
 719 {
 720         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 721         /* get pointers to arch-specific information */
 722         armv4_5_common_t *armv4_5 = target->arch_info;
 723
 724         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 725         armv4_5->core_cache = (*cache_p);
 726 }
 727
 728 int arm7tdmi_examine(struct target_s *target)
 729 {
 730         int retval;
 731         armv4_5_common_t *armv4_5 = target->arch_info;
 732         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 733         if (!target->type->examined)
 734         {
 735                 /* get pointers to arch-specific information */
 736                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 737                 reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
 738                 if (t==NULL)
 739                         return ERROR_FAIL;
 740
 741                 (*cache_p) = t;
 742                 arm7_9->eice_cache = (*cache_p);
 743
 744                 if (arm7_9->etm_ctx)
 745                 {
 746                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 747                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 748                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 749                 }
 750                 target->type->examined = 1;
 751         }
 752         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 753                 return retval;
 754         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 755                 return retval;
 756         if (arm7_9->etm_ctx)
 757         {
 758                 if ((retval=etm_setup(target))!=ERROR_OK)
 759                         return retval;
 760         }
 761         return ERROR_OK;
 762 }
 763
 764 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 765 {
 766         arm7tdmi_build_reg_cache(target);
 767
 768         return ERROR_OK;
 769 }
 770
 771 int arm7tdmi_quit(void)
 772 {
 773         return ERROR_OK;
 774 }
 775
 776 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
 777 {
 778         armv4_5_common_t *armv4_5;
 779         arm7_9_common_t *arm7_9;
 780
 781         arm7_9 = &arm7tdmi->arm7_9_common;
 782         armv4_5 = &arm7_9->armv4_5_common;
 783
 784         /* prepare JTAG information for the new target */
 785         arm7_9->jtag_info.tap = tap;
 786         arm7_9->jtag_info.scann_size = 4;
 787
 788         /* register arch-specific functions */
 789         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
 790         arm7_9->change_to_arm = arm7tdmi_change_to_arm;
 791         arm7_9->read_core_regs = arm7tdmi_read_core_regs;
 792         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
 793         arm7_9->read_xpsr = arm7tdmi_read_xpsr;
 794
 795         arm7_9->write_xpsr = arm7tdmi_write_xpsr;
 796         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
 797         arm7_9->write_core_regs = arm7tdmi_write_core_regs;
 798
 799         arm7_9->load_word_regs = arm7tdmi_load_word_regs;
 800         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
 801         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
 802
 803         arm7_9->store_word_regs = arm7tdmi_store_word_regs;
 804         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
 805         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
 806
 807         arm7_9->write_pc = arm7tdmi_write_pc;
 808         arm7_9->branch_resume = arm7tdmi_branch_resume;
 809         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
 810
 811         arm7_9->enable_single_step = arm7_9_enable_eice_step;
 812         arm7_9->disable_single_step = arm7_9_disable_eice_step;
 813
 814         arm7_9->pre_debug_entry = NULL;
 815         arm7_9->post_debug_entry = NULL;
 816
 817         arm7_9->pre_restore_context = NULL;
 818         arm7_9->post_restore_context = NULL;
 819
 820         /* initialize arch-specific breakpoint handling */
 821         arm7_9->arm_bkpt = 0xdeeedeee;
 822         arm7_9->thumb_bkpt = 0xdeee;
 823
 824         arm7_9->dbgreq_adjust_pc = 2;
 825         arm7_9->arch_info = arm7tdmi;
 826
 827         arm7tdmi->arch_info = NULL;
 828         arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 829
 830         arm7_9_init_arch_info(target, arm7_9);
 831
 832         return ERROR_OK;
 833 }
 834
 835 int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
 836 {
 837         arm7tdmi_common_t *arm7tdmi;
 838
 839         arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
 840         arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
 841
 842         return ERROR_OK;
 843 }
 844
 845 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 846 {
 847         int retval;
 848
 849         retval = arm7_9_register_commands(cmd_ctx);
 850
 851         return retval;
 852 }