1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
30 #include "embeddedice.h"
40 #define _DEBUG_INSTRUCTION_EXECUTION_
44 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx);
46 /* forward declarations */
47 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
48 int arm7tdmi_target_create(Jim_Interp *interp, struct target_s *target);
49 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
50 int arm7tdmi_quit(void);
52 /* target function declarations */
53 int arm7tdmi_poll(struct target_s *target);
54 int arm7tdmi_halt(target_t *target);
56 target_type_t arm7tdmi_target =
61 .arch_state = armv4_5_arch_state,
63 .target_request_data = arm7_9_target_request_data,
66 .resume = arm7_9_resume,
69 .assert_reset = arm7_9_assert_reset,
70 .deassert_reset = arm7_9_deassert_reset,
71 .soft_reset_halt = arm7_9_soft_reset_halt,
73 .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
75 .read_memory = arm7_9_read_memory,
76 .write_memory = arm7_9_write_memory,
77 .bulk_write_memory = arm7_9_bulk_write_memory,
78 .checksum_memory = arm7_9_checksum_memory,
79 .blank_check_memory = arm7_9_blank_check_memory,
81 .run_algorithm = armv4_5_run_algorithm,
83 .add_breakpoint = arm7_9_add_breakpoint,
84 .remove_breakpoint = arm7_9_remove_breakpoint,
85 .add_watchpoint = arm7_9_add_watchpoint,
86 .remove_watchpoint = arm7_9_remove_watchpoint,
88 .register_commands = arm7tdmi_register_commands,
89 .target_command = arm7tdmi_target_command,
90 // .target_create = arm7tdmi_target_create,
91 .init_target = arm7tdmi_init_target,
92 .examine = arm7tdmi_examine,
96 int arm7tdmi_examine_debug_reason(target_t *target)
98 /* get pointers to arch-specific information */
99 armv4_5_common_t *armv4_5 = target->arch_info;
100 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
102 /* only check the debug reason if we don't know it already */
103 if ((target->debug_reason != DBG_REASON_DBGRQ)
104 && (target->debug_reason != DBG_REASON_SINGLESTEP))
106 scan_field_t fields[2];
110 jtag_add_end_state(TAP_PD);
112 fields[0].device = arm7_9->jtag_info.chain_pos;
113 fields[0].num_bits = 1;
114 fields[0].out_value = NULL;
115 fields[0].out_mask = NULL;
116 fields[0].in_value = &breakpoint;
117 fields[0].in_check_value = NULL;
118 fields[0].in_check_mask = NULL;
119 fields[0].in_handler = NULL;
120 fields[0].in_handler_priv = NULL;
122 fields[1].device = arm7_9->jtag_info.chain_pos;
123 fields[1].num_bits = 32;
124 fields[1].out_value = NULL;
125 fields[1].out_mask = NULL;
126 fields[1].in_value = databus;
127 fields[1].in_check_value = NULL;
128 fields[1].in_check_mask = NULL;
129 fields[1].in_handler = NULL;
130 fields[1].in_handler_priv = NULL;
132 arm_jtag_scann(&arm7_9->jtag_info, 0x1);
133 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
135 jtag_add_dr_scan(2, fields, TAP_PD);
136 jtag_execute_queue();
138 fields[0].in_value = NULL;
139 fields[0].out_value = &breakpoint;
140 fields[1].in_value = NULL;
141 fields[1].out_value = databus;
143 jtag_add_dr_scan(2, fields, TAP_PD);
146 target->debug_reason = DBG_REASON_WATCHPOINT;
148 target->debug_reason = DBG_REASON_BREAKPOINT;
154 static int arm7tdmi_num_bits[]={1, 32};
155 static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
157 u32 values[2]={breakpoint, flip_u32(out, 32)};
159 jtag_add_dr_out(jtag_info->chain_pos,
165 jtag_add_runtest(0, -1);
170 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
171 static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
173 jtag_add_end_state(TAP_PD);
174 arm_jtag_scann(jtag_info, 0x1);
175 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
177 return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
180 /* clock the target, reading the databus */
181 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
183 scan_field_t fields[2];
185 jtag_add_end_state(TAP_PD);
186 arm_jtag_scann(jtag_info, 0x1);
187 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
189 fields[0].device = jtag_info->chain_pos;
190 fields[0].num_bits = 1;
191 fields[0].out_value = NULL;
192 fields[0].out_mask = NULL;
193 fields[0].in_value = NULL;
194 fields[0].in_check_value = NULL;
195 fields[0].in_check_mask = NULL;
196 fields[0].in_handler = NULL;
197 fields[0].in_handler_priv = NULL;
199 fields[1].device = jtag_info->chain_pos;
200 fields[1].num_bits = 32;
201 fields[1].out_value = NULL;
202 fields[1].out_mask = NULL;
203 fields[1].in_value = NULL;
204 fields[1].in_handler = arm_jtag_buf_to_u32_flip;
205 fields[1].in_handler_priv = in;
206 fields[1].in_check_value = NULL;
207 fields[1].in_check_mask = NULL;
209 jtag_add_dr_scan(2, fields, -1);
211 jtag_add_runtest(0, -1);
213 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
215 jtag_execute_queue();
219 LOG_DEBUG("in: 0x%8.8x", *in);
223 LOG_ERROR("BUG: called with in == NULL");
231 /* clock the target, and read the databus
232 * the *in pointer points to a buffer where elements of 'size' bytes
233 * are stored in big (be==1) or little (be==0) endianness
235 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
237 scan_field_t fields[2];
239 jtag_add_end_state(TAP_PD);
240 arm_jtag_scann(jtag_info, 0x1);
241 arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
243 fields[0].device = jtag_info->chain_pos;
244 fields[0].num_bits = 1;
245 fields[0].out_value = NULL;
246 fields[0].out_mask = NULL;
247 fields[0].in_value = NULL;
248 fields[0].in_check_value = NULL;
249 fields[0].in_check_mask = NULL;
250 fields[0].in_handler = NULL;
251 fields[0].in_handler_priv = NULL;
253 fields[1].device = jtag_info->chain_pos;
254 fields[1].num_bits = 32;
255 fields[1].out_value = NULL;
256 fields[1].out_mask = NULL;
257 fields[1].in_value = NULL;
261 fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip;
264 fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip;
267 fields[1].in_handler = arm_jtag_buf_to_8_flip;
270 fields[1].in_handler_priv = in;
271 fields[1].in_check_value = NULL;
272 fields[1].in_check_mask = NULL;
274 jtag_add_dr_scan(2, fields, -1);
276 jtag_add_runtest(0, -1);
278 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
280 jtag_execute_queue();
284 LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
288 LOG_ERROR("BUG: called with in == NULL");
296 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
298 /* get pointers to arch-specific information */
299 armv4_5_common_t *armv4_5 = target->arch_info;
300 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
301 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
303 /* save r0 before using it and put system in ARM state
304 * to allow common handling of ARM and THUMB debugging */
306 /* fetch STR r0, [r0] */
307 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
308 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
309 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
310 /* nothing fetched, STR r0, [r0] in Execute (2) */
311 arm7tdmi_clock_data_in(jtag_info, r0);
313 /* MOV r0, r15 fetched, STR in Decode */
314 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
315 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
316 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
317 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
318 /* nothing fetched, STR r0, [r0] in Execute (2) */
319 arm7tdmi_clock_data_in(jtag_info, pc);
321 /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
322 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
323 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
324 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
325 /* nothing fetched, data for LDR r0, [PC, #0] */
326 arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
327 /* nothing fetched, data from previous cycle is written to register */
328 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
331 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
332 /* NOP fetched, BX in Decode, MOV in Execute */
333 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
334 /* NOP fetched, BX in Execute (1) */
335 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
337 jtag_execute_queue();
339 /* fix program counter:
340 * MOV r0, r15 was the 4th instruction (+6)
341 * reading PC in Thumb state gives address of instruction + 4
347 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
350 /* get pointers to arch-specific information */
351 armv4_5_common_t *armv4_5 = target->arch_info;
352 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
353 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
355 /* STMIA r0-15, [r0] at debug speed
356 * register values will start to appear on 4th DCLK
358 arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
360 /* fetch NOP, STM in DECODE stage */
361 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
362 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
363 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
365 for (i = 0; i <= 15; i++)
368 /* nothing fetched, STM still in EXECUTE (1+i cycle) */
369 arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
374 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
377 /* get pointers to arch-specific information */
378 armv4_5_common_t *armv4_5 = target->arch_info;
379 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
380 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
381 int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
382 u32 *buf_u32 = buffer;
383 u16 *buf_u16 = buffer;
386 /* STMIA r0-15, [r0] at debug speed
387 * register values will start to appear on 4th DCLK
389 arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
391 /* fetch NOP, STM in DECODE stage */
392 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
393 /* fetch NOP, STM in EXECUTE stage (1st cycle) */
394 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
396 for (i = 0; i <= 15; i++)
398 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
404 arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
407 arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
410 arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
418 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
420 /* get pointers to arch-specific information */
421 armv4_5_common_t *armv4_5 = target->arch_info;
422 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
423 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
426 arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
429 arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
430 /* fetch NOP, STR in DECODE stage */
431 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
432 /* fetch NOP, STR in EXECUTE stage (1st cycle) */
433 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
434 /* nothing fetched, STR still in EXECUTE (2nd cycle) */
435 arm7tdmi_clock_data_in(jtag_info, xpsr);
439 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
441 /* get pointers to arch-specific information */
442 armv4_5_common_t *armv4_5 = target->arch_info;
443 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
444 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
446 LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
449 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
450 /* MSR2 fetched, MSR1 in DECODE */
451 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
452 /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
453 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
454 /* nothing fetched, MSR1 in EXECUTE (2) */
455 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
456 /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
457 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
458 /* nothing fetched, MSR2 in EXECUTE (2) */
459 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
460 /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
461 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
462 /* nothing fetched, MSR3 in EXECUTE (2) */
463 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
464 /* NOP fetched, MSR4 in EXECUTE (1) */
465 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
466 /* nothing fetched, MSR4 in EXECUTE (2) */
467 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
470 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
472 /* get pointers to arch-specific information */
473 armv4_5_common_t *armv4_5 = target->arch_info;
474 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
475 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
477 LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
480 arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
481 /* NOP fetched, MSR in DECODE */
482 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
483 /* NOP fetched, MSR in EXECUTE (1) */
484 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
485 /* nothing fetched, MSR in EXECUTE (2) */
486 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
490 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
493 /* get pointers to arch-specific information */
494 armv4_5_common_t *armv4_5 = target->arch_info;
495 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
496 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
498 /* LDMIA r0-15, [r0] at debug speed
499 * register values will start to appear on 4th DCLK
501 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
503 /* fetch NOP, LDM in DECODE stage */
504 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
505 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
506 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
508 for (i = 0; i <= 15; i++)
511 /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
512 arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
514 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
518 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
520 /* get pointers to arch-specific information */
521 armv4_5_common_t *armv4_5 = target->arch_info;
522 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
523 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
525 /* put system-speed load-multiple into the pipeline */
526 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
527 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
528 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
532 void arm7tdmi_load_hword_reg(target_t *target, int num)
534 /* get pointers to arch-specific information */
535 armv4_5_common_t *armv4_5 = target->arch_info;
536 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
537 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
539 /* put system-speed load half-word into the pipeline */
540 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
541 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
542 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
546 void arm7tdmi_load_byte_reg(target_t *target, int num)
548 /* get pointers to arch-specific information */
549 armv4_5_common_t *armv4_5 = target->arch_info;
550 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
551 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
553 /* put system-speed load byte into the pipeline */
554 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
555 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
556 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
560 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
562 /* get pointers to arch-specific information */
563 armv4_5_common_t *armv4_5 = target->arch_info;
564 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
565 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
567 /* put system-speed store-multiple into the pipeline */
568 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
569 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
570 arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
574 void arm7tdmi_store_hword_reg(target_t *target, int num)
576 /* get pointers to arch-specific information */
577 armv4_5_common_t *armv4_5 = target->arch_info;
578 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
579 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
581 /* put system-speed store half-word into the pipeline */
582 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
583 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
584 arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
588 void arm7tdmi_store_byte_reg(target_t *target, int num)
590 /* get pointers to arch-specific information */
591 armv4_5_common_t *armv4_5 = target->arch_info;
592 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
593 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
595 /* put system-speed store byte into the pipeline */
596 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
597 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
598 arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
602 void arm7tdmi_write_pc(target_t *target, u32 pc)
604 /* get pointers to arch-specific information */
605 armv4_5_common_t *armv4_5 = target->arch_info;
606 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
607 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
609 /* LDMIA r0-15, [r0] at debug speed
610 * register values will start to appear on 4th DCLK
612 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
613 /* fetch NOP, LDM in DECODE stage */
614 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
615 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
616 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
617 /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
618 arm7tdmi_clock_out_inner(jtag_info, pc, 0);
619 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
620 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
621 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
622 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
623 /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
624 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
625 /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
626 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
629 void arm7tdmi_branch_resume(target_t *target)
631 /* get pointers to arch-specific information */
632 armv4_5_common_t *armv4_5 = target->arch_info;
633 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
634 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
636 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
637 arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
641 void arm7tdmi_branch_resume_thumb(target_t *target)
645 /* get pointers to arch-specific information */
646 armv4_5_common_t *armv4_5 = target->arch_info;
647 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
648 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
649 reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
651 /* LDMIA r0, [r0] at debug speed
652 * register values will start to appear on 4th DCLK
654 arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
656 /* fetch NOP, LDM in DECODE stage */
657 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
658 /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
659 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
660 /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
661 arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
662 /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
663 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
665 /* Branch and eXchange */
666 arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
668 embeddedice_read_reg(dbg_stat);
670 /* fetch NOP, BX in DECODE stage */
671 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
673 /* target is now in Thumb state */
674 embeddedice_read_reg(dbg_stat);
676 /* fetch NOP, BX in EXECUTE stage (1st cycle) */
677 arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
679 /* target is now in Thumb state */
680 embeddedice_read_reg(dbg_stat);
683 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
684 /* fetch NOP, LDR in Decode */
685 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
686 /* fetch NOP, LDR in Execute */
687 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
688 /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
689 arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
690 /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
691 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
693 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
694 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
696 embeddedice_read_reg(dbg_stat);
698 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
699 arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
703 void arm7tdmi_build_reg_cache(target_t *target)
705 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
706 /* get pointers to arch-specific information */
707 armv4_5_common_t *armv4_5 = target->arch_info;
709 (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
710 armv4_5->core_cache = (*cache_p);
713 int arm7tdmi_examine(struct target_s *target)
716 armv4_5_common_t *armv4_5 = target->arch_info;
717 arm7_9_common_t *arm7_9 = armv4_5->arch_info;
718 if (!target->type->examined)
720 /* get pointers to arch-specific information */
721 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
722 reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
727 arm7_9->eice_cache = (*cache_p);
731 arm_jtag_t *jtag_info = &arm7_9->jtag_info;
732 (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
733 arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
735 target->type->examined = 1;
737 if ((retval=embeddedice_setup(target))!=ERROR_OK)
739 if ((retval=arm7_9_setup(target))!=ERROR_OK)
743 if ((retval=etm_setup(target))!=ERROR_OK)
749 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
752 arm7tdmi_build_reg_cache(target);
758 int arm7tdmi_quit(void)
764 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int chain_pos, const char *variant)
766 armv4_5_common_t *armv4_5;
767 arm7_9_common_t *arm7_9;
769 arm7_9 = &arm7tdmi->arm7_9_common;
770 armv4_5 = &arm7_9->armv4_5_common;
772 /* prepare JTAG information for the new target */
773 arm7_9->jtag_info.chain_pos = chain_pos;
774 arm7_9->jtag_info.scann_size = 4;
776 /* register arch-specific functions */
777 arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
778 arm7_9->change_to_arm = arm7tdmi_change_to_arm;
779 arm7_9->read_core_regs = arm7tdmi_read_core_regs;
780 arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
781 arm7_9->read_xpsr = arm7tdmi_read_xpsr;
783 arm7_9->write_xpsr = arm7tdmi_write_xpsr;
784 arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
785 arm7_9->write_core_regs = arm7tdmi_write_core_regs;
787 arm7_9->load_word_regs = arm7tdmi_load_word_regs;
788 arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
789 arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
791 arm7_9->store_word_regs = arm7tdmi_store_word_regs;
792 arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
793 arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
795 arm7_9->write_pc = arm7tdmi_write_pc;
796 arm7_9->branch_resume = arm7tdmi_branch_resume;
797 arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
799 arm7_9->enable_single_step = arm7_9_enable_eice_step;
800 arm7_9->disable_single_step = arm7_9_disable_eice_step;
802 arm7_9->pre_debug_entry = NULL;
803 arm7_9->post_debug_entry = NULL;
805 arm7_9->pre_restore_context = NULL;
806 arm7_9->post_restore_context = NULL;
808 /* initialize arch-specific breakpoint handling */
809 arm7_9->arm_bkpt = 0xdeeedeee;
810 arm7_9->thumb_bkpt = 0xdeee;
812 arm7_9->dbgreq_adjust_pc = 2;
813 arm7_9->arch_info = arm7tdmi;
815 arm7tdmi->arch_info = NULL;
816 arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
820 arm7tdmi->variant = strdup(variant);
824 arm7tdmi->variant = strdup("");
827 arm7_9_init_arch_info(target, arm7_9);
832 /* target arm7tdmi <endianess> <startup_mode> <chain_pos> <variant> */
833 int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target)
836 char *variant = NULL;
837 arm7tdmi_common_t *arm7tdmi = malloc(sizeof(arm7tdmi_common_t));
838 memset(arm7tdmi, 0, sizeof(*arm7tdmi));
842 LOG_ERROR("'target arm7tdmi' requires at least one additional argument");
846 chain_pos = strtoul(args[3], NULL, 0);
851 arm7tdmi_init_arch_info(target, arm7tdmi, chain_pos, variant);
856 int arm7tdmi_target_create(Jim_Interp *interp,
857 struct target_s *target)
859 arm7tdmi_common_t *arm7tdmi;
861 arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
863 arm7tdmi_init_arch_info(target, arm7tdmi, target->chain_position, target->variant);
870 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
874 retval = arm7_9_register_commands(cmd_ctx);
882 * Local Variables: ***
883 * c-basic-offset: 4 ***