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   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifdef HAVE_CONFIG_H
  27 #include "config.h"
  28 #endif
  29
  30 #include "arm7tdmi.h"
  31
  32 #include "arm7_9_common.h"
  33 #include "register.h"
  34 #include "target.h"
  35 #include "armv4_5.h"
  36 #include "embeddedice.h"
  37 #include "etm.h"
  38 #include "log.h"
  39 #include "jtag.h"
  40 #include "arm_jtag.h"
  41
  42 #include <stdlib.h>
  43 #include <string.h>
  44
  45 #if 0
  46 #define _DEBUG_INSTRUCTION_EXECUTION_
  47 #endif
  48
  49 /* forward declarations */
  50
  51 int arm7tdmi_target_create(struct target_s *target,Jim_Interp *interp);
  52 int arm7tdmi_quit(void);
  53
  54 /* target function declarations */
  55 int arm7tdmi_poll(struct target_s *target);
  56 int arm7tdmi_halt(target_t *target);
  57
  58 target_type_t arm7tdmi_target =
  59 {
  60         .name = "arm7tdmi",
  61
  62         .poll = arm7_9_poll,
  63         .arch_state = armv4_5_arch_state,
  64
  65         .target_request_data = arm7_9_target_request_data,
  66
  67         .halt = arm7_9_halt,
  68         .resume = arm7_9_resume,
  69         .step = arm7_9_step,
  70
  71         .assert_reset = arm7_9_assert_reset,
  72         .deassert_reset = arm7_9_deassert_reset,
  73         .soft_reset_halt = arm7_9_soft_reset_halt,
  74
  75         .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
  76
  77         .read_memory = arm7_9_read_memory,
  78         .write_memory = arm7_9_write_memory,
  79         .bulk_write_memory = arm7_9_bulk_write_memory,
  80         .checksum_memory = arm7_9_checksum_memory,
  81         .blank_check_memory = arm7_9_blank_check_memory,
  82
  83         .run_algorithm = armv4_5_run_algorithm,
  84
  85         .add_breakpoint = arm7_9_add_breakpoint,
  86         .remove_breakpoint = arm7_9_remove_breakpoint,
  87         .add_watchpoint = arm7_9_add_watchpoint,
  88         .remove_watchpoint = arm7_9_remove_watchpoint,
  89
  90         .register_commands  = arm7tdmi_register_commands,
  91         .target_create  = arm7tdmi_target_create,
  92         .init_target = arm7tdmi_init_target,
  93         .examine = arm7tdmi_examine,
  94         .quit = arm7tdmi_quit
  95 };
  96
  97 int arm7tdmi_examine_debug_reason(target_t *target)
  98 {
  99         int retval = ERROR_OK;
 100         /* get pointers to arch-specific information */
 101         armv4_5_common_t *armv4_5 = target->arch_info;
 102         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 103
 104         /* only check the debug reason if we don't know it already */
 105         if ((target->debug_reason != DBG_REASON_DBGRQ)
 106                         && (target->debug_reason != DBG_REASON_SINGLESTEP))
 107         {
 108                 scan_field_t fields[2];
 109                 u8 databus[4];
 110                 u8 breakpoint;
 111
 112                 jtag_add_end_state(TAP_DRPAUSE);
 113
 114                 fields[0].tap = arm7_9->jtag_info.tap;
 115                 fields[0].num_bits = 1;
 116                 fields[0].out_value = NULL;
 117                 fields[0].in_value = &breakpoint;
 118                 fields[0].in_handler = NULL;
 119
 120                 fields[1].tap = arm7_9->jtag_info.tap;
 121                 fields[1].num_bits = 32;
 122                 fields[1].out_value = NULL;
 123                 fields[1].in_value = databus;
 124                 fields[1].in_handler = NULL;
 125
 126                 if((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
 127                 {
 128                         return retval;
 129                 }
 130                 arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 131
 132                 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
 133                 if((retval = jtag_execute_queue()) != ERROR_OK)
 134                 {
 135                         return retval;
 136                 }
 137
 138                 fields[0].in_value = NULL;
 139                 fields[0].out_value = &breakpoint;
 140                 fields[1].in_value = NULL;
 141                 fields[1].out_value = databus;
 142
 143                 jtag_add_dr_scan(2, fields, TAP_DRPAUSE);
 144
 145                 if (breakpoint & 1)
 146                         target->debug_reason = DBG_REASON_WATCHPOINT;
 147                 else
 148                         target->debug_reason = DBG_REASON_BREAKPOINT;
 149         }
 150
 151         return ERROR_OK;
 152 }
 153
 154 static int arm7tdmi_num_bits[]={1, 32};
 155 static __inline int arm7tdmi_clock_out_inner(arm_jtag_t *jtag_info, u32 out, int breakpoint)
 156 {
 157         u32 values[2]={breakpoint, flip_u32(out, 32)};
 158
 159         jtag_add_dr_out(jtag_info->tap,
 160                         2,
 161                         arm7tdmi_num_bits,
 162                         values,
 163                         TAP_INVALID);
 164
 165         jtag_add_runtest(0, TAP_INVALID);
 166
 167         return ERROR_OK;
 168 }
 169
 170 /* put an instruction in the ARM7TDMI pipeline or write the data bus, and optionally read data */
 171 static __inline int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *deprecated, int breakpoint)
 172 {
 173         jtag_add_end_state(TAP_DRPAUSE);
 174         arm_jtag_scann(jtag_info, 0x1);
 175         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 176
 177         return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 178 }
 179
 180 /* clock the target, reading the databus */
 181 int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
 182 {
 183         int retval = ERROR_OK;
 184         scan_field_t fields[2];
 185
 186         jtag_add_end_state(TAP_DRPAUSE);
 187         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 188         {
 189                 return retval;
 190         }
 191         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 192
 193         fields[0].tap = jtag_info->tap;
 194         fields[0].num_bits = 1;
 195         fields[0].out_value = NULL;
 196         fields[0].in_value = NULL;
 197         fields[0].in_handler = NULL;
 198
 199
 200         fields[1].tap = jtag_info->tap;
 201         fields[1].num_bits = 32;
 202         fields[1].out_value = NULL;
 203         u8 tmp[4];
 204         fields[1].in_value = tmp;
 205         fields[1].in_handler = NULL;
 206
 207         jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 208
 209         if (jtag_error==ERROR_OK)
 210         {
 211                 *in=flip_u32(le_to_h_u32(tmp), 32);
 212         }
 213
 214         jtag_add_runtest(0, TAP_INVALID);
 215
 216 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 217 {
 218                 if((retval = jtag_execute_queue()) != ERROR_OK)
 219                 {
 220                         return retval;
 221                 }
 222
 223                 if (in)
 224                 {
 225                         LOG_DEBUG("in: 0x%8.8x", *in);
 226                 }
 227                 else
 228                 {
 229                         LOG_ERROR("BUG: called with in == NULL");
 230                 }
 231 }
 232 #endif
 233
 234         return ERROR_OK;
 235 }
 236
 237 /* clock the target, and read the databus
 238  * the *in pointer points to a buffer where elements of 'size' bytes
 239  * are stored in big (be==1) or little (be==0) endianness
 240  */
 241 int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
 242 {
 243         int retval = ERROR_OK;
 244         scan_field_t fields[2];
 245
 246         jtag_add_end_state(TAP_DRPAUSE);
 247         if((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
 248         {
 249                 return retval;
 250         }
 251         arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
 252
 253         fields[0].tap = jtag_info->tap;
 254         fields[0].num_bits = 1;
 255         fields[0].out_value = NULL;
 256         fields[0].in_value = NULL;
 257         fields[0].in_handler = NULL;
 258
 259         fields[1].tap = jtag_info->tap;
 260         fields[1].num_bits = 32;
 261         fields[1].out_value = NULL;
 262         u8 tmp[4];
 263         fields[1].in_value = tmp;
 264         fields[1].in_handler = NULL;
 265
 266         jtag_add_dr_scan_now(2, fields, TAP_INVALID);
 267
 268         u32 readback=flip_u32(le_to_h_u32(tmp), 32);
 269         switch (size)
 270         {
 271                 case 4:
 272                         if (be)
 273                         {
 274                                 h_u32_to_be(((u8*)in), readback);
 275                         } else
 276                         {
 277                                  h_u32_to_le(((u8*)in), readback);
 278                         }
 279                         break;
 280                 case 2:
 281                         if (be)
 282                         {
 283                                 h_u16_to_be(((u8*)in), readback & 0xffff);
 284                         } else
 285                         {
 286                                 h_u16_to_le(((u8*)in), readback & 0xffff);
 287                         }
 288                         break;
 289                 case 1:
 290                         *((u8 *)in)= readback & 0xff;
 291                         break;
 292         }
 293
 294         jtag_add_runtest(0, TAP_INVALID);
 295
 296 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 297 {
 298                 if((retval = jtag_execute_queue()) != ERROR_OK)
 299                 {
 300                         return retval;
 301                 }
 302
 303                 if (in)
 304                 {
 305                         LOG_DEBUG("in: 0x%8.8x", *(u32*)in);
 306                 }
 307                 else
 308                 {
 309                         LOG_ERROR("BUG: called with in == NULL");
 310                 }
 311 }
 312 #endif
 313
 314         return ERROR_OK;
 315 }
 316
 317 void arm7tdmi_change_to_arm(target_t *target, u32 *r0, u32 *pc)
 318 {
 319         /* get pointers to arch-specific information */
 320         armv4_5_common_t *armv4_5 = target->arch_info;
 321         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 322         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 323
 324         /* save r0 before using it and put system in ARM state
 325          * to allow common handling of ARM and THUMB debugging */
 326
 327         /* fetch STR r0, [r0] */
 328         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 329         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 330         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 331         /* nothing fetched, STR r0, [r0] in Execute (2) */
 332         arm7tdmi_clock_data_in(jtag_info, r0);
 333
 334         /* MOV r0, r15 fetched, STR in Decode */
 335         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_MOV(0, 15), NULL, 0);
 336         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_STR(0, 0), NULL, 0);
 337         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 338         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 339         /* nothing fetched, STR r0, [r0] in Execute (2) */
 340         arm7tdmi_clock_data_in(jtag_info, pc);
 341
 342         /* use pc-relative LDR to clear r0[1:0] (for switch to ARM mode) */
 343         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 344         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 345         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 346         /* nothing fetched, data for LDR r0, [PC, #0] */
 347         arm7tdmi_clock_out(jtag_info, 0x0, NULL, 0);
 348         /* nothing fetched, data from previous cycle is written to register */
 349         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 350
 351         /* fetch BX */
 352         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_BX(0), NULL, 0);
 353         /* NOP fetched, BX in Decode, MOV in Execute */
 354         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 355         /* NOP fetched, BX in Execute (1) */
 356         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 357
 358         jtag_execute_queue();
 359
 360         /* fix program counter:
 361          * MOV r0, r15 was the 4th instruction (+6)
 362          * reading PC in Thumb state gives address of instruction + 4
 363          */
 364         *pc -= 0xa;
 365 }
 366
 367 void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
 368 {
 369         int i;
 370         /* get pointers to arch-specific information */
 371         armv4_5_common_t *armv4_5 = target->arch_info;
 372         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 373         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 374
 375         /* STMIA r0-15, [r0] at debug speed
 376          * register values will start to appear on 4th DCLK
 377          */
 378         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 379
 380         /* fetch NOP, STM in DECODE stage */
 381         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 382         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 383         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 384
 385         for (i = 0; i <= 15; i++)
 386         {
 387                 if (mask & (1 << i))
 388                         /* nothing fetched, STM still in EXECUTE (1+i cycle) */
 389                         arm7tdmi_clock_data_in(jtag_info, core_regs[i]);
 390         }
 391 }
 392
 393 void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
 394 {
 395         int i;
 396         /* get pointers to arch-specific information */
 397         armv4_5_common_t *armv4_5 = target->arch_info;
 398         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 399         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 400         int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
 401         u32 *buf_u32 = buffer;
 402         u16 *buf_u16 = buffer;
 403         u8 *buf_u8 = buffer;
 404
 405         /* STMIA r0-15, [r0] at debug speed
 406          * register values will start to appear on 4th DCLK
 407          */
 408         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 409
 410         /* fetch NOP, STM in DECODE stage */
 411         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 412         /* fetch NOP, STM in EXECUTE stage (1st cycle) */
 413         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 414
 415         for (i = 0; i <= 15; i++)
 416         {
 417                 /* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
 418                 if (mask & (1 << i))
 419                 {
 420                         switch (size)
 421                         {
 422                                 case 4:
 423                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
 424                                         break;
 425                                 case 2:
 426                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
 427                                         break;
 428                                 case 1:
 429                                         arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
 430                                         break;
 431                         }
 432                 }
 433         }
 434 }
 435
 436 void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
 437 {
 438         /* get pointers to arch-specific information */
 439         armv4_5_common_t *armv4_5 = target->arch_info;
 440         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 441         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 442
 443         /* MRS r0, cpsr */
 444         arm7tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), NULL, 0);
 445
 446         /* STR r0, [r15] */
 447         arm7tdmi_clock_out(jtag_info, ARMV4_5_STR(0, 15), NULL, 0);
 448         /* fetch NOP, STR in DECODE stage */
 449         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 450         /* fetch NOP, STR in EXECUTE stage (1st cycle) */
 451         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 452         /* nothing fetched, STR still in EXECUTE (2nd cycle) */
 453         arm7tdmi_clock_data_in(jtag_info, xpsr);
 454 }
 455
 456 void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
 457 {
 458         /* get pointers to arch-specific information */
 459         armv4_5_common_t *armv4_5 = target->arch_info;
 460         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 461         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 462
 463         LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
 464
 465         /* MSR1 fetched */
 466         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
 467         /* MSR2 fetched, MSR1 in DECODE */
 468         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff00) >> 8, 0xc, 2, spsr), NULL, 0);
 469         /* MSR3 fetched, MSR1 in EXECUTE (1), MSR2 in DECODE */
 470         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff0000) >> 16, 0x8, 4, spsr), NULL, 0);
 471         /* nothing fetched, MSR1 in EXECUTE (2) */
 472         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 473         /* MSR4 fetched, MSR2 in EXECUTE (1), MSR3 in DECODE */
 474         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM((xpsr & 0xff000000) >> 24, 0x4, 8, spsr), NULL, 0);
 475         /* nothing fetched, MSR2 in EXECUTE (2) */
 476         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 477         /* NOP fetched, MSR3 in EXECUTE (1), MSR4 in DECODE */
 478         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 479         /* nothing fetched, MSR3 in EXECUTE (2) */
 480         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 481         /* NOP fetched, MSR4 in EXECUTE (1) */
 482         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 483         /* nothing fetched, MSR4 in EXECUTE (2) */
 484         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 485 }
 486
 487 void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
 488 {
 489         /* get pointers to arch-specific information */
 490         armv4_5_common_t *armv4_5 = target->arch_info;
 491         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 492         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 493
 494         LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
 495
 496         /* MSR fetched */
 497         arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
 498         /* NOP fetched, MSR in DECODE */
 499         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 500         /* NOP fetched, MSR in EXECUTE (1) */
 501         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 502         /* nothing fetched, MSR in EXECUTE (2) */
 503         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 504 }
 505
 506 void arm7tdmi_write_core_regs(target_t *target, u32 mask, u32 core_regs[16])
 507 {
 508         int i;
 509         /* get pointers to arch-specific information */
 510         armv4_5_common_t *armv4_5 = target->arch_info;
 511         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 512         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 513
 514         /* LDMIA r0-15, [r0] at debug speed
 515         * register values will start to appear on 4th DCLK
 516         */
 517         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), NULL, 0);
 518
 519         /* fetch NOP, LDM in DECODE stage */
 520         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 521         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 522         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 523
 524         for (i = 0; i <= 15; i++)
 525         {
 526                 if (mask & (1 << i))
 527                         /* nothing fetched, LDM still in EXECUTE (1+i cycle) */
 528                         arm7tdmi_clock_out_inner(jtag_info, core_regs[i], 0);
 529         }
 530         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 531 }
 532
 533 void arm7tdmi_load_word_regs(target_t *target, u32 mask)
 534 {
 535         /* get pointers to arch-specific information */
 536         armv4_5_common_t *armv4_5 = target->arch_info;
 537         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 538         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 539
 540         /* put system-speed load-multiple into the pipeline */
 541         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 542         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 543         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 1), NULL, 0);
 544 }
 545
 546 void arm7tdmi_load_hword_reg(target_t *target, int num)
 547 {
 548         /* get pointers to arch-specific information */
 549         armv4_5_common_t *armv4_5 = target->arch_info;
 550         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 551         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 552
 553         /* put system-speed load half-word into the pipeline */
 554         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 555         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 556         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRH_IP(num, 0), NULL, 0);
 557 }
 558
 559 void arm7tdmi_load_byte_reg(target_t *target, int num)
 560 {
 561         /* get pointers to arch-specific information */
 562         armv4_5_common_t *armv4_5 = target->arch_info;
 563         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 564         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 565
 566         /* put system-speed load byte into the pipeline */
 567         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 568         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 569         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDRB_IP(num, 0), NULL, 0);
 570 }
 571
 572 void arm7tdmi_store_word_regs(target_t *target, u32 mask)
 573 {
 574         /* get pointers to arch-specific information */
 575         armv4_5_common_t *armv4_5 = target->arch_info;
 576         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 577         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 578
 579         /* put system-speed store-multiple into the pipeline */
 580         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 581         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 582         arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask, 0, 1), NULL, 0);
 583 }
 584
 585 void arm7tdmi_store_hword_reg(target_t *target, int num)
 586 {
 587         /* get pointers to arch-specific information */
 588         armv4_5_common_t *armv4_5 = target->arch_info;
 589         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 590         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 591
 592         /* put system-speed store half-word into the pipeline */
 593         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 594         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 595         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRH_IP(num, 0), NULL, 0);
 596 }
 597
 598 void arm7tdmi_store_byte_reg(target_t *target, int num)
 599 {
 600         /* get pointers to arch-specific information */
 601         armv4_5_common_t *armv4_5 = target->arch_info;
 602         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 603         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 604
 605         /* put system-speed store byte into the pipeline */
 606         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 607         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 608         arm7tdmi_clock_out(jtag_info, ARMV4_5_STRB_IP(num, 0), NULL, 0);
 609 }
 610
 611 void arm7tdmi_write_pc(target_t *target, u32 pc)
 612 {
 613         /* get pointers to arch-specific information */
 614         armv4_5_common_t *armv4_5 = target->arch_info;
 615         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 616         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 617
 618         /* LDMIA r0-15, [r0] at debug speed
 619          * register values will start to appear on 4th DCLK
 620          */
 621         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x8000, 0, 0), NULL, 0);
 622         /* fetch NOP, LDM in DECODE stage */
 623         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 624         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 625         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 626         /* nothing fetched, LDM in EXECUTE stage (1st cycle) load register */
 627         arm7tdmi_clock_out_inner(jtag_info, pc, 0);
 628         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) load register */
 629         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 630         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) load register */
 631         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 632         /* fetch NOP, LDM in EXECUTE stage (4th cycle) */
 633         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 634         /* fetch NOP, LDM in EXECUTE stage (5th cycle) */
 635         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_NOP, 0);
 636 }
 637
 638 void arm7tdmi_branch_resume(target_t *target)
 639 {
 640         /* get pointers to arch-specific information */
 641         armv4_5_common_t *armv4_5 = target->arch_info;
 642         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 643         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 644
 645         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 1);
 646         arm7tdmi_clock_out_inner(jtag_info, ARMV4_5_B(0xfffffa, 0), 0);
 647 }
 648
 649 void arm7tdmi_branch_resume_thumb(target_t *target)
 650 {
 651         LOG_DEBUG("-");
 652
 653         /* get pointers to arch-specific information */
 654         armv4_5_common_t *armv4_5 = target->arch_info;
 655         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 656         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 657         reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 658
 659         /* LDMIA r0, [r0] at debug speed
 660          * register values will start to appear on 4th DCLK
 661          */
 662         arm7tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 0x1, 0, 0), NULL, 0);
 663
 664         /* fetch NOP, LDM in DECODE stage */
 665         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 666         /* fetch NOP, LDM in EXECUTE stage (1st cycle) */
 667         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 668         /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */
 669         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) | 1, NULL, 0);
 670         /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */
 671         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 672
 673         /* Branch and eXchange */
 674         arm7tdmi_clock_out(jtag_info, ARMV4_5_BX(0), NULL, 0);
 675
 676         embeddedice_read_reg(dbg_stat);
 677
 678         /* fetch NOP, BX in DECODE stage */
 679         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 680
 681         /* target is now in Thumb state */
 682         embeddedice_read_reg(dbg_stat);
 683
 684         /* fetch NOP, BX in EXECUTE stage (1st cycle) */
 685         arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
 686
 687         /* target is now in Thumb state */
 688         embeddedice_read_reg(dbg_stat);
 689
 690         /* load r0 value */
 691         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_LDR_PCREL(0), NULL, 0);
 692         /* fetch NOP, LDR in Decode */
 693         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 694         /* fetch NOP, LDR in Execute */
 695         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 696         /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */
 697         arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0);
 698         /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */
 699         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 700
 701         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 702         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0);
 703
 704         embeddedice_read_reg(dbg_stat);
 705
 706         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 1);
 707         arm7tdmi_clock_out(jtag_info, ARMV4_5_T_B(0x7f8), NULL, 0);
 708 }
 709
 710 void arm7tdmi_build_reg_cache(target_t *target)
 711 {
 712         reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 713         /* get pointers to arch-specific information */
 714         armv4_5_common_t *armv4_5 = target->arch_info;
 715
 716         (*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
 717         armv4_5->core_cache = (*cache_p);
 718 }
 719
 720 int arm7tdmi_examine(struct target_s *target)
 721 {
 722         int retval;
 723         armv4_5_common_t *armv4_5 = target->arch_info;
 724         arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 725         if (!target->type->examined)
 726         {
 727                 /* get pointers to arch-specific information */
 728                 reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
 729                 reg_cache_t *t=embeddedice_build_reg_cache(target, arm7_9);
 730                 if (t==NULL)
 731                         return ERROR_FAIL;
 732
 733                 (*cache_p) = t;
 734                 arm7_9->eice_cache = (*cache_p);
 735
 736                 if (arm7_9->etm_ctx)
 737                 {
 738                         arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 739                         (*cache_p)->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
 740                         arm7_9->etm_ctx->reg_cache = (*cache_p)->next;
 741                 }
 742                 target->type->examined = 1;
 743         }
 744         if ((retval=embeddedice_setup(target))!=ERROR_OK)
 745                 return retval;
 746         if ((retval=arm7_9_setup(target))!=ERROR_OK)
 747                 return retval;
 748         if (arm7_9->etm_ctx)
 749         {
 750                 if ((retval=etm_setup(target))!=ERROR_OK)
 751                         return retval;
 752         }
 753         return ERROR_OK;
 754 }
 755
 756 int arm7tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
 757 {
 758         arm7tdmi_build_reg_cache(target);
 759
 760         return ERROR_OK;
 761 }
 762
 763 int arm7tdmi_quit(void)
 764 {
 765         return ERROR_OK;
 766 }
 767
 768 int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_tap_t *tap)
 769 {
 770         armv4_5_common_t *armv4_5;
 771         arm7_9_common_t *arm7_9;
 772
 773         arm7_9 = &arm7tdmi->arm7_9_common;
 774         armv4_5 = &arm7_9->armv4_5_common;
 775
 776         /* prepare JTAG information for the new target */
 777         arm7_9->jtag_info.tap = tap;
 778         arm7_9->jtag_info.scann_size = 4;
 779
 780         /* register arch-specific functions */
 781         arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
 782         arm7_9->change_to_arm = arm7tdmi_change_to_arm;
 783         arm7_9->read_core_regs = arm7tdmi_read_core_regs;
 784         arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
 785         arm7_9->read_xpsr = arm7tdmi_read_xpsr;
 786
 787         arm7_9->write_xpsr = arm7tdmi_write_xpsr;
 788         arm7_9->write_xpsr_im8 = arm7tdmi_write_xpsr_im8;
 789         arm7_9->write_core_regs = arm7tdmi_write_core_regs;
 790
 791         arm7_9->load_word_regs = arm7tdmi_load_word_regs;
 792         arm7_9->load_hword_reg = arm7tdmi_load_hword_reg;
 793         arm7_9->load_byte_reg = arm7tdmi_load_byte_reg;
 794
 795         arm7_9->store_word_regs = arm7tdmi_store_word_regs;
 796         arm7_9->store_hword_reg = arm7tdmi_store_hword_reg;
 797         arm7_9->store_byte_reg = arm7tdmi_store_byte_reg;
 798
 799         arm7_9->write_pc = arm7tdmi_write_pc;
 800         arm7_9->branch_resume = arm7tdmi_branch_resume;
 801         arm7_9->branch_resume_thumb = arm7tdmi_branch_resume_thumb;
 802
 803         arm7_9->enable_single_step = arm7_9_enable_eice_step;
 804         arm7_9->disable_single_step = arm7_9_disable_eice_step;
 805
 806         arm7_9->pre_debug_entry = NULL;
 807         arm7_9->post_debug_entry = NULL;
 808
 809         arm7_9->pre_restore_context = NULL;
 810         arm7_9->post_restore_context = NULL;
 811
 812         /* initialize arch-specific breakpoint handling */
 813         arm7_9->arm_bkpt = 0xdeeedeee;
 814         arm7_9->thumb_bkpt = 0xdeee;
 815
 816         arm7_9->dbgreq_adjust_pc = 2;
 817         arm7_9->arch_info = arm7tdmi;
 818
 819         arm7tdmi->arch_info = NULL;
 820         arm7tdmi->common_magic = ARM7TDMI_COMMON_MAGIC;
 821
 822         arm7_9_init_arch_info(target, arm7_9);
 823
 824         return ERROR_OK;
 825 }
 826
 827 int arm7tdmi_target_create( struct target_s *target, Jim_Interp *interp )
 828 {
 829         arm7tdmi_common_t *arm7tdmi;
 830
 831         arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
 832         arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
 833
 834         return ERROR_OK;
 835 }
 836
 837 int arm7tdmi_register_commands(struct command_context_s *cmd_ctx)
 838 {
 839         int retval;
 840
 841         retval = arm7_9_register_commands(cmd_ctx);
 842
 843         return retval;
 844 }